DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-5, 7-14, and 16-20 are pending.
Claims 1, 9, and 14 have been amended.
This action is Final.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-11 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khasawneh et al. (hereinafter as Khasawneh) PGPUB 2022/0197856, and further in view of Lee et al. (hereinafter as Lee) PGPUB 2021/0067335 and Morris PGPUB 2007/0283239.
As per claim 1, Khasawneh teaches a method comprising:
detecting a context switch to a first operating system process [FIG. 3 step 320 and 0043: (request is received to start execution of a given application (first operating system process); this is considered a context switch because it causes the processor to change its operation to perform execution of an application)];
responsive to detecting the context switch [FIG. 3: (based on the request to start an application in step 320, machine learning is performed in step 350) and 0034-0035: (based on identification of application and/or phase, machine learning is used to determine an updated configuration)], identifying the first operating system process based on an attribute of the first operating system process, the first operating system process having instructions configured to be executed by a processor core [FIG. 1, 0017, 0020, 0029, 0033, 0035, 0074-0075: (responsive to detecting an application executing (responsive to detecting the context switch), perform identification of a particular application (operating system process) based on monitoring information (attribute) and its phase in execution by CPU cores)];
determining a phase associated with the first operating system process [0033-0034 and 0045: (classification based on performance monitoring information to identify a particular workload and a particular application phase)];
determining a first set of parameters based on an attribute of the first operating system process and the phase [0017 and 0033-0034: (corresponding configuration (first set of parameters) provided based on the identification (attribute) and the phase of the application); and FIG. 3: (machine learning determines optimal configuration (first set of parameters) based on performance monitoring statistics (which includes identification of the application and phase) in step 350]; and
configuring a component of the processor core using the first set of parameters [FIG. 1 and 0034-0035 and 0045: (based on identified application, configuration information is used to configure the prefetcher circuit 140 (component of processor core)) and FIG. 3: (update configuration in step 360)].
Khasawneh does not explicitly teach the attribute including at least one of: an address space identifier (ASID), and address space, a range of memory addresses, or a virtual machine identifier (VMID); and wherein determining the first set of parameters comprises evaluating and selecting a particular model from a library of models based on the attribute of the first operating system process. Khasawneh describes identifying an application and its phase in execution using monitored information, but does not indicate that it uses ASID, address space, range of memory addresses, or a VMID to identify the application/operating system process. Khasawneh also teaches each model may be associated with a processor feature [0033], such as a processor feature to be configured or optimized for a particular application or phase of application, but Khasawneh does not explicitly teach evaluating and selecting a particular model based on the attribute such as an ASID.
Lee teaches an execution environment of a data processing apparatus. Lee is thus similar to Khasawneh. Lee further teaches the attribute including at least one of: an address space identifier (ASID), and address space, a range of memory addresses, or a virtual machine identifier (VMID) [0026: (an address space identifier may be used to identify a particular application instance executing on a data processing apparatus)]. Lee teaches that an ASID is used for identifying an application.
The combination of Khasawneh with Lee leads to Khasawneh identifying an application by reading the ASID.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Lee’s teachings of referring to the ASID to determine the identity of the application. Lee teaches the mechanism on how to identify an application in Khasawneh. One of ordinary skill in the art would have been motivated to refer to the ASID to identify the application in Khasawneh because applications are assigned an address space and ASID and are thus correlated, and so referring to an ASID would be another way to quickly refer to the application that is using such address space.
Khasawneh and Lee do not explicitly teach wherein determining the first set of parameters comprises evaluating and selecting a particular model from a library of models based on the attribute of the first operating system process.
Morris teaches determining a characteristic of an application executing on the device. Morris is thus similar to Khasawneh and Lee because they determine the status or property or identifier of the application. Morris further teaches wherein determining the first set of parameters comprises evaluating and selecting a particular model from a library of models [0029, 0034 and claim 7: (determining (evaluating and selecting) a model from among several models (library of models)] based on the attribute of the first operating system process [0036, claim 7, and claim 8: (based on state of application or application characteristic, a particular model is determined to be used from a plurality of models (evaluating and selecting a model from a library of models based on attribute/characteristic/state of operating system process/application))]. In summary, Morris selects a model from a plurality of models to use based on application characteristics of an application, where the user model define data and resources used by the application.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Morris’ teachings of selecting a model from a plurality of models according to application characteristics in Khasawneh and Lee. One of ordinary skill in the art would have been motivated to evaluate and select a particular model relevant to a particular application in Khasawneh and Lee from a plurality of models because it allows for more tailored or customized parameter adjustments according to the application being executed, thereby providing greater control and improved user experience.
As per claim 2, Khasawneh, Lee, and Morris teach the method of claim 1, further comprising: caching the first set of parameters in a memory system associated with the processor core [Khasawneh 0034: (configuration information (first set of parameters) is provided to one or more configuration registers 152 (caching to a memory system)].
As per claim 3, Khasawneh, Lee, and Morris teach the method of claim 1, wherein determining the first set of parameters includes: obtaining a cached set of parameters as the first set of parameters [Khasawneh 0034, 0046-0048: (various candidate configuration values in configuration system registers CSRs; when application is in a particular phase, configuration is used by control prefetcher circuit to prefetch data from a further portion of a memory circuit (obtaining cached set of parameters))].
As per claim 4, Khasawneh, Lee, and Morris teach the method of claim 1, wherein determining the first set of parameters includes: obtaining a cached set of parameters associated with the first operating system process [Khasawneh 0046 and 0053: (candidate configurations are obtained)]; obtaining profiling information regarding execution of the first operating system process [Khasawneh 0045-0048, 0053, and 0060: (determining metrics of candidate configurations for each phase of application (profiling information)]; and determining the first set of parameters based on the cached set of parameters and the profiling information [Khasawneh 0040, 0045, 0055, and 0060: (an optimal configuration (first set of parameters) is determined from the candidate configurations)].
As per claim 5, Khasawneh, Lee, and Morris teach the method of claim 1, further comprising: identifying a change to the phase associated with the first operating system process [Khasawneh 0021, 0025, and 0033-0034: (identifying a particular application phase, which means it detects the different phases in the application)]; updating the first set of parameters based on the phase [Khasawneh 0021, 0025, 0034-0035, 0038-0039, and 0046-0048: (configuration is fine tuned for each phase until an optimal configuration is determined)]; and re-configuring the component of the processor core using the updated first set of parameters [Khasawneh 0040 and 0045: (configuration settings may be provided to configuration registers that can be used to update configuration of the prefetcher using the determined optimal configuration as phase changes)].
As per claim 6, Khasawneh, Lee, and Morris teach the method of claim 1, wherein determining the first set of parameters comprises: selecting a model from a plurality of models, wherein the model is selected based on the attribute of the first operating system process [Khasawneh 0019 and 0033: (a plurality of models are provided; models may be tuned for different firmware versions or for particular application phase)]; and evaluating the model against a datum stored in a memory system associated with the processor core or a characteristic of the processor core to determine the first set of parameters [Khasawneh 0024, 0039, 0045, 0048, 0104, 0106, and claim 6: (machine learning algorithm determines optimal configuration using performance monitoring statistics and performing analysis on the metrics; cache memory metrics, such as rate of useless prefetches, is provided to the machine learning model to perform the analysis (e.g. evaluating the model against characteristic of the processor core/rate of useless prefetches)].
As per claim 7, Khasawneh, Lee, and Morris teach the method of claim 1, wherein determining the first set of parameters comprises: accessing a model comprising a plurality of parameters [Khasawneh 0018 and 0033-0034: (a machine learning model may provide various configuration information (plurality of parameters)], wherein the first set of parameters is selected from the plurality of parameters based on the first operating system process [Khasawneh 0034: (based on the identified application, machine learning model provides a configuration; for example, controlling the aggressiveness of a prefetcher circuit according to mode information of the configuration information)].
As per claim 8, Khasawneh, Lee, and Morris teach the method of claim 1, the method further comprising: executing a second operating system process, wherein the second operating system process determines the first set of parameters for the first operating system process [Khasawneh 0033-0034: (a machine learning model (second operating system process) is used to determine the configuration for the identified application)].
Claim 9 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
As per claim 10, Khasawneh, Lee, and Morris teach the apparatus of claim 9, wherein the processor core is configured to determine the first set of parameters by using microcode implemented by the processor core to determine the first set of parameters [Khasawneh 0041: microcode].
As per claim 11, Khasawneh, Lee, and Morris teach the apparatus of claim 9, wherein the component is one of a prefetcher, a branch predictor, a dispatch unit, a vector unit, or clock controller [Khasawneh 0034: prefetcher circuit].
Claim 14 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claim(s) 12-13 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khasawneh et al. (hereinafter as Khasawneh) PGPUB 2022/0197856 in view of Lee et al. (hereinafter as Lee) PGPUB 2021/0067335 and Morris PGPUB 2007/0283239, and further in view of Favor et al. (hereinafter as Favor) PGPUB 2022/0027467.
As per claim 12, Khasawneh, Lee, and Morris teach the apparatus of claim 9.
Khasawneh, Lee, and Morris do not explicitly teach wherein the processor core is configured to: access a table comprising a plurality of parameters, wherein the ASID is used to determine the first set of parameters from the plurality of parameters in the table. Although Khasawneh and Lee teach an ASID identifier, they do not mention using the ASID to determine parameters from a table.
Favor teaches a core processing threads in a pipeline that performs fetching and using ASID. Favor is thus similar to Khasawneh, Lee, and Morris. Favor further teaches wherein the processor core is configured to: access a table comprising a plurality of parameters, wherein the ASID is used to determine the first set of parameters from the plurality of parameters in the table [0041: (ASID may be associated with a table of processes; ASID may correspond to a processor context identifier which is used for determining different privilege modes of the core)]. Favor teaches the use of an ASID with a table to obtain a processor context identifier PCID that allows for setting in different privilege modes.
It would have been obvious to one of ordinary skill in the art before the effective filing date to use Favor’s teachings of referencing a table with an ASID to determine configuration in Khasawneh, Lee, and Morris. One of ordinary skill in the art would have been motivated to identify an application process and corresponding parameters/privileges of the core using ASID and a table in Khasawneh, Lee, and Morris because it allows the core to identify the thread or process and corresponding parameters while performing address translation, without needing additional resources to detect the identity of the process or thread.
As per claim 13, Khasawneh, Lee, and Morris teach the apparatus of claim 9.
Khasawneh, Lee, and Morris do not explicitly teach wherein the address space stored in a page table base register implemented by the processor core, and wherein the processor core is configured to: access a table comprising a plurality of parameters, wherein the page table base register is used to determine the first set of parameters from the plurality of parameters in the table.
Favor teaches a core processing threads in a pipeline that performs fetching. Favor is thus similar to Khasawneh, Lee, and Morris. Favor further teaches wherein the address space stored in a page table base register implemented by the processor core [0041: (process or thread running on core is identified by address space, which is referenced using an ASID)], and wherein the processor core is configured to: access a table comprising a plurality of parameters, wherein the page table base register is used to determine the first set of parameters from the plurality of parameters in the table [0041: (ASID may be associated with a table of processes; ASID may correspond to a processor context identifier which is used for determining different parameters/privilege modes of the core)]. Favor teaches the use of an ASID (representing an address space) with a table to obtain a processor context identifier PCID that allows for setting in different privilege modes.
It would have been obvious to one of ordinary skill in the art before the effective filing date to use Favor’s teachings of an attribute being an address space in Khasawneh, Lee, and Morris, and referencing a table with an ASID that represents the address space to determine configuration in Khasawneh, Lee, and Morris. One of ordinary skill in the art would have been motivated to identify an application process and corresponding parameters/privileges of the core using ASID representing the address space and a table in Khasawneh, Lee, and Morris because it allows the core to identify the thread or process and corresponding parameters while performing address translation, without needing additional resources to detect the identity of the process or thread.
As per claim 18, Khasawneh, Lee, and Morris teach the non-transitory computer readable medium storing instructions of claim 14.
Khasawneh, Lee, and Morris do not teach wherein the first operating system process is a hypervisor executing a guest operating system.
Favor teaches a core processing threads in a pipeline that performs fetching. Favor is thus similar to Khasawneh, Lee, and Morris. Favor further teaches teach wherein the first operating system process is a hypervisor executing a guest operating system [0019, 0041, and 0043] and the attribute of the first operating system process includes a virtual machine identifier (VMID) [0041-0044, and 0059-0060: VMID].
It would have been obvious to one of ordinary skill in the art before the effective filing date to use Favor’s teachings of a hypervisor and virtual machine identifier in Khasawneh, Lee, and Morris. One of ordinary skill in the art would have been motivated to provide a hypervisor executing a guest OS as an application and a virtual machine identifier in Khasawneh, Lee, and Morris because it allows Khasawneh, Lee, and Morris’ teachings to be extended to virtual machines, and selecting optimal configurations when the application being executed is a virtual machine.
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khasawneh et al. (hereinafter as Khasawneh) PGPUB 2022/0197856 in view of Lee et al. (hereinafter as Lee) PGPUB 2021/0067335 and Morris PGPUB 2007/0283239, and further in view of Cui PGPUB 2021/0124847.
As per claim 16, Khasawneh, Lee, and Morris teach the non-transitory computer readable medium storing instructions of claim 14.
Khasawneh, Lee, and Morris do not teach the operations further comprising: detecting the processor core executing to access a memory address within the range of memory addresses. Khasawneh, Lee, and Morris do not appear to describe identifying an application by the range of addresses.
Cui teaches a computing system that determines an application program ID. Cui is thus similar to Khasawneh, Lee, and Morris. Cui further teaches wherein the attribute is a range of memory addresses, the operations further comprising: detecting the processor core executing to access a memory address within the range of memory addresses [0028 and claim 8: (determining an application program ID based on the address range in which the application program is executed)]. Cui teaches determining the address range in which an application executes to determine the application ID.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Cui’s teachings of detecting an application ID/attribute based on the core accessing a memory address within a range of addresses in Khasawneh, Lee, and Morris. One of ordinary skill in the art would have been motivated to identify an application ID based on the memory addresses that are accessed in Khasawneh, Lee, and Morris because it is a quick and simple way to determine the application that is being run without relying on additional application identifiers and components to look up and compare application identifiers.
As per claim 17, Khasawneh, Lee, and Morris teach the non-transitory computer readable medium storing instructions of claim 14.
Khasawneh, Lee, and Morris do not teach the operations further comprising: executing the first operating system process in a user mode; and writing the first set of parameters by a second operating system process executed in a privileged mode.
Cui teaches a computing system that determines an application program ID. Cui is thus similar to Khasawneh, Lee, and Morris. Cui further teaches executing the first operating system process in a user mode [0060 and 0080]; and writing the first set of parameters by a second operating system process executed in a privileged mode [0056, 0060, 0080].
It would have been obvious to one of ordinary skill in the art before the effective filing date to use Cui’s teachings of a user mode and a privileged mode in Khasawneh, Lee, and Morris. One of ordinary skill in the art would have been motivated to user a user mode and a privileged mode in Khasawneh, Lee, and Morris because it provides different levels of operation having different features, thus providing Khasawneh, Lee, and Morris with more flexibility.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khasawneh et al. (hereinafter as Khasawneh) PGPUB 2022/0197856 in view of Lee et al. (hereinafter as Lee) PGPUB 2021/0067335 and Morris PGPUB 2007/0283239, and further in view of Ashkar et al. (hereinafter as Ashkar) PGPUB 2019/0101973.
As per claim 19, Khasawneh, Lee, and Morris teaches the non-transitory computer readable medium storing instructions of claim 14.
Khasawneh, Lee, and Morris do not teach wherein configuring the component comprises configuring a clock signal to control power consumption associated with the component.
Ashkar teaches configuring a prefetcher. Ashkar is thus similar to Khasawneh, Lee, and Morris. Ashkar further teaches wherein configuring the component comprises configuring a clock signal to control power consumption associated with the component [0023: (pre-fetch engine may be configured to be clock-gated)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Ashkar’s teachings of configuring the prefetcher to be clock gated when a queued number of instructions becomes too high in Khasawneh, Lee, and Morris. One of ordinary skill in the art would have been motivated to configure the prefetcher in Khasawneh, Lee, and Morris to be clock gated because it allows for conserving power without impacting performance when prefetch engines are getting too far ahead of draw completion [Ashkar 0023 and 0001].
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khasawneh et al. (hereinafter as Khasawneh) PGPUB 2022/0197856 in view of Lee et al. (hereinafter as Lee) PGPUB 2021/0067335 and Morris PGPUB 2007/0283239, and further in view of Tomita PGPUB 2001/0042161.
As per claim 20, Khasawneh, Lee, and Morris teach the non-transitory computer readable medium storing instructions of claim 14.
Khasawneh, Lee, and Morris do not explicitly teach wherein configuring the component comprises configuring hardware to implement a redundancy associated with executing the first operating system process.
Tomita teaches use of a prefetcher. Tomita is thus similar to Khasawneh, Lee, and Morris. Tomita further teaches wherein configuring the component comprises configuring hardware to implement a redundancy associated with executing the first operating system process [0002, 0050, 0089, 0107 and 0127: (new configuration for redundant circuitry in pre-fetch circuit)]. Tomita teaches a configuration for redundant circuitry for pre-fetching.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Tomita’s teachings of configuring to provide redundant circuitry for prefetcher in Khasawneh, Lee, and Morris. One of ordinary skill in the art would have been motivated to provide a configuration in which there is redundant circuitry for the prefetcher in Khasawneh, Lee, and Morris because it allows for more efficient operations [0014].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 9, and 14 have been considered but are moot because the new ground of rejection does not rely on the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/DANNY CHAN/Primary Examiner, Art Unit 2175
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