DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of claim(s) 1-15 without traverse in the reply filed on 10/20/2025 is acknowledged.
Claim(s) 16-23 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species and device/method claim(s), there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-3, 5-8, 12-13, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noma Seiji et al. (JP publication 2010-027695 A, using English machine translation), hereinafter referred to as Noma695.
Regarding claim 1, Noma695 teaches a semiconductor device (fig. 1 and related text) comprising: a semiconductor substrate (10, [0035]); a source region (12, [0036]) of a first conductivity type (n-type) of a MISFET and a drain region (14, [0038]) of the first conductivity type (n-type) of the MISFET (fig. 1), the source region and the drain region being formed spaced apart from each other in the semiconductor substrate (fig. 1); a gate electrode (17, [0039]) of the MISFET, the gate electrode being formed on the semiconductor substrate between the source region and the drain region via a gate dielectric film (16, [0039], fig. 1); a recessed portion (a recess where 30 (31/32) resides, [0040], fig. 1) formed on the semiconductor substrate and penetrating the source region (fig. 1); at least one first semiconductor region (13, [0037]) of a second conductivity type (p-type) formed under the recessed portion (fig. 1), the second conductivity type being opposite the first conductivity type; and a second semiconductor region (11, [0036]) of the second conductivity type (p-type) formed in the semiconductor substrate so as to surround the source region and the at least one first semiconductor region (fig. 1).
Regarding claim 2, Noma695 teaches wherein the second semiconductor region is in contact with a bottom surface of the at least one first semiconductor region and a side surface of the at least one first semiconductor region, and is in contact with a bottom surface of the source region and a side surface of the source region opposite to a side of the recessed portion (fig. 1).
Regarding claim 3, Noma695 teaches wherein, in plan view, the recessed portion is surrounded by the source region (fig. 1).
Regarding claim 5, Noma695 teaches wherein an upper surface of the at least one first semiconductor region is located below a bottom surface of the source region in the semiconductor substrate (fig. 1).
Regarding claim 6, Noma695 teaches wherein, in a gate length direction of the gate electrode, a length of the at least one first semiconductor region is larger than a length of the recessed portion (fig. 1).
Regarding claim 7, Noma695 teaches wherein, in plan view, the at least one first semiconductor region is arranged in an island shape in the second semiconductor region (fig. 1).
Regarding claim 8, Noma695 teaches wherein the at least one first semiconductor region comprises a plurality of first semiconductor regions (regions on left, right, and bottom of 30) formed in the second semiconductor region (fig. 1).
Regarding claim 12, Noma695 teaches wherein an upper portion of the second semiconductor region between the source region and the drain region is a channel forming region of the MISFET, and wherein an impurity concentration of the at least one first semiconductor region is higher than an impurity concentration of the second semiconductor region (fig. 1).
Regarding claim 13, Noma695 teaches comprising: a third semiconductor region (a n-type region of 10) of the first conductivity type interposed between the at least one first semiconductor region and the drain region in a gate length direction of the gate electrode, wherein an impurity concentration of the third semiconductor region is lower than an impurity concentration of the drain region (fig. 1).
Regarding claim 15, Noma695 teaches wherein at least one pair of the recessed portion and the at least one first semiconductor region comprises a plurality of pairs of recessed portions and first semiconductor regions formed in the semiconductor substrate, and wherein the plurality of pairs are arranged spaced apart from each other in a gate width direction of the gate electrode (a plurality of devices of fig. 1 arranged side by side in a substrate will meet this limitation).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Noma695, as applied to claim 1 or 3 above.
Regarding claim 4, Noma695 discloses all the limitations of claim 3 as discussed above on which this claim depends.
Noma695 does not explicitly teach wherein, in a gate width direction of the gate electrode, a width of the source region is equal to a width of the gate electrode. However, it is well-known in the art that a width/thickness of a semiconducting or insulation or conductive layer depends on a process technology, overall size of the device, and is a result-effective variable as electrical properties (conductivity, current, resistance, doping, insulation, withstanding breakdown, etc.) depend on the width/thickness of a semiconducting or insulation or conductive layer. So, a width/thickness of a semiconducting or insulation or conductive layer is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation.
Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Noma695 so that wherein, in a gate width direction of the gate electrode, a width of the source region is equal to a width of the gate electrode for the purpose of optimizing device performance and overall size of the device.
Allowable Subject Matter
Claims 9-11 and 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9-11, the claim contains the following limitations: “comprising: an interlayer dielectric layer provided on the semiconductor substrate; a first contact plug electrically connected to the at least one first semiconductor region; and sidewall dielectric films formed on side surfaces of the recessed portion, wherein the first contact plug penetrates through the interlayer dielectric layer, passes through between the sidewall dielectric films and reaches an upper surface of the at least one first semiconductor region” and none of the prior art of record discloses, teaches or fairly suggests, alone or in combinations when taken in combination with all other limitations of the base claim and any intervening claims.
Regarding claim 14, the claim contains the following limitations: “wherein the second semiconductor region includes: a fourth semiconductor region of the second conductivity type surrounding the at least one first semiconductor region; and a fifth semiconductor region of the second conductivity type adjacent to the fourth semiconductor region, wherein an impurity concentration of the fourth semiconductor region is higher than an impurity concentration of the fifth semiconductor region, wherein the channel forming region is located in the fifth semiconductor region” and none of the prior art of record discloses, teaches or fairly suggests, alone or in combinations when taken in combination with all other limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art.
Feng et al. (US publication 20220271157 A1) teaches (a recessed portion (a recess where 34 resides, [0024], fig. 2b) formed on the semiconductor substrate and penetrating the source region (16)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897