DETAILED ACTION
This action is in response to the claims filed 06/02/2026 for Application number 18/191,700. Claims 1, 8, 15 have been amended, claims 3, 4, 5, 10, 11, 12, 17, 18, and 19 have been canceled, and claims 21-30 are newly added. Thus, claims 1-2, 6-9, 13-16, and 20-30 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in India on 08/22/2022. It is noted, however, that applicant has not filed a certified copy of the IN202241047830 application as required by 37 CFR 1.55.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
a configuration engine configured to... in claim 30
a configuration delivery mechanism configured to… in claim 30
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 2, 6-9, 13-16, 20, and 22-30 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Regarding claim 1,
Step 1 Analysis: Claim 1 is directed to a process, which falls within one of the four statutory categories.
Step 2A Prong 1 Analysis: Claim 1 recites, in part, The limitations of:
determining, by the processing system, an accuracy improvement of the selected layer by comparing a quantization error of executing the first bit precision to a quantization error of executing the second bit precision using distance metrics between outputs of the layers can be considered to be an evaluation in the human mind,
determining, by the processing system, a latency degradation of the selected layer by comparing inference time with the first bit precision to inference time with the second bit precision can be considered to be an evaluation in the human mind
calculating, by the processing system, an impact factor for the selected layer based on a ratio of the accuracy improvement to the latency degradation can be considered to be an evaluation in the human mind
selecting, based on the impact factor, the first bit precision or the second bit precision for implementing the selected layer to produce a selected combination of bit precision can be considered to be an evaluation in the human mind
These limitations as drafted, are processes that, under broadest reasonable interpretation, covers performance of the limitation in the mind or with the aid of pen and paper which falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A Prong 2 Analysis: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements - “executing, by the processing system, the trained neural network in floating-point mode to establish baseline outputs and performance metrics for each layer of the trained neural network;”
“executing, by the processing system, the trained neural network with each layer quantized to a second bit precision and recording accuracy and latency performance for each layer”
“executing, by the processing system, the trained neural network with a selected layer quantized to a first bit precision while other layers remain in the second bit precision, measuring performance;”
“configuring the neural network with the selected combination of bit precisions each layer while maintaining a mixed precision factor below a target mixed precision factor threshold.”
Thus, these elements in the claim are recited at a high level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component. Please see MPEP 2106.05(f). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
The claim further recites: receiving, by a processing system of the computing device, the trained neural network trained on a training precision; This limitation is a mere data gathering step and thus is an insignificant extra-solution activity. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim as a whole is directed to an abstract idea.
Step 2B Analysis: The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of executing the neural network to perform the steps of the claimed process amount to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Furthermore, the limitation of receiving, by a processing system of the computing device, the trained neural network trained on a training precision is well-understood, routine, and conventional, as evidenced by MPEP §2106.05(d)(II)(I), “receiving or transmitting data over a network”. These limitations therefore remain insignificant extra-solution activity even upon reconsideration, and does not amount to significantly more. Even when considered in combination, these additional elements amount to mere instructions to apply the exception using generic computer components and insignificant extra-solution activity, which cannot provide an inventive concept. The claim is not patent eligible.
Regarding claim 2, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein the first bit precision is based on a first quantization of floating point data to fixed point data of a first length, and wherein the second bit precision is based on a second quantization of the floating point data to fixed point data of a second length that differs relative to the first length. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 6, the rejection of claim 1 is further incorporated, and further, the claim recites: further comprising
determining a mixed precision factor for the neural network in which the layer uses the second bit precision and one or more further layers use the first bit precision, wherein selecting the first bit precision or the second bit precision is based further on a comparison between the mixed precision factor and a threshold mixed precision factor. This claim recites additional mental steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application, nor to significantly more than the judicial exceptions. The claim is not patent eligible.
Regarding claim 7, the rejection of claim 1 is further incorporated, and further, the claim recites: further comprising
selecting the second bit precision for use in implementing a further layer of the neural network;
determining a further mixed precision factor for the neural network in which the selected layer and the further layer use the second bit precision;
comparing the further mixed precision factor and the threshold mixed precision factor; and
selecting the first bit precision for use in implementing the further layer of the neural network based on the further mixed precision factor exceeding the threshold mixed precision factor. This claim recites additional mental steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application, nor to significantly more than the judicial exceptions. The claim is not patent eligible.
Regarding claim 8,
Step 1 Analysis: Claim 8 is directed to a process, which falls within one of the four statutory categories.
Step 2A Prong 1 Analysis: Claim 8 recites, in part, The limitations of:
calculate an accuracy improvement between the respective outputs of the respective layer implemented using the first bit precision relative to using the second bit precision using a quantization error metric can be considered to be an evaluation in the human mind
measure a latency degradation by comparing inference execution times of the respective layer implemented using the first bit precision relative to using the second bit precision can be considered to be an evaluation in the human mind
calculate an impact factor as a ratio of accuracy improvement to latency degradation; select the first or second bit precision for the respective layer based on the impact factor can be considered to be an evaluation in the human mind
generate a neural network configuration balancing accuracy improvement and latency degradation can be considered to be an evaluation in the human mind
These limitations as drafted, are processes that, under broadest reasonable interpretation, covers performance of the limitation in the mind or with the aid of pen and paper which falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A Prong 2 Analysis: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements - “A configuration engine for configuring a neural network for mixed precision execution on a system-on-chip, comprising: one or more computer-readable storage media; a processing system coupled to the one or more computer-readable storage media; and program instructions stored on the one or more computer-readable storage media that, when read and executed by the processing system, direct the configuration engine to:”
“execute the trained neural network in floating-point mode and measure baseline accuracy and latency for each layer of the trained neural network”
“execute inferences for the trained neural network with the respective layer configured with a first bit precision to generate a first output, and with the respective layer configured with a second bit precision to generate a second output”
Thus, these elements in the claim are recited at a high level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component. Please see MPEP 2106.05(f). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
The claim further recites: receive a trained neural network; This limitation is a mere data gathering step and thus is an insignificant extra-solution activity. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim as a whole is directed to an abstract idea.
Step 2B Analysis: The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of executing the neural network to perform the steps of the claimed process amount to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Furthermore, the limitation of receive a trained neural network is well-understood, routine, and conventional, as evidenced by MPEP §2106.05(d)(II)(I), “receiving or transmitting data over a network”. These limitations therefore remain insignificant extra-solution activity even upon reconsideration, and does not amount to significantly more. Even when considered in combination, these additional elements amount to mere instructions to apply the exception using generic computer components and insignificant extra-solution activity, which cannot provide an inventive concept. The claim is not patent eligible.
Regarding claims 9, 13, 14, they are substantially similar to claims 2, 6 and 7 respectively, and are rejected in the same manner, the same art, and reasoning applying.
Regarding claim 15,
Step 1 Analysis: Claim 15 is directed to a process, which falls within one of the four statutory categories.
Step 2A Prong 1 Analysis: Claim 15 recites, in part, The limitations of:
determine an accuracy improvement of the respective layer by comparing quantization error of a configuration with the first bit precision to quantization error of a configuration with the second bit precision using distance metrics between layer outputs can be considered to be an evaluation in the human mind
determine a latency degradation of the respective layer by comparing inference time in the first bit precision configuration to inference time in the second bit precision configuration can be considered to be an evaluation in the human mind
calculate an impact factor for the respective layer based on a ratio of the accuracy improvement to the latency degradation; can be considered to be an evaluation in the human mind
select, based on the impact factor, the first bit precision or the second bit precision for implementing the respective layer to produce a selected combination of bit precisions can be considered to be an evaluation in the human mind
configure the neural network with the selected combination of bit precisions for each layer to achieve reduced memory consumption and decreased power usage while maintaining execution speed above a target threshold can be considered to be an evaluation in the human mind
These limitations as drafted, are processes that, under broadest reasonable interpretation, covers performance of the limitation in the mind or with the aid of pen and paper which falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A Prong 2 Analysis: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements - “One or more computer-readable storage media having program instructions stored thereon, wherein the program instructions, when read and executed by a processing system, direct the processing system to”
“execute the trained neural network in floating-point mode on the processing system to establish baseline outputs and performance metrics for each layer of the trained neural network”
“execute the trained neural network with each layer quantized to a second bit precision and record accuracy and latency performance for each layer;”
“execute the trained neural network with a respective layer quantized to a first bit precision while other layers remain in the second bit precision, measuring performance”
Thus, these elements in the claim are recited at a high level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component. Please see MPEP 2106.05(f). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
The claim further recites: receive a trained neural network; This limitation is a mere data gathering step and thus is an insignificant extra-solution activity. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim as a whole is directed to an abstract idea.
Step 2B Analysis: The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of executing the neural network to perform the steps of the claimed process amount to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Furthermore, the limitation of receive a trained neural network is well-understood, routine, and conventional, as evidenced by MPEP §2106.05(d)(II)(I), “receiving or transmitting data over a network”. These limitations therefore remain insignificant extra-solution activity even upon reconsideration, and does not amount to significantly more. Even when considered in combination, these additional elements amount to mere instructions to apply the exception using generic computer components and insignificant extra-solution activity, which cannot provide an inventive concept. The claim is not patent eligible.
Regarding claims 16 and 20, they are substantially similar to claims 2 and 6 respectively, and are rejected in the same manner, the same art, and reasoning applying.
Regarding claim 22, the rejection of claim 1 is further incorporated, and further, the claim recites: calculating respective impact factors for each layer of the neural network using the impact factor;
sorting the impact factors for each layer from highest to lowest;
selecting the layer with the highest impact factor to implement in the first bit precision;
computing a mixed precision factor based on an interference time divided by an 8 bit time;
comparing the mixed precision factor to a target mixed precision factor threshold; and
iteratively adding layers with next-highest impact factors to the first bit precision mode until the mixed precision factor would exceed the target threshold, then stopping at the configuration immediately before exceeding the threshold. This claim recites additional mental steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exceptions into a practical application, nor to significantly more than the judicial exceptions. The claim is not patent eligible.
Regarding claim 23, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein the first bit precision and second bit precision are selected from a group consisting of 32-bit floating-point, 16-bit floating-point, 16-bit fixed-point integer, 8-bit fixed-point integer, and 4-bit fixed-point integer. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 24, the rejection of claim 1 is further incorporated, and further, the claim recites: executing the neural network with all layers in 8-bit precision and measuring accuracy and latency; This limitation amounts to mere instructions to apply the judicial exception using a generic computer component. Please see MPEP 2106.05(f).
iteratively quantizing each layer to 16-bit precision while maintaining others in 8-bit;calculating quantization error for each mixed-precision configuration using distance metrics between outputs; This is a mathematical calculation, thus recites an abstract idea
computing a mixed precision factor (MPF) for each configuration as the ratio of inference time to all-8-bit inference time; This is a mathematical calculation, thus recites an abstract idea
comparing the MPF to a target threshold; and
selecting a layer configuration achieving maximum accuracy improvement without exceeding the target MPF. These limitations recite additional mental steps in addition to the judicial exception identified in the rejection of claim 1, thus recites a judicial exception.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 25, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein: the training precision comprises 32-bit floating-point; the first bit precision comprises 16-bit fixed-point; and the second bit precision comprises 8-bit fixed-point. This limitation amounts to more specifics of the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 26, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein determining the accuracy improvement comprises: calculating a quantization error between an output using the first bit precision and an output using the training precision. This limitation amounts to mathematical calculations in addition to the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 27, the rejection of claim 8 is further incorporated, and further, the claim recites: wherein a neural network module comprises one or more hardware accelerators including a floating-point module, an 8-bit precision module, and a 16-bit precision module and wherein the program instructions further direct the configuration engine to select, for each layer of the neural network configured with the first bit precision or the second bit precision, a corresponding one of the hardware accelerators to execute that layer during runtime inference. This limitation amounts to mere instructions to apply the judicial exception using a generic computer component. Please see MPEP 2106.05(f).
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 28, the rejection of claim 8 is further incorporated, and further, the claim recites: wherein the configuration engine is integrated within or communicatively coupled to a system-on-chip (SoC) including a processing system and a neural network module, and wherein the program instructions further direct the configuration engine to provide the neural network configuration to the processing system for execution of the neural network according to the configured layer precisions, and wherein the SoC is integrated into an embedded system, microcontroller unit (MCU), or application-specific device for inference operations. This limitation amounts to mere instructions to apply the judicial exception using a generic computer component. Please see MPEP 2106.05(f).
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 29, the rejection of claim 1 is further incorporated, and further, the claim recites: wherein comparing quantization error of the first bit precision execution to quantization error of the second bit precision execution comprises: selecting, based on the layer output type, either a normalized mean average error (MAE) metric or a normalized mean squared error (MSE) metric; computing a mean and standard deviation at each output of the neural network executed in floating-point mode; and calculating the MAE or MSE error at each output, normalizing the errors relative to the mean and standard deviation to determine final error values for layer configuration purposes. This limitation amounts to additional mental steps in addition to the judicial exception identified in the rejection of claim 1 above.
The claim does not include any additional elements that amount to an integration of the judicial exception into a practical application, nor to significantly more than the judicial exception. The claim is not patent eligible.
Regarding claim 30,
Step 1 Analysis: Claim 30 is directed to a process, which falls within one of the four statutory categories.
Step 2A Prong 1 Analysis: Claim 30 recites, in part, The limitations of:
determine an impact factor for each layer of the trained neural network based on accuracy improvement and latency degradation can be considered to be an evaluation in the human mind
generate a neural network configuration specifying a bit precision for each layer can be considered to be an evaluation in the human mind
These limitations as drafted, are processes that, under broadest reasonable interpretation, covers performance of the limitation in the mind or with the aid of pen and paper which falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A Prong 2 Analysis: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements - “A system for configuring neural networks for inference execution, comprising: a configuration engine configured to”
“execute the neural network in multiple precision modes”
“one or more embedded systems, microcontroller units (MCUs), or application-specific devices communicatively coupled to the configuration engine;”
Thus, these elements in the claim are recited at a high level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component. Please see MPEP 2106.05(f). Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
The claim further recites: receive a trained neural network;
a configuration delivery mechanism configured to provide the neural network configuration from the configuration engine to the embedded systems, MCUs, or application- specific devices for execution of the neural network according to the configured precisions, wherein each embedded system, MCU, or application-specific device comprises a processing system and a neural network module with hardware accelerators corresponding to at least the specified precisions.
These limitations are insignificant extra-solution activities. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim as a whole is directed to an abstract idea.
Step 2B Analysis: The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements of executing the neural network to perform the steps of the claimed process amount to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Furthermore, the limitations of receive a trained neural network; and
a configuration delivery mechanism configured to provide the neural network configuration from the configuration engine to the embedded systems, MCUs, or application- specific devices for execution of the neural network according to the configured precisions, wherein each embedded system, MCU, or application-specific device comprises a processing system and a neural network module with hardware accelerators corresponding to at least the specified precisions.
are well-understood, routine, and conventional, as evidenced by MPEP §2106.05(d)(II)(I), “receiving or transmitting data over a network”. These limitations therefore remain insignificant extra-solution activity even upon reconsideration, and does not amount to significantly more. Even when considered in combination, these additional elements amount to mere instructions to apply the exception using generic computer components and insignificant extra-solution activity, which cannot provide an inventive concept. The claim is not patent eligible.
The limitations of claim 21 amount to an integration of the abstract idea into a practical application and amount to significantly more than the judicial exception, therefore the claim is patent eligible under 35 U.S.C. 101.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 30 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Darvish Rouhani et al. ("US 20200210840 A1", hereinafter "Darvish").
Regarding claim 30, Darvish Rouhani teaches A system for configuring neural networks for inference execution, comprising:
a configuration engine configured to (See ¶0050, neural network module):
receive a trained neural network (“The neural network module 130 can be used to specify, train, and evaluate a neural network model using a tool flow that includes a hardware-agnostic modelling framework 131 (also referred to as a native framework or a machine learning execution engine), a neural network compiler 132, and a neural network runtime environment 133.” [¶0050]),
execute the neural network in multiple precision modes (“At process block 610, parameters, such as weights and biases, of the neural network can be initialized. As one example, the weights and biases can be initialized to random block floating-point values in a lower precision format, for example having between two and five bits of precision. In some examples, the weights and biases can be initialized to random floating-point values in a lower precision but normal floating-point format, without exponent sharing.” [¶0092]),
determine an impact factor for each layer of the trained neural network based on accuracy improvement and latency degradation (“In some examples of the disclosed technology, the training performance metric is based on accuracy or change in accuracy of at least one layer of the trained neural network, and the accuracy or change in accuracy is measured based at least in part on one or more of the following for the at least one layer of the trained neural network” [¶0162; See further: ¶0027 and ¶0061 disclose “latency”]), and
generate a neural network configuration specifying a bit precision for each layer; one or more embedded systems, microcontroller units (MCUs), or application-specific devices communicatively coupled to the configuration engine (“The compiler 132 can generate configuration data for the accelerator 180 that is used to configure accelerator resources to evaluate the subgraphs assigned to the optional accelerator 180. The compiler 132 can create data structures for storing values generated by the neural network model during execution and/or training and for communication between the CPU 120 and the accelerator 180. The compiler 132 can generate metadata that can be used to identify subgraphs, edge groupings, training data, and various other information about the neural network model during runtime.” [¶0054]); and
a configuration delivery mechanism configured to provide the neural network configuration from the configuration engine to the embedded systems, MCUs, or application- specific devices for execution of the neural network according to the configured precisions (“Such neural networks may be deployed in a distributed computing environment for use in inference operations with the trained neural network. … The disclosed technology may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network.” [¶0148-¶0150]), wherein each embedded system, MCU, or application-specific device comprises a processing system and a neural network module with hardware accelerators corresponding to at least the specified precisions. (“The runtime environment 133 can include a deployment tool that, during a deployment mode, can be used to deploy or install all or a portion of the neural network to neural network accelerator 180. The runtime environment 133 can further include a scheduler that manages the execution of the different runtime modules and the communication between the runtime modules and the neural network accelerator 180.” [¶0056])
Allowable Subject Matter
Claims 1-2, 6-9, 13-16, and 20-29 are objected to as being allowable over prior art if all outstanding rejections were withdrawn. None of the prior art, either alone or in combination, fairly discloses limitations of claims 1, 8 and 15 in particular:
Claim 1:
receiving, by a processing system of the computing device, the trained neural network trained on a training precision;
executing, by the processing system, the trained neural network in floating-point mode to establish baseline outputs and performance metrics for each layer of the trained neural network;
executing, by the processing system, the trained neural network with each layer quantized to a second bit precision and recording accuracy and latency performance for each layer;
executing, by the processing system, the trained neural network with a selected layer quantized to a first bit precision while other layers remain in the second bit precision, measuring performance;
determining, by the processing system, an accuracy improvement of the selected layer by comparing a quantization error of executing the first bit precision to a quantization error of executing the second bit precision using distance metrics between outputs of the layers;
determining, by the processing system, a latency degradation of the selected layer by comparing inference time with the first bit precision to inference time with the second bit precision;
calculating, by the processing system, an impact factor for the selected layer based on a ratio of the accuracy improvement to the latency degradation;
selecting, based on the impact factor, the first bit precision or the second bit precision for implementing the selected layer to produce a selected combination of bit precision; and
configuring the neural network with the selected combination of bit precisions each layer while maintaining a mixed precision factor below a target mixed precision factor threshold.
Claim 8:
a trained neural network
execute the trained neural network in floating-point mode and measure baseline accuracy and latency for each layer of the trained neural network
execute inferences for the trained neural network with the respective layer configured with a first bit precision to generate a first output, and with the respective layer configured with a second bit precision to generate a second output
calculate an accuracy improvement between the respective outputs of the respective layer implemented using the first bit precision relative to using the second bit precision using a quantization error metric;
measure a latency degradation by comparing inference execution times of the respective layer implemented using the first bit precision relative to using the second bit precision;
calculate an impact factor as a ratio of accuracy improvement to latency degradation;
select the first or second bit precision for the respective layer based on the impact factor; and
generate a neural network configuration balancing accuracy improvement and latency degradation.
Claim 15:
receive a trained neural network;
execute the trained neural network in floating-point mode on the processing system to establish baseline outputs and performance metrics for each layer of the trained neural network;
execute the trained neural network with each layer quantized to a second bit precision and record accuracy and latency performance for each layer;
execute the trained neural network with a respective layer quantized to a first bit precision while other layers remain in the second bit precision, measuring performance;
determine an accuracy improvement of the respective layer by comparing quantization error of a configuration with the first bit precision to quantization error of a configuration with the second bit precision using distance metrics between layer outputs;
determine a latency degradation of the respective layer by comparing inference time in the first bit precision configuration to inference time in the second bit precision configuration;
calculate an impact factor for the respective layer based on a ratio of the accuracy improvement to the latency degradation;
select, based on the impact factor, the first bit precision or the second bit precision for implementing the respective layer to produce a selected combination of bit precisions; and
configure the neural network with the selected combination of bit precisions for each layer to achieve reduced memory consumption and decreased power usage while maintaining execution speed above a target threshold.
Response to Arguments
Applicant's arguments filed 06/02/2026 have been fully considered but they are not persuasive.
Regarding the 35 U.S.C. §101 Rejection:
Applicant argues the amended claims require specific, concrete technological implementation that cannot be performed in the human mind or with pen and paper. Examiner respectfully disagrees. The particular steps of executing as argued by the applicant amount to mere instructions to apply the judicial exception using a generic computer component. Please see MPEP 2106.05(f). Applicant further argues the amended language require actual hardware acceleration modules and the steps of “determining an accuracy improvement…using distance metrics between layer outputs” requires measurement of actual layer output values and “determining … a latency degradation … by comparing inference time” requires measurement of actual hardware performance metrics. Examiner respectfully disagrees. These steps of “determining …”, under BRI, amount to processes which can be practically performed in the human mind. Examiner further notes that a claim that requires a computer may still recite a mental process. Please see MPEP §2106.04.(a)(2).III.C. Therefore, applicant’s arguments are not persuasive and the claim remains patent ineligible.
Applicant argues the amended claims are not directed to generic computing and requires specialized neural network hardware and not a generic computer. Examiner respectfully disagrees. The claims do not recite any specialized neural network hardware rather the claims merely recite “a processing system” which is a broad and generic use of a generic computer component. Therefore, applicant’s arguments are not persuasive.
Applicant further argues the amended claims specify a particular measurement methodology. Examiner respectfully disagrees. The claimed steps as identified in the 101 rejection above recite steps which can be practically performed in the human mind. The independent claims do not specify the “specific mathematical functions” as argued by applicant rather the claims merely recite “a distance metric” between outputs (i.e. under BRI, merely a difference between prediction values). Therefore, applicant’s arguments are not persuasive.
Applicant further argues new claim 22 specifies the exact iterative procedure, however as noted in the 101 rejection above, the limitations of claim 22 amount to additional mental steps which can be practically performed in the human mind. There are no additional elements in claim 22 that would amount to an integration of the judicial exception into a practical application nor significantly more. Therefore, applicant’s arguments are not persuasive.
As noted above, examiner has indicated that claim 21 is patent eligible and therefore the independent claims would be patent eligible if the claims were rewritten to incorporate all of the limitations of claim 21.
Regarding the prior art rejection:
The claims have been searched, however no prior art was uncovered which fairly discloses the limitations of claims 1, 8 and 15. Therefore, the claims would be allowable if all outstanding rejections were withdrawn.
Regarding claim 30, the examiner has provided an updated prior art rejection as it recites limitations which are different in scope from claims 1, 8 and 15.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL H HOANG whose telephone number is (571)272-8491. The examiner can normally be reached Mon-Fri 8:30AM-4:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kakali Chaki can be reached at (571) 272-3719. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL H HOANG/PRIMARY EXAMINER, Art Unit 2122
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