Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final Office Action
DETAILED ACTION
Examiner’s Notes
(a) Claim date: 07/01/2026 (in response to restriction requirement, 1-9 selected.)
(b) Priority date: 03/28/2023.
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1–9 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Shaddock (US10,642,630 B1).
(As to claim 1, Shaddock discloses)
1. (Original) A tangible, non-transitory, and computer-readable medium, storing instructions thereon, wherein the instructions, when executed, are to cause a processor to [Fig. 1, 106, “Server”]:
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receive a design to be implemented onto a programmable fabric of an integrated circuit device [FIG. 3B: Shaddock discloses receiving input to specify functional logic of an algorithm to implement on a particular FPGA (integrated circuit device having a programmable fabric), wherein the input is received as graphical blocks in the IDE’s GUI representing the design, disclosing receiving a design to be implemented onto a programmable fabric of an integrated circuit device]
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determine that the design is implementable using a persona from a library comprising a plurality of personas [FIG. 2 block 208, Col. 6: Shaddock discloses automatically determining a subset of the primitive functions (personas) comprising particular primitive functions that correspond to the graphical blocks of the functional logic, by consulting a mapping table or configuration file that maps each functional block to a particular pre-compiled primitive bitstream stored in digital storage (the library comprising the plurality of personas), disclosing determining that the design is implementable using a persona from a library comprising a plurality of personas];
compile the design, wherein the plurality of personas are compiled at a different time than the design [Col. 4, FIG. 2 blocks 202–204: Shaddock explicitly discloses that “ahead of time” — meaning before the end user designs an algorithm — the server pre-compiles all possible combinations of primitives (personas) for the target FPGA platform and stores the compiled primitive bitstreams in digital storage (blocks 202–204), while the user’s design (the algorithm) is defined at a separate later time (block 206), disclosing compiling the design wherein the plurality of personas are compiled at a different time than the design];
transmit a bit stream to partially reconfigure the integrated circuit device using the persona, wherein the bit stream comprises data to configure a region of the integrated circuit device [Col. 4, FIG. 2 blocks 210–214, Col. 3: Shaddock discloses using one or more partial reconfiguration operations to write the subset of primitive bitstreams to the FPGA, wherein each partial bitstream contains configuration data and location data for a specific reconfigurable partition (region) of the FPGA, and the compilation agent causes the bitstreams to be written to specified RPs and variations of the FPGA, disclosing transmitting a bit stream to partially reconfigure the integrated circuit device using the persona wherein the bit stream comprises data to configure a region of the integrated circuit device]
(As to claim 2, Shaddock discloses)
2. (Original) The tangible, non-transitory, and computer-readable medium of claim 1, wherein the instructions, when executed, are to cause the processor to:
decompose the design into a compiler data flow graph comprising one or more graph nodes [FIG. 2 block 208, which involves decomposing the block diagram (data flow graph) into its constituent nodes, disclosing decomposing the design into a compiler data flow graph comprising one or more graph nodes];
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map the one or more graph nodes to one or more personas of the plurality of personas [FIG. 3C illustrates the functional blocks of the algorithm assigned to specific RPs or regions of the FPGA architecture, disclosing mapping the one or more graph nodes to one or more personas of the plurality of personas].
(As to claim 3, Shaddock discloses)
3. (Original) The tangible, non-transitory, and computer-readable medium of claim 2, wherein the instructions, when executed, are to cause the processor to
cluster a first set of personas of the one or more personas in a first region, wherein each of the first set of personas consume less than a threshold amount of resources [Col. 8–9, FIG. 3A, FIG. 3D: Shaddock discloses that in a variation of the architecture, low-level PR modules (1.1, 1.2, 1.3 to 6.3) represent smaller primitives (personas consuming fewer resources) that are assigned to first-set DSP block PR regions, while larger PR regions (N.1, N.2, N.X in FIG. 3D) are configured as single-channel instruments].
(As to claim 4, Shaddock discloses)
4. (Original) The tangible, non-transitory, and computer-readable medium of claim 2, wherein the instructions, when executed, are to cause the processor to:
divide a first persona of the one or more personas into multiple smaller personas [Col. 9–10, FIG. 3A–3B: Shaddock discloses that complex functional blocks may result in bitstreams that are divided across two or more variations of an FPGA region, stating “complex functional blocks may result in bitstreams that are divided across two or more variations of an FPGA region,” disclosing dividing a first persona of the one or more personas into multiple smaller personas];
determine routing between each of the multiple smaller personas [Col. 9, FIG. 3A: Shaddock discloses that a plurality of interconnects 302 allow arbitrary connections between rows of DSP block PR regions, disclosing determining routing between each of the multiple smaller personas].
(As to claim 5, Shaddock discloses)
5. (Original) The tangible, non-transitory, and computer-readable medium of claim 1, wherein the instructions, when executed, are to cause the processor to
receive an additional design from a same user or a different user to implement onto the programmable fabric of the integrated circuit device [FIG. 1: the server 106 is configured to receive requests from multiple client computing devices 102, each running their own IDE and design, including different users, to implement their respective designs onto the same target FPGA platform, disclosing receiving an additional design from a same user or a different user to implement onto the programmable fabric of the integrated circuit device].
(As to claim 6, Shaddock discloses)
6. (Original) The tangible, non-transitory, and computer-readable medium of claim 1, wherein the instructions, when executed, are to cause the processor to:
determine a second persona associated with the design from the library [FIG. 2 block 208, FIG. 3B–3C: the compilation agent automatically determines all pre-compiled primitive bitstreams (personas), a design with multiple functional blocks, the compiler determines each corresponding primitive (persona) from the library for each block, including a second persona for a second graph node of the design, disclosing determining a second persona associated with the design from the library];
determine a first region to be configured by the persona and a second region to be configured by the second persona [FIG. 3C shows each functional block assigned to a specific region (e.g., region 1.1 is assigned Sine Gen logic, region 1.2 is the demodulator), disclosing determining a first region to be configured by the persona and a second region to be configured by the second persona];
generate a clock signal based on a path between the first region and the second region [Col. 9, FIG. 3A: regions in relation to interconnects 302 and buses 304 determines signal routing and clock domain relationships between the first and second regions, disclosing generating a clock signal based on a path between the first region and the second region].
(As to claim 7, Shaddock discloses)
7. (Original) The tangible, non-transitory, and computer-readable medium of claim 6, wherein the instructions, when executed, are to cause the processor to:
determine a location of the first region based on a function of the persona and a location of a network-on-chip [Col. 9, FIG. 3A, FIG. 3C: regions in relation to interconnects 302 (a network-on-chip) and AXI buses 304 accomplishes implementation in a particular chip arrangement, and the compilation agent determines which available RP (region location) is to receive which primitive bitstream (persona function)];
determine a location of the second region based on a function of the second persona and the location of the network-on-chip [Col. 9, FIG. 3A, FIG. 3C: the RP location for each primitive (persona) based on that primitive’s function and its position relative to the interconnects 302 and AXI buses 304 (the network-on-chip), disclosing determining a location of the second region based on a function of the second persona and the location of the network-on-chip].
(As to claim 8, Shaddock discloses)
8. (Original) The tangible, non-transitory, and computer-readable medium of claim 1, wherein
the library comprising the plurality of personas is generated prior to compilation of the design [Col. 4, FIG. 2 blocks 202–204: the server pre-compiles all possible combinations of primitives (the library comprising the plurality of personas) and stores them in digital storage at blocks 202–204, and that this occurs “ahead of time”—before the end user computer is used to design an algorithm (block 206)].
(As to claim 9, Shaddock discloses)
9. (Original) The tangible, non-transitory, and computer-readable medium of claim 8, wherein
the plurality of personas comprises personas by a manufacturer, personas generated by a customer, personas generated by other designers, or a combination thereof [Col. 5: discloses that the compilation server process 132 may be operated by the FPGA vendor (manufacturer personas), and individual users (customer/designer personas) may specify or contribute to the library, disclosing that the plurality of personas comprises personas by a manufacturer, personas generated by a customer, personas generated by other designers, or a combination thereof].
Conclusion
The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851
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