Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed on 09/18/2025.
Claim Objections
Claims 10, 13, and 15 are objected to because of the following informalities: Regarding claim 10, in line 5, “voltage supply terminal” appears that it should read as “the voltage supply terminal”. Regarding claim 13, in line 10, “the first input” appears that it should read as “a first input”. Regarding claim 15, in line 2, “capable of” appears that it should read as “is capable of”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, and 2 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yao et al. (Chinese Patent Application Publication CN 106357099 A, hereinafter “Yao”).
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<Annotated Fig. 12 of Yao>
Regarding claim 1, Yao discloses (see Annotated Fig. 12) a circuit (see Fig. 12), comprising: gate drive circuitry having an input (Gate IN) and an output (Gate OUT) and including a first transistor (MP1) having a first terminal (top-side terminal of MP1) coupled to a voltage supply terminal (coupled to VCC via Is), a second terminal (bottom-side terminal of MP1) coupled to the output of the gate drive circuitry, and a control terminal (gate of MP1) coupled to the input of the gate drive circuitry; a second transistor (MP2) having a first terminal (top-side terminal of MP2) coupled to the voltage supply terminal (coupled to VCC via Im), a second terminal (bottom-side terminal of MP2) coupled to the output of the gate drive circuitry, and a control terminal (gate of MP2); a logic circuit (OR) having a first input (top-side input terminal of OR), a second input (bottom-side input terminal of OR) coupled to the control terminal of the first transistor, and an output (output of OR) coupled to the control terminal of the second transistor; and a pulse generation circuit (comprising MN_hs, gate_sense_h, Delay_cell_h, inverter) having an output (output of the inverter) coupled to the first input of the logic circuit, and including: a third transistor (MN_hs) having a first terminal (top-side terminal of MN_hs) coupled to the voltage supply terminal, a second terminal (bottom-side terminal of MN_hs) coupled to a switching terminal (SW), and a control terminal (gate of MN_hs) coupled to the output of the gate drive circuitry.
Regarding claim 2, Yao discloses (see Annotated Fig. 12) wherein the logic circuit includes an OR gate (OR gate) having the first input coupled to the output of the pulse
generation circuit (top-side input of OR is coupled to the output of the inverter), the second input coupled to the control terminal of the first transistor (bottom-side input of OR is coupled to the gate of MP1), and the output coupled to the control terminal of the second transistor (output of OR is coupled to the gate of MP2).
Allowable Subject Matter
Claims 3-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 4, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the pulse generation circuit includes a current source coupled between the power terminal and the third current terminal having a first terminal coupled to the voltage supply terminal and a second terminal coupled to the first terminal of the third transistor.”.
Claims 3, 5-9 are objected due to their dependency on claim 4.
Claims 10-16 are objected to according to the objections made above, but would be allowable if rewritten to overcome the objections. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 10, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “a comparator having an input coupled to the first terminal of the transistor and an output coupled to the output of the pulse generation circuit, in which the pulse generation circuit is capable of generating a pulse to disable the second drive circuit responsive to a signal at the first terminal of the transistor and a threshold voltage of the comparator.”.
a comparator having an input coupled to the first terminal of the transistor and an output coupled to the output of the pulse generation circuit, in which the pulse generation circuit is capable of generating a pulse to disable the second drive circuit responsive to a signal at the first terminal of the transistor and a threshold voltage of the comparator. Claims 11-16 are objected due to their dependency on claim 10.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 2 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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/JYE-JUNE LEE/Examiner, Art Unit 2838
/JUE ZHANG/Primary Examiner, Art Unit 2838