Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final Office Action
DETAILED ACTION
Examiner’s Notes
(a) Claim date: 03/29/2023.
(b) Priority date: NA
(c) Invention: Verification cryptographic IP block. Claiming generic features, novelty could not be identified.
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1-20, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of record “Wang” <US 20130305194 A1>.(As to claim 1, 8, 15, Wang discloses):1. A method for automatic verification of a hardware cryptographic implementation, the method comprising [0002: “validating integrated circuit designs built with encrypted silicon IP blocks”]:
receiving a reference implementation of a cryptographic algorithm [0070: “an encrypted silicon IP block to get its original design”];
receiving test case data associated with the cryptographic algorithm [0013: “verification tools … encrypted silicon IP blocks”];
generating a stimulus based upon the test case data; applying the stimulus to the reference implementation using a simulation model to generate a first intermediate state result [Claim 16: “circuit verification tool to perform a circuit validation”] [Note: design verification is a well-known art in the semiconductor industry, which uses applying vector or stimulus and comparing the results with desired output];
applying the stimulus to a hardware implementation of the cryptographic algorithm using the simulation model to generate a second intermediate state result [0002: “validating integrated circuit designs built with encrypted silicon IP blocks”] [Note: Limitation “second intermediate state result” is interpreted as any intermediate “state” as part of the various design verification process flow (not distinctive enough to get patentable weight]; and
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generating a verification result based upon a comparison of the first intermediate state result and the second intermediate state result [Fig. 3, refer to the highlighted sections. Note: The key concept of this invention is disclosed in the flow chart, wherein, for each intermediate state (follow the “No” conditions) the cryptographic algorithm is verified with respect to the DRC.].
(As to claim 2, 9, 16, Wang discloses):2. The method of claim 1, wherein applying the stimulus to the hardware implementation further comprises mapping a signal of the hardware implementation to a corresponding equivalent element of the reference implementation [Fig. 5, 525, 530].
(As to claim 3, 10, 17, Wang discloses):3. The method of claim 2, wherein the equivalent element comprises at least one of a variable or function of the reference implementation [0086: “polygons and the nets or device have a data link reference to each other”].
(As to claim 4, 11, 18, Wang discloses):4. The method of claim 2, wherein mapping the signal of the hardware implementation to the corresponding equivalent element of the reference implementation [Fig. 5, 525, 530] further comprises receiving a user input specifying the mapping of the signal of the hardware implementation to the corresponding equivalent element of the reference implementation [0010: “user has no way to test it out by using his own proven verification flow.”].
(As to claim 5, 12, 19, Wang discloses):5. The method of claim 1, further comprising determining an expected output signal of the hardware implementation based upon the test case data and the reference implementation [Claim 16: “circuit verification tool to perform a circuit validation”] [Note: design verification is a well-known art in the semiconductor industry, which uses applying vector or stimulus and comparing the results with desired output].
(As to claim 6, 13, 20, Wang discloses):6. The method of claim 1, wherein generating the verification result is based upon occurrence of an event [Claim 16: “circuit verification tool to perform a circuit validation”. Note: well-known in the art of semiconductor verification.].
(As to claim 7, 14 Wang discloses):7. The method of claim 6, wherein the event includes at least one of receiving a predetermined output signal or after a predetermined period of time has passed [0015: “circuit validation checks, such as signal EM (Electro migration) and voltage drop check, SI (Signal Integrity) check and static timing check, etc.”].
Conclusion
The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851