Prosecution Insights
Last updated: August 09, 2026
Application No. 18/192,429

METHODS AND APPARATUS TO REDUCE LEAKAGE OF COOLING FLUID USED TO COOL AN ELECTRONIC COMPONENT

Non-Final OA §103
Filed
Mar 29, 2023
Examiner
CUMAR, NATHAN
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
951 granted / 1209 resolved
+18.7% vs TC avg
Moderate +15% lift
Without
With
+14.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
38 currently pending
Career history
1241
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
44.8%
+4.8% vs TC avg
§102
23.2%
-16.8% vs TC avg
§112
28.2%
-11.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1209 resolved cases

Office Action

§103
CTNF 18/192,429 CTNF 88029 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 1-8, 11-12, 16 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1 (Campbell et al., US Pub. 2008-0084664) in view of D2 (You et al., TW 201521564) . For claim 1, D1 discloses, in Figures 1-13, a seal assembly (cap, para. [0039]) comprising: a socket to receive an electronic component, the electronic component including a semiconductor die and a substrate to support the die (The space in which the electronic systems 913 are arranged defines the socket. Figure 9. Electronic system includes semiconductor 502 [para. 0052], die [para. 0036, 0040]); a first seal to be forced against the electronic component, the first seal to surround the die; and a second seal to be forced against the electronic component, the second seal to surround the first seal. D2 teaches a method of sealing an electronic with a cooling system. The system has a motherboard (p5, para. 8), and a seal 284 surrounding the heat dissipation body 210 (p.9, para. 9) for effective sealing, as in Figure 13. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify D1 with seal such that a first seal to be forced against the electronic component, the first seal to surround the die; and a second seal to be forced against the electronic component, the second seal to surround the first seal, as taught by D2 with a reasonable expectation of success of having an effective sealing environment. For claim 2, the combination teaches the seal assembly of claim 1, wherein the first seal is to be forced toward a surface of the substrate of the electronic component, the die mounted to the surface of the substrate (D1 discloses die on substrate [para. 0039]. D1 teaches sealing a heat sink in an electronic device, as shown in claim 1. D1 modified with teachings of D2 teaches the claimed limitations.) For claim 3, the combination teaches the seal assembly of claim 2, wherein the second seal is to be forced into direct contact with at least one of the substrate or a device stiffener disposed on the surface of the substrate (D1 discloses substrate [para. 0039]. D1 teaches sealing a heat sink in an electronic device, as shown in claim 1. D1 modified with teachings of D2 teaches the claimed limitations.) For claim 4, the combination teaches the seal assembly of claim 1, wherein the second seal has a first shape and the socket has a second shape, the first shape complementary to the second shape, the first shape of the second seal to align with the second shape of the socket (D2 teaches a seal 284 having a shape that compliments the space (socket) in which the seal is disposed, Figure 13. D1 modified with teachings of D2 teaches the claimed limitations.) For claim 5, the combination teaches the seal assembly of claim 1, wherein the first seal defines a first sealed area, the die to be positioned within the first sealed area, the first seal to retain a cooling fluid within the first sealed area (D1 discloses die [para. 0039]. D2 teaches a seal 284 and the area between seal 284 and body 210 defines the seal area. D1 modified with teachings of D2 teaches the claimed limitations.) For claim 6, the combination teaches the seal assembly of claim 5, wherein the second seal defines a second sealed area outside of the first sealed area, the second seal to retain a gas within the second sealed area (D2 teaches a cooling fluid passage [p.9, para. 5], and seal 284, Figure 13. D1 modified with teachings of D2 teaches the claimed limitations.) For claim 7, the combination teaches the seal assembly of claim 6, wherein the first sealed area is associated with a first pressure and the second sealed area is associated with a second pressure (D2 teaches cooling fluid passage [p.9, para. 5] carrying fluid at a pressure higher than the surrounding atmospheric pressure, and a seal 284. D1 modified with teachings of D2 teaches the claimed limitations.) For claim 8, D1 discloses the seal assembly of claim 7, further including a third area outside of the second sealed area that is exposed to an ambient atmosphere (Outside the capped area is at atmospheric pressure. Para. [0039].) For claim 11, D1 discloses, in Figures 1-13, a seal assembly (cap, para. [0039]) comprising: a socket to receive an electronic component (The space in which the electronic systems 913 are arranged defines the socket. Figure 9.); and a first seal to be urged into sealing engagement with the electronic component, the first seal to separate a first sealed area from a second sealed area, the first sealed area to contain a coolant, the coolant to directly contact the electronic component, the first sealed area to be at a first pressure, the second sealed area to be at a second pressure greater than the first pressure. D2 teaches a method of sealing an electronic with a cooling system. The system has a motherboard (p5, para. 8), and a seal 284 surrounding the heat dissipation body 210 and the sealing fluid conduit (p.9, para. 9) for effective sealing, as in Figure 13. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify D1 with seal such that a first seal to be urged into sealing engagement with the electronic component, the first seal to separate a first sealed area from a second sealed area, the first sealed area to contain a coolant, the coolant to directly contact the electronic component, the first sealed area to be at a first pressure, the second sealed area to be at a second pressure greater than the first pressure, as taught by D2 with a reasonable expectation of success of having an effective sealing environment. For claim 12, the combination teaches the seal assembly of claim 11, further including a second seal to be urged toward the electronic component, the second seal to surround the first seal, the second seal to define the second sealed area (D2 teaches a seal 284 surrounding the body 210 [p.9, para. 9]. D1 modified with teachings of D2 teaches the claimed limitations.) For claim 16, D1 discloses, in Figures 1-13, a method comprising: placing an electronic component into a socket (The space in which electronics system 913 is disposed defines the socket. Figure 9. The electronic system has semiconductor 502 [para. 0052], die [0036, 0039].); positioning an inner seal to interface with the electronic component, the inner seal to enclose a semiconductor die of the electronic component within an inner sealed area, the inner sealed area to contain cooling fluid to cool the electronic component; positioning an outer seal to interface with the electronic component, the outer seal to enclose the inner seal, an outer sealed area defined between the inner seal and the outer seal; and providing a gas to the outer sealed area (Air flow 115, para. [0037].) D2 teaches a method of sealing an electronic with a cooling system. The system has a motherboard (p5, para. 8), and a seal 284 surrounding the heat dissipation body 210 and the sealing fluid conduit (p.9, para. 9) for effective sealing, as in Figure 13. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify D1 with seal such that an inner seal is positioned to interface with the electronic component, the inner seal to enclose a semiconductor die of the electronic component within an inner sealed area, the inner sealed area to contain cooling fluid to cool the electronic component; and an outer seal is positioned to interface with the electronic component, the outer seal to enclose the inner seal, an outer sealed area defined between the inner seal and the outer seal, as taught by D2 with a reasonable expectation of success of having an effective sealing environment. For claim 19, D1 discloses the method of claim 16, wherein the inner sealed area is at a first pressure and the outer sealed area is at a second pressure, the method further including modulating the second pressure in response to changes in the first pressure (Capped module seal the electronic components, para. [0039]. Forced air cool the components, para. [0037]. Pressures inside and outside the cap are different.) 07-21-aia AIA Claim (s) 9-10, 13-15, and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1 (Campbell et al., US Pub. 2008-0084664) in view of D2 (You et al., TW 201521564) and further in view of D3 (Beckett et al., US Pub. 2021-0199647) . For claim 9, the combination teaches the seal assembly of claim 1, but does not disclose further including a package force applicator to force the first seal and the second seal against the electronic component (D3 teaches die [para. 0232] and applicator [para. 0232,0233] to completely seal the component. D1 modified with teachings of D3 teaches the claimed limitations.) For claim 10, The combination teaches the seal assembly of claim 9, wherein the package force applicator includes a channel to deliver a pressurized gas to an area between the first seal and the second seal (D2 teaches the fluid passage 298 carries cooling fluid. P.9, para. 5 and 7. D1 modified with teachings of D2 teaches the claimed limitations.) For claim 13, the combination teaches the seal assembly of claim 12, but does not disclose further including a package force applicator positioned between the first seal and the second seal, the first and second seals to be in sealing engagement with the package force applicator (D2 teaches seal 284. D3 teaches die [para. 0232] and applicator [para. 0232,0233] to completely seal the component. D1 modified with teachings of D2 and D3 teaches the claimed limitations.) For claim 14, the combination teaches the seal assembly of claim 13, wherein the package force applicator includes a channel to provide gas between the first and second seals to the second sealed area (D3 teaches die [para. 0232] and applicator [para. 0232,0233] to completely seal the component. D1 modified with teachings of D3 teaches the claimed limitations.) For claim 15, the combination teaches the seal assembly of claim 14, wherein the gas is at least one of air, nitrogen, or helium (D2 teaches Air cooled heat sink. P.9, para. [4]. D1 modified with teachings of D3 teaches the claimed limitations.) For claim 17, the combination teaches the method of claim 16, but does not disclose further including positioning a package force applicator, the package force applicator to enable a sealing force to be applied to the inner seal and the outer seal (D3 teaches die [para. 0232] and applicator [para. 0232,0233] to completely seal the component. D2 teaches seal 284. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify D1 modified with D2 to modify with a package force applicator, such that the package force applicator to enable a sealing force to be applied to the inner seal and the outer seal, as taught by D3 with a reasonable expectation of success of effective sealing of a component.) For claim 18, the combination teaches the method of claim 17, further including positioning a die force applicator, the die force applicator including a surface defining the inner sealed area (D1 discloses die, para. [0039]. D3 teaches die [para. 0232] and applicator [para. 0232,0233] to completely seal the component. D1 modified with teaches of D3 teaches the claimed limitations.) 07-21-aia AIA Claim (s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1 (Campbell et al., US Pub. 2008-0084664) in view of D2 (You et al., TW 201521564) and further in view of D4 (Renk et al., US 7,251,985) . For claim 20, D1 discloses the method of claim 19, further including detecting a failure of the inner seal by monitoring for changes in the second pressure (Possibility of leaks, para. [0071].) D4 teaches a method of detecting leaks. The system has first seal 23 (Col.7, L 1-4), a second seal (Col.7, L 18-30), and a pressure switch to detect leak due to pressure change (Col.4, L5-10) to provide a reliable sealing system. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify D1 with a failure detecting system that detects a failure of the inner seal by monitoring for changes in the second pressure, as taught by D4 with a reasonable expectation of success of providing a reliable sealing system. Conclusion Prior art made of record and not relied upon is considered pertinent to applicant's disclosure and provides example of invention. A few of the prior art cited but not applied includes Song (US Pub. 2015-0276798); Gao (US 12,089,370); and Chang (US Pub. 2020-0350229). Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN CUMAR whose telephone number is (571)270-3112. The examiner can normally be reached Monday thru Friday, 8:00 am to 5:00 pm EST. Examiner interviews are available via telephone, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, KRISTINA FULTON can be reached at 571-272-7376. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATHAN CUMAR/Primary Examiner, Art Unit 3675 Application/Control Number: 18/192,429 Page 2 Art Unit: 3675 Application/Control Number: 18/192,429 Page 3 Art Unit: 3675 Application/Control Number: 18/192,429 Page 4 Art Unit: 3675 Application/Control Number: 18/192,429 Page 5 Art Unit: 3675 Application/Control Number: 18/192,429 Page 6 Art Unit: 3675 Application/Control Number: 18/192,429 Page 7 Art Unit: 3675 Application/Control Number: 18/192,429 Page 8 Art Unit: 3675 Application/Control Number: 18/192,429 Page 9 Art Unit: 3675 Application/Control Number: 18/192,429 Page 10 Art Unit: 3675 Application/Control Number: 18/192,429 Page 11 Art Unit: 3675 Application/Control Number: 18/192,429 Page 13 Art Unit: 3675 Application/Control Number: 18/192,429 Page 14 Art Unit: 3675
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Prosecution Timeline

Mar 29, 2023
Application Filed
Aug 30, 2023
Response after Non-Final Action
May 05, 2026
Non-Final Rejection mailed — §103
Jul 17, 2026
Interview Requested
Jul 23, 2026
Applicant Interview (Telephonic)
Jul 23, 2026
Examiner Interview Summary

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
93%
With Interview (+14.6%)
2y 7m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1209 resolved cases by this examiner. Grant probability derived from career allowance rate.

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