CTNF 18/192,440 CTNF 82547 DETAILED ACTION This office action is in response to the application filed on 03/29/2023. Claims 1-20 are pending. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawing The drawing submitted on 03/29/2023 is acknowledged and accepted by the examiner. Information Disclosure Statement The information disclosure statements (IDS) submitted on 04/21/2025 has been considered by the examiner. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 7-9, 11-12, 17-18, and 20 are rejected under 35 U.S.C. 102( a)(1) and/or (a)(2 ) as being anticipated by IDE et al. (US Patent or PG Pub. No. 20230361782, hereinafter ‘782) . Claim 1, ‘782 teaches an apparatus (e.g., see Fig. 1-10), comprising: a control circuit to provide a request (e.g., the output of 6) for a current output (e.g., the current output of 3) from a power circuit (e.g., 3, 4), wherein the power circuit comprises a set of power links (e.g., 3), and each power link comprises a plurality of columns of transistors (e.g., MOS transistors of 3, 4); a first monitoring circuit (e.g., 11) to monitor a resistance of one or more replica columns (e.g., the on-resistance information regarding the replica circuit 4) and to provide a first output (e.g., the voltage at the node connecting 4, 11, 12) based on the resistance, wherein the one or more replica columns are replicas (e.g., 4) of the columns of transistors in the set of power links (e.g., see [0072], Fig. 4, 6-8, 10); a second monitoring circuit (e.g., 2) to monitor a dropout voltage (e.g., the differential voltage between Vout and Vref1, see [0051]) of the set of power links, and to provide a second output (e.g., D1) based on the dropout voltage (e.g., see Fig. 4, 6-8, 10); and a logic circuit (e.g., 6) coupled to the first monitoring circuit and the second monitoring circuit to provide control signals (e.g., the output of 6) to turn on or off power links in the set of power links, in response to the first output and the second output, to regulate an output voltage of the set of power links (e.g., Vout, see Fig. 4, 6-8, 10). Claim 2, ‘782 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the first output comprises an indication of a number of power links to turn on in the set of power links (e.g., the control circuit 6 generates a control signal for making the on-resistance of the corresponding transistors of the output stage circuit 3 match the on-resistance of the replica circuit 4, see [0056]). Claim 3, ‘782 teaches the limitations of claim 2 as discussed above. It further teaches that wherein the second output comprises an adjustment coefficient to adjust the number (e.g., the output of 6 being function of D2, see [0056][0057], Fig. 4, 6-8, 10). Claim 7, ‘782 teaches the limitations of claim 1 as discussed above. It further teaches that wherein a decoder (e.g., 6) is to connect or disconnect a transistor in each column to a ground voltage or another fixed bias in response to the request (e.g., the corresponding output of 6 mapping the respective gate input of 3 based on the states of D1, D2 and EN2, see Fig. 4, 6-8, 10). Claim 8, ‘782 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the control circuit is to provide the request based on a comparison between the output voltage of the set of power links and a target voltage (e.g., Vref1, see Fig. 4, 6-8, 10). Claim 9, ‘782 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the second monitoring circuit is to provide the second output based on a difference between a target voltage (e.g., Vref1) and a low-pass filtered version of an input voltage (e.g., Filtered Vout by C1, see Fig. 4, 6-8, 10) of the set of power links. Claim 11, ‘782 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the resistance is a drain-to-source resistance of the one or more replica columns (e.g., drain-to-source resistance of the MOS transistors of 3, 4, see Fig. 4, 6-8, 10). Claim 12, ‘782 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the control signals compensate for changes in an input voltage (e.g., the gate voltage of 3) of the set of power links while a ground voltage (e.g., the corresponding gate voltage of the respective transistor of 3 to be set to OFF) is applied to control gates of the transistors (e.g., see Fig. 4, 6-8, 10). Claim 17, ‘782 teaches a voltage regulator (e.g., see Fig. 1-10), comprising: a set of power links (e.g., 3) to generate an output voltage (e.g., Vout), wherein each power link comprises a plurality of columns of transistors; an output path coupled to the set of power links to provide power to a load (e.g., the load supplied by V out and I load , see Fig. 3, 4, 6-8, 10); a control circuit (e.g., 2, 6) to receive an output voltage (e.g., Vout) of the load and a target voltage (e.g., Vref1), wherein the control circuit is to provide an output voltage (e.g., Vout) on the output path based on an error between the target voltage and the output voltage (e.g., the differential voltage between Vout and Vref1, see [0051]); a first monitoring circuit (e.g., 11) to monitor a drain-to-source resistance of one or more replica columns (e.g., 4) and to provide a first output (e.g., the voltage at the node connecting 4, 11, 12) based on the drain-to-source resistance, wherein the one or more replica columns are replicas of the columns of transistors in the set of power links (e.g., see [0072], Fig. 4, 6-8, 10); a second monitoring circuit (e.g., 2) to monitor a dropout voltage of the set of power links (e.g., the differential voltage between Vout and Vref1, see [0051]), and to provide a second output (e.g., D1) based on the dropout voltage (e.g., see Fig. 4, 6-8, 10); and a logic circuit (e.g., 6) coupled to the first monitoring circuit, the second monitoring circuit and the output path (e.g., the output of 6) to regulate the output voltage (e.g., Vout, see Fig. 4, 6-8, 10). Claim 18, ‘782 teaches the limitations of claim 17 as discussed above. It further teaches that wherein the logic circuit is to open or close respective power link switches of the set of power link switches (e.g., the control circuit 6 generates a control signal for making the on-resistance of the corresponding transistors of the output stage circuit 3 match the on-resistance of the replica circuit 4, see [0056]). Claim 20, ‘782 teaches the limitations of claim 17 as discussed above. It further teaches that further comprising: for each power link, a plurality of column switches (e.g., the respective transistors of 3) to activate or inactivate columns of transistors of the plurality of columns of transistors of the power link (e.g., the respective transistors of 3 being active or deactivated by 6 based on the states of D1, D2 and EN2, see Fig. 4, 6-8, 10); and a decoder (e.g., 6) to provide control signals to the plurality of column switches of each power link of the set of power links (e.g., the corresponding output of 6 mapping the respective gate input of 3 based on the states of D1, D2 and EN2, see Fig. 4, 6-8, 10) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4-6, 10, 13-16, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 The following is a statement of reasons for the indication of allowable subject matters: For claim 4, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, … wherein when the dropout voltage is less than a threshold dropout voltage, the second output indicates the number of power links to turn on is to be overridden so that all of the power links are turned on. For claim 5, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, … wherein when the dropout voltage is between a lower threshold dropout voltage and an upper threshold dropout voltage, the second output indicates the number of power links indicated by the first output is to be reduced. For claim 6, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, … wherein when the dropout voltage is greater than a threshold dropout voltage, the second output indicates the number of power links indicated by the first output is not to be changed. For claim 10, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, … wherein: the one or more replica columns are in a local oscillator; and the first monitoring circuit is to determine a frequency of the local oscillator, and calculate the resistance based on the frequency. For claims 13-16, the prior art does not disclose or suggest, primarily, … a set of multipliers to provide the digital request, wherein to provide the digital request, the set of multipliers passes or blocks digital codes from a control circuit in response to a respective control signal from a logic circuit. For claim 19, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, … wherein the logic circuit is to turn on a larger number of power links of the set of power links when the drain-to-source resistance of the one or more replica columns is larger. Examiner's Note: Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JUE ZHANG/ Primary Examiner, Art Unit 2838 Application/Control Number: 18/192,440 Page 2 Art Unit: 2838 Application/Control Number: 18/192,440 Page 3 Art Unit: 2838 Application/Control Number: 18/192,440 Page 4 Art Unit: 2838 Application/Control Number: 18/192,440 Page 5 Art Unit: 2838 Application/Control Number: 18/192,440 Page 6 Art Unit: 2838 Application/Control Number: 18/192,440 Page 7 Art Unit: 2838 Application/Control Number: 18/192,440 Page 8 Art Unit: 2838 Application/Control Number: 18/192,440 Page 9 Art Unit: 2838
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