CTNF 18/192,449 CTNF 87379 Detailed Action 12-151 AIA 26-51 12-51 Status of Claims Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-20 are presented for examination. Claims 1-20 are rejected. This Action is Non-Final. Information Disclosure Statement 06-52 The information disclosure statement (IDS) submitted on 08/08/2024 and 01/23/2026,the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claims 1-20 are reje cted under 35 U.S.C. 103 as being unpatentable over Erez (US Patent Application Pub. No: 20190250930 A1) in view of Madigan et al. (US Patent Application Pub. No: 20200401205 A1). As pe r claim 1, Erez teaches an apparatus, comprising: a memory to store instructions [Fig.2; Paragraph 0024,… the SSD 204 includes a host interface 206, a controller 208, a volatile memory 210, and a non-volatile memory (NVM) 212.]; and a processor coupled to the memory [Paragraph 0022, … device A and device B each include one or more processors 112 and 114 to control various operations including PCIe operations and data communication between the devices.], wherein the processor is to execute the instructions to: determine a data rate associated with a Peripheral Component Interconnect Express (PCIe) link in an evaluation cycle [Paragraphs 0019;0030-0031, During hardware initialization, device A and device B negotiate the lane widths and frequency of operation used by the PCIe link. In general, the frequency of operation of the PCIe link increases in later PCIe generations, resulting in higher data rate per-lane.], wherein the link has a bandwidth at a start of the evaluation cycle, and the bandwidth represents a maximum available data rate of the link [Paragraphs 0019;0030-0031,… Each newer PCIe generation generally uses higher frequency to increase data rate of the PCIe link. PCIe generations may be referred to as technology generation in this disclosure….]; compare the data rate to one or more thresholds [claim 7; Paragraphs 0019;0030-0031,…,wherein the selecting the link configuration comprises: if the utilization rate is less than a predetermined value, selecting a link configuration to decrease the lane width of the serial data link; and if the utilization rate is greater than the predetermined value, selecting a link configuration to increase the lane width of the serial data link.]; and reduce the bandwidth in a remainder of the evaluation cycle based at least in part on whether the comparison indicates the data rate is below the one or more thresholds [claim 7; Paragraphs 0019;0030-0031,…, wherein the selecting the link configuration comprises: if the utilization rate is less than a predetermined value, selecting a link configuration to decrease the lane width of the serial data link;...]. Erze does not explicitly disclose evaluation cycle. Madigan discloses evaluation cycle [Paragraph 0088, … a circuit cell array of evaluator circuitry 550 comprises a row of cells CK11, CK21, . . . , CKI1 which are to perform respective evaluations for a first criterion—e.g., where a row of cells CK12, CK22, . . . , CKI2 are to perform respective evaluations for second criterion, and a row of cells CK1J, CK2J, . . . , CKIJ are to perform respective evaluations for Jth criterion.]. It would have been obvious one ordinary skill in the art before the effective filling, date of the claimed invention, to include Madigan ’s SOC for use in embedded applications for supporting operation as a component of a computing device into Erze ’s method for operating a first device using a dynamic serial data link for the benefit of the SOC facilitates chip area savings and better signal quality, less power consumption and high performance latency and the SOC enables wireless communications by a communication chip for transfer of data to and from a computing device ( Madigna ,[0103]) to obtain the invention as specified in claim 1. As per claim 2, Erze and Madigna teach all the limitations of claim 1 above, where Erze teaches, an apparatus, wherein the data rate is a maximum data rate of a plurality of downstream paths of the PCIe link [ Erze , Paragraphs 0019;0030-0031, … Each newer PCIe generation generally uses higher frequency to increase data rate of the PCIe link. PCIe generations may be referred to as technology generation in this disclosure….]. As per claim 3, Erze and Madigna teach all the limitations of claim 2 above, where Erze and Madigna teach, an apparatus, wherein the plurality of downstream paths are to transmit data from a system-on-a-chip [ Madigna , Paragraphs 0002; 0041-0043,…In a system-on-chip (SOC), circuit components of the SOC are integrated on a single chip. SOC integrated circuits are becoming ever more popular in various applications including embedded applications such as with set-top-boxes,…], to one or more peripherals via a discrete Universal Serial Bus host [ Erze , Paragraphs 0002; 0041-0043,…A Peripheral Component Interconnect (PCI) bus is a common connection interface for attaching computer peripherals to a host computer. Early versions of PCI use a parallel bus to connect the peripherals with the computer. Some examples of PCI peripherals are data storage systems, network cards, USB hubs, graphic cards, etc.]. As per claim 4, Erze and Madigna teach all the limitations of claim 1 above, where Erze and Madigna teach, an apparatus, wherein: the PCIe link is to transmit data from a system-on-a-chip to a discrete Universal Serial Bus host [ Madigna , Paragraphs 0002; 0041-0043,…In a system-on-chip (SOC), circuit components of the SOC are integrated on a single chip. SOC integrated circuits are becoming ever more popular in various applications including embedded applications such as with set-top-boxes,…]; and the evaluation cycle is triggered by connection of a peripheral to the discrete Universal Serial Bus host [ Erze , Paragraphs 0002; 0041-0043,…A Peripheral Component Interconnect (PCI) bus is a common connection interface for attaching computer peripherals to a host computer. Early versions of PCI use a parallel bus to connect the peripherals with the computer. Some examples of PCI peripherals are data storage systems, network cards, USB hubs, graphic cards, etc.]. As per claim 5, Erze and Madigna teach all the limitations of claim 1 above, where Erze and Madigna teach, an apparatus, wherein the PCIe link is to transmit data from a system-on-a-chip to a discrete Universal Serial Bus (USB) host [ Madigna , Paragraphs 0002; 0041-0043,…In a system-on-chip (SOC), circuit components of the SOC are integrated on a single chip. SOC integrated circuits are becoming ever more popular in various applications including embedded applications such as with set-top-boxes,…], and the processor is to increase a power state of the PCIe link in response to connection of a peripheral to the USB host [ Erze , Paragraphs 0002; 0041-0043,…A Peripheral Component Interconnect (PCI) bus is a common connection interface for attaching computer peripherals to a host computer. Early versions of PCI use a parallel bus to connect the peripherals with the computer. Some examples of PCI peripherals are data storage systems, network cards, USB hubs, graphic cards, etc.]. As per claim 6, Erze and Madigna teach all the limitations of claim 5 above, where Erze teaches, an apparatus, wherein the processor is to increase the power state from an L2/L3 state to an L1 sub state when the peripheral comprises a DisplayPort peripheral [ Erze , Paragraphs 0025-0027, …., after different periods of link idle, a device can transition from the active link state L0 to one of the power saving link states (e.g., L0s, L1, L1.2, etc.). The power saving link states are different in the amount of power saving and latency they provide before returning to the fully functional state L0.]. As per claim 7, Erze and Madigna teach all the limitations of claim 5 above, where Erze teaches, an apparatus, wherein the processor is to increase the power state from an L2/L3 state to an L0 state when the peripheral comprises a keyboard or mouse [ Erze , Paragraphs 0025-0027, …., after different periods of link idle, a device can transition from the active link state L0 to one of the power saving link states (e.g., L0s, L1, L1.2, etc.). The power saving link states are different in the amount of power saving and latency they provide before returning to the fully functional state L0.]. As per claim 8, Erze teaches an apparatus, comprising: a plurality of transmitters, wherein each transmitter of the plurality of transmitters is to transmit data on a respective downstream path of a bidirectional link [Paragraphs 0019;0027,The PCIe link 110 can include one or more lanes for transmitting and receiving data between the devices. Each lane includes a set of differential signal pairs, one pair for transmission and one pair for reception.]; a plurality of counters, wherein each counter of the plurality of counters is coupled to a respective transmitter of the plurality of transmitters to determine a respective data rate of the respective downstream path [Paragraphs 0019;0027,The PCIe link 110 can include one or more lanes for transmitting and receiving data between the devices. Each lane includes a set of differential signal pairs, one pair for transmission and one pair for reception.]; and a circuit to adjust a bandwidth of the respective downstream paths based on the respective data rates [Paragraphs 0017;0019,…, systems and methods for reconfiguring a Component Interconnect Express (PCIe) link to dynamically manage PCIe bandwidth to optimize power consumption and reduce underutilized bandwidth.]. Erze does not explicitly disclose a circuit to adjust a bandwidth. Madigna discloses a circuit to adjust a bandwidth [Paragraph 0024, The term “scaling” may also refer to adjusting (e.g., slowing down or speeding up—i.e., scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.]. It would have been obvious one ordinary skill in the art before the effective filling, date of the claimed invention, to include Madigan ’s SOC for use in embedded applications for supporting operation as a component of a computing device into Erze ’s method for operating a first device using a dynamic serial data link for the benefit of the SOC facilitates chip area savings and better signal quality, less power consumption and high performance latency and the SOC enables wireless communications by a communication chip for transfer of data to and from a computing device ( Madigna ,[0103]) to obtain the invention as specified in claim 8. As per claim 9, Erze and Madigna teach all the limitations of claim 8 above, where Madigna teaches, an apparatus, wherein to adjust the bandwidth, the circuit is to adjust a clock rate of a common clock signal of the plurality of transmitters [ Madigna , Paragraph 0024, The term “scaling” may also refer to adjusting (e.g., slowing down or speeding up—i.e., scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level.]. As per claim 10, Erze and Madigna teach all the limitations of claim 8 above, where Erze teaches, an apparatus, wherein: the bidirectional link is a Peripheral Component Interconnect Express (PCIe) link comprising a plurality of bidirectional lanes [ Erze , Paragraphs 0019;0030-0031, During hardware initialization, device A and device B negotiate the lane widths and frequency of operation used by the PCIe link. In general, the frequency of operation of the PCIe link increases in later PCIe generations, resulting in higher data rate per-lane.]; and each respective downstream path is in a respective lane of the plurality of bidirectional lanes [ Erze , Paragraphs 0019;0027,The PCIe link 110 can include one or more lanes for transmitting and receiving data between the devices. Each lane includes a set of differential signal pairs, one pair for transmission and one pair for reception.]. As per claim 11, Erze and Madigna teach all the limitations of claim 8 above, where Erze and Madigna teach, an apparatus, wherein: the plurality of transmitters, the plurality of counters and the circuit are in a first physical interface circuit [ Erze , Paragraphs 0019;0027,The PCIe link 110 can include one or more lanes for transmitting and receiving data between the devices. Each lane includes a set of differential signal pairs, one pair for transmission and one pair for reception.]; the first physical interface circuit is on a system-on-a-chip [ Madigan , Fig.3; Paragraphs 0035;0061,…SOC 100 is merely one example of an integrated circuit (IC) chip that determines a power mode for multiple components (also referred to herein as “functional blocks”) which have various respective power utilization characteristics that change over time.]; and the bidirectional link is to couple the first physical interface circuit to a second physical interface circuit on a discrete Universal Serial Bus host [ Erze , Paragraphs 0019;0027,The PCIe link 110 can include one or more lanes for transmitting and receiving data between the devices. Each lane includes a set of differential signal pairs, one pair for transmission and one pair for reception.]. As per claim 12, Erze and Madigna teach all the limitations of claim 8 above, where Madigna teaches, an apparatus, wherein: the circuit is to adjust the bandwidth in an evaluation cycle [ Madigna , Paragraphs 0068;0088, ….evaluator circuit 350 is coupled to receive signals 336 while evaluator circuit 350 is programmed or otherwise configured based on multiple criteria which each correspond to a different respective power mode of SOC 300.]; and the evaluation cycle includes a data rate calculation period in which the respective data rates are determined and a remainder in which the bandwidth is adjusted [ Madigna , Paragraphs 0068; 0088, … a circuit cell array of evaluator circuitry 550 comprises a row of cells CK11, CK21, . . . , CKI1 which are to perform respective evaluations for a first criterion—e.g., where a row of cells CK12, CK22, . . . , CKI2 are to perform respective evaluations for second criterion, and a row of cells CK1J, CK2J, . . . , CKIJ are to perform respective evaluations for Jth criterion.]. As per claim 13, Erze and Madigna teach all the limitations of claim 8 above, where Erze teaches, an apparatus, wherein the circuit is to adjust the bandwidth based on a comparison of a maximum data rate of the respective data rates to one or more thresholds [ Erze , Paragraphs 0019;0030-0031, … Each newer PCIe generation generally uses higher frequency to increase data rate of the PCIe link. PCIe generations may be referred to as technology generation in this disclosure….]. As per claim 14, Erze and Madigna teach all the limitations of claim 13 above, where Erze and Madigna teach, an apparatus, wherein: the bidirectional link is provided according to a Peripheral Component Interconnect Express (PCIe) standard [ Erze , Paragraphs 0019;0030-0031, During hardware initialization, device A and device B negotiate the lane widths and frequency of operation used by the PCIe link. In general, the frequency of operation of the PCIe link increases in later PCIe generations, resulting in higher data rate per-lane.]; and the one or more thresholds correspond to unidirectional per lane bandwidths of different generations of the PCIe standard [ Erze , Paragraphs 0019-0021,… During hardware initialization, device A and device B negotiate the lane widths and frequency of operation used by the PCIe link. In general, the frequency of operation of the PCIe link increases in later PCIe generations, resulting in higher data rate per-lane.]. As per claims 15- 20, claims 15- 20 is rejected in accordance to the same rational and reasoning as the above claims 1-7 above, wherein claims 15- 20 are the apparatus claims for the apparatus of claims 1-7. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion RELEVANT ART CITED BY THE EXAMINER The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c). References Considered Pertinent but not relied upon Das Sharman et al. (US Patent Application Pub. No: 20240311330 A1) teaches an apparatus, systems, techniques, or processes that are directed to on-package die-to-die (D2D) interconnects. Das Sharman discloses specifically, embodiments herein may relate to on-package D2D interconnects for memory that use or relate to the Universal Chiplet Interconnect Express (UCIe) adapter or physical layer (PHY); and other embodiments are described and claimed. Kommula et al. (US Patent Application Pub. No: 20230336447 A1) teaches a performance monitoring system includes a metric collector configured to receive, via metric exporters, telemetry data comprising metrics related to a network of computing devices. Kommula discloses a metric time series database stores related metrics; and an alert rule evaluator service is configured to evaluate rules using stored metrics. Kommula suggests the performance monitoring system may include a machine learning module and is configured to determine optimized metric collection sampling intervals and rule evaluation intervals, and to automatically determine recommended alert rules. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GETENTE A YIMER whose telephone number is (571)270-7106. The examiner can normally be reached on Monday-Friday 6:30-3:00.Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached on 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair my.uspto.gov/pair/ PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GETENTE A YIMER/Primary Examiner, Art Unit 2181 Application/Control Number: 18/192,449 Page 2 Art Unit: 2181
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