DETAILED ACTION
Claims 1-20 are pending.
The office acknowledges the following papers:
Oath filed on 1/24/2024,
Letter requesting suspension filed on 3/14/2024.
Priority
The effective filing date for the subject matter defined in the pending claims in this application is 9/26/2022.
Drawings
The Examiner contends that the drawings submitted on 03/29/2023 are acceptable for examination proceedings.
Specification
The disclosure is objected to because of the following informalities:
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The Applicant’s cooperation is requested in correcting any errors of which the Applicant may become aware.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Oberman et al. (U.S. 2001/0051969), in view of Moudgill et al. (U.S. 2018/0173527).
As per claim 1:
Oberman and Moudgill disclosed an apparatus comprising:
decoder circuitry to decode an instance of a single instruction (Oberman: Figures 4 and 39A elements 120 and 3120, paragraphs 129-130 and 286)(The decoder decodes the PF2ID instruction.), the instance of the single instruction to include at least one or more fields for an opcode (Oberman: Figures 28 and 39A elements 2304 and 3121, paragraphs 242 and 286), one or more fields for location information for at least a first source operand and a destination operand (Oberman: Figure 39A elements 3122A and 3122B, paragraph 286), wherein the opcode is to indicate that execution circuitry is to convert, using truncation or saturation, each floating-point data element of at least the first source operand to an integer value and store the integer value into a corresponding data element position of the destination operand (Oberman: Figures 4, 28, and 39A-B elements 136E, 2300, 2304, 3121, and 3122A-B, paragraphs 130, 145, 241-248, 254-256, and 286-287)(The opcode of the PF2ID instruction controls the execution logic to convert the packed floating-point data elements of the source register to integer elements to be stored in the destination register. The opcode controls processing of the instruction, which includes clamping values at a maximum/minimum value when outside of an allowable conversion range (i.e. saturation).), wherein truncation is to be used when a conversion is inexact (Moudgill: Figure 3 element 302, paragraphs 45 and 47-48)(Oberman: Figures 39A-C element 3128, paragraphs 10, 286-289)(Moudgill disclosed a floating-point to integer conversion instruction that includes rounding rules to handle undefined numbers/NaNs (e.g. inexact). The combination allows for Oberman to convert NaNs to the default rounding mode (i.e. truncation).) and saturation is to be used when a conversion overflows (Oberman: Figures 39A-B, paragraphs 286-287)(The opcode controls processing of the instruction, which includes clamping values at a maximum/minimum value (i.e. overflow/underflow) when outside of an allowable conversion range (i.e. saturation).); and
the execution circuitry to execute the decoded instance of the single instruction according to the opcode (Oberman: Figures 4, 28, and 39A elements 136E, 2300, 2304, and 3121, paragraphs 130, 145, 241-248, and 286)(Floating-point execution logic executes the PF2ID instruction.).
The advantage of implementing rounding rules for unsupported numbers or NaNs in conversion operations is that exception calls can be avoided. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the method of truncating NaNs in Moudgill within the vector conversion instructions of Oberman for the above advantage.
As per claim 2:
Oberman and Moudgill disclosed the apparatus of claim 1, wherein the one or more fields for location information for the first source operand are to identify a vector register (Oberman: Figure 39A element 3122B, paragraph 286)(In an embodiment, the source field identifies a vector source register.).
As per claim 3:
Oberman and Moudgill disclosed the apparatus of claim 1, wherein the one or more fields for location information for the first source operand to provide memory location information (Oberman: Figure 39A element 3122B, paragraph 286)(In an embodiment, the source field identifies a memory location.).
As per claim 4:
Oberman and Moudgill disclosed the apparatus of claim 1, wherein each of the floating-point values of the first source operand is to have a type that is one of a 4-bit floating point value, an 8-bit floating point value, a 16-bit floating point value, a 32-bit floating point value, or a 64-bit floating point value (Oberman: Figures 39A and 40A, paragraphs 286 and 290)(The source field identifies a source operand location storing either 16/32-bit floating point data elements, as indicated by the opcode.).
As per claim 5:
Oberman and Moudgill disclosed the apparatus of claim 4, wherein the type is identified by the opcode (Oberman: Figures 39A and 40A, paragraphs 286 and 290)(The source field identifies a source operand location storing either 16/32-bit floating point data elements, as indicated by the opcode.).
As per claim 7:
Oberman and Moudgill disclosed the apparatus of claim 1, wherein the instance of the single instruction is to indicate a rounding mode to be applied (Moudgill: Figure 3 element 302, paragraphs 45 and 47-48)(Oberman: Figures 39A-C element 3128, paragraphs 10, 286-289)(Moudgill disclosed a floating-point to integer conversion instruction that includes rounding rules to handle undefined numbers/NaNs (e.g. inexact). The combination allows for Oberman to convert NaNs to the default rounding mode (i.e. truncation).).
As per claim 15:
Claim 15 essentially recites the same limitations of claim 1. Claim 15 additionally recites the following limitations:
memory to store at least an instance of a single instruction (Oberman: Figure 4 element 114, paragraph 129);
wherein the decoder circuitry is to support instructions other than the single instruction (Oberman: Figure 4 elements 120 and 136A-E, paragraphs 129-130).
As per claim 16:
The additional limitation(s) of claim 16 basically recite the additional limitation(s) of claim 2. Therefore, claim 16 is rejected for the same reason(s) as claim 2.
As per claim 17:
The additional limitation(s) of claim 17 basically recite the additional limitation(s) of claim 3. Therefore, claim 17 is rejected for the same reason(s) as claim 3.
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claim 4. Therefore, claim 18 is rejected for the same reason(s) as claim 4.
As per claim 19:
The additional limitation(s) of claim 19 basically recite the additional limitation(s) of claim 5. Therefore, claim 19 is rejected for the same reason(s) as claim 5.
Claims 6, 8-14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Oberman et al. (U.S. 2001/0051969), in view of Moudgill et al. (U.S. 2018/0173527), further in view of Official Notice.
As per claim 6:
Oberman and Moudgill disclosed the apparatus of claim 1, wherein the instance of the single instruction further comprises one or more fields to provide location information for a second source operand (Oberman: Figure 39A element 3122B, paragraph 286)(In an embodiment, the source field identifies a vector source register. Official notice is given that vector instructions can use multiple source operands to select data elements for execution and movement into a destination register for the advantage of increasing code density. Thus, it would have been obvious to one of ordinary skill in the art to implement a second source operand within the vector conversion instruction of Oberman.).
As per claim 8:
Claim 8 essentially recites the same limitations of claim 1. Claim 8 additionally recites the following limitations:
translating an instance of a single instruction from a first instruction set architecture to one or more instructions of second instruction set architecture (Oberman: Figure 4 element 120, paragraph 129)(Official notice is given that non-supported ISA operations can be translated to supported ISA instructions in the front-end of processors for the advantage of executing non-native programs. Thus, it would have been obvious to one of ordinary skill in the art to implement an instruction translation unit in Oberman.).
As per claim 9:
The additional limitation(s) of claim 9 basically recite the additional limitation(s) of claim 2. Therefore, claim 9 is rejected for the same reason(s) as claim 2.
As per claim 10:
The additional limitation(s) of claim 10 basically recite the additional limitation(s) of claim 3. Therefore, claim 10 is rejected for the same reason(s) as claim 3.
As per claim 11:
The additional limitation(s) of claim 11 basically recite the additional limitation(s) of claim 4. Therefore, claim 11 is rejected for the same reason(s) as claim 4.
As per claim 12:
The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claim 5. Therefore, claim 12 is rejected for the same reason(s) as claim 5.
As per claim 13:
The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 6. Therefore, claim 13 is rejected for the same reason(s) as claim 6.
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 7. Therefore, claim 14 is rejected for the same reason(s) as claim 7.
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claim 6. Therefore, claim 20 is rejected for the same reason(s) as claim 6.
Conclusion
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Blomgren et al. (U.S. 9,264,066), taught type conversion using a FPU.
Rodriguez et al. (U.S. 7,103,621), taught floating-point conversion.
Handlogten et al. (U.S. 6,684,232), taught convert-to-integer operations.
Abdallah et al. (U.S. 6,292,815), taught packed data conversion operations.
Keith et al. (U.S. 5,764,548), taught fast floating-point conversion.
Poon (U.S. 5,257,215), taught floating point conversions in a floating-point adder.
Ito (U.S. 2020/0143232), taught floating-point to integer conversion.
Rovers (U.S. 2018/0278264), taught floating-point to fixed-point conversion.
Chauvel et al. (U.S. 2006/0026393), taught floating-point to integer instructions.
Ho et al. (U.S. 2016/0211862), taught floating-point to integer conversions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183