Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Finality of the Office Action
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Response to the Argument
Applicant’s arguments submitted on December 21, 2025, have been fully considered. While certain arguments are persuasive, others fail to establish error in the Examiner’s rejections, as explained below.
A. Ding Reference (U.S. Patent No. 10,992,266)
The Examiner agrees with Applicant’s argument that Ding does not disclose a protection circuit configured to cause a portion of the bias control current to flow to ground based on an amplification signal and a second signal derived from a first voltage, as recited in independent claim 1. Accordingly, Applicant’s argument with respect to Ding has been found persuasive.
B. Rejection of Claims 1 and 4 Over Gebeyehu in View of Tsutsui
Applicant’s arguments concerning the rejection of claims 1 and 4 based on Gebeyehu (US 2023/0079623) in view of Tsutsui (US 2019/0356288) are not persuasive.
Applicant asserts that “nothing in Gebeyehu describes using the battery voltage (Vbat) in the clamp circuit 324.” This assertion appears to overlook the disclosed power architecture of the system. Specifically, transistors 341a and 341b within the clamp circuit 324 are DC-biased from the battery voltage Vbat, as clearly understood by a person of ordinary skill in the art.
Active semiconductor devices cannot operate without a supply voltage. In Gebeyehu, the supply voltage for all active components of the mobile device illustrated in Figure 7 is provided by battery 808 via the power management circuit 805. The amplifier circuitry shown in Figure 6, including power amplifiers 811, is part of this same mobile device architecture. Thus, the clamp circuit necessarily operates using the battery voltage, whether explicitly labeled at each transistor terminal or not.
C. Claim 3 – Load-Based Signal Argument
Applicant’s argument regarding claim 3—specifically, the limitation reciting “a protection circuit configured to cause part of the bias control current to flow to ground based on a third signal based on a change in the load”—appears to rely on an unduly narrow or specialized interpretation of the term “load” that is inconsistent with its ordinary meaning in the art.
Applicant acknowledges that Gebeyehu discloses operation of the clamp circuit based on the RF output of the amplifier yet fails to recognize that amplifier output inherently varies with changes in load. This principle is well known in the art. As the load changes, the load current correspondingly changes, which in turn alters the voltage drop across the detector diode 331 (see Figure 6 of Gebeyehu) within the protection circuit. Accordingly, the clamp circuit response is necessarily load-dependent, satisfying the recited limitation.
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D. Claims 2 and 5 – Capacitive Coupling in an Operational Amplifier
With respect to claims 2 and 5, Applicant’s argument reflects a misunderstanding of capacitive coupling between the input and output of an operational amplifier. As is well established in the art, a typical operational amplifier includes an internal compensation capacitor (Cc) that provides a significant capacitive path between the output and an internal input node. This intrinsic capacitive coupling satisfies the claimed limitation.
E. Claims 6 and 7 – Identification of the “First Transistor”
Regarding claims 6 and 7, Applicant appears to interpret the “first transistor” as the power amplifier 325. However, the Examiner has consistently identified FET 372 as the first transistor, as claims 6 and 7 expressly refer back to the protection circuit recited in claims 2 and 5.
To the extent Applicant argues that FET 372 is not powered by the low-dropout regulator (LDO) of operational amplifier 371, attention is directed to the disclosed electrical connections between the supply voltage terminals of op-amp 371 and FET 372, which demonstrate that both devices are powered from the same supply source.
F. Claims 8 and 9 – Inclusion of a Controller
Finally, Applicant’s arguments regarding claims 8 and 9 suggest a misunderstanding of the relationship between the controller and the protection circuit. The controller is not a separate or unrelated component; rather, it is an integral part of both the protection circuit and the bias control circuitry.
The protection circuit functions to regulate and control the bias current supplied to the power amplifiers, and the controller performs this function by monitoring conditions and adjusting bias accordingly. As such, inclusion of the controller within the protection circuit is fully consistent with the claimed limitations.
For the reasons set forth above, Applicant’s arguments do not overcome the rejections of claims 1–9, except as noted with respect to Ding. The rejections based on Gebeyehu in view of Tsutsui are therefore maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-11, 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Gebeyehu (US 2023/0079623 A1 effectively filed on September 14, 2021) in view of TSUTSUI et al. (US 2019/0356288 Al).
Regarding claims 1, 3-4, Gebeyehu discloses (in Fig. 6) a power amplifier circuit (380, §0132) comprising:
a first amplifier1 (first stage of the two-stage amplifier 321, §0133) configured to operate in accordance with a first voltage supplied from a voltage supply source (the power management circuit 805 essentially powering all the active devices of the mobile device 800 of Fig. 7 from the battery 808, §0151-§0152) to amplify a first signal, and to output an amplification signal;
a bias transistor (a first biasing bipolar transistor 331a, §0135) that has a base to which a bias control current (from the current mirror 363 is provided to the base of 331, §0138) is supplied, and an emitter (emitter of 331a) configured to supply a bias (base bias current to the amplifier 321, §0135) to the first amplifier (321) 2; and (essentially Vbat), to amplify a first signal (RFin), and to output an amplification signal (RFout, §0134);
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Fig. 6 of Gebeyehu annotated by the examiner for ease of reference.
a protection circuit (clamp circuit 324) configured to cause part of the bias control current (current mirror 363 output current) to flow to ground (through transistor 341a) based on the amplification signal (RF output coupled through the coupler circuit 302 and detected by the detector 323, §0138) and a second signal based on the first voltage (Vbat3).
However, Gebeyehu does not explicitly teach the first resistor through which the bias transistor (331a)’s emitter biases the first amplifier (321) as recited in claim 1.
TSUTSUI in similar filed of endeavor teaches (in Fig. 2) in a power amplifier circuit (100A) with bias transistor (Q3) having resistors (specifically resistor R1) connected between the emitter of the bias transistor (Q3) and the base of the amplifier transistor (Q2), demonstrating the known practice of using resistors in bias networks of power amplifier circuits.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the power amplifier circuit of Gebeyehu to include the resistor connection as taught by TSUTSUI, as this represents a conventional design choice for implementing proper bias distribution in amplifier circuits. The motivation would be to provide through resistor R1, stability in RF amplifier design where R1 provides lossy feedback from the output back to the input stage This controlled feedback prevents unwanted oscillations that could occur due to parasitic feedback paths in high-frequency circuits. R1 helps flatten the gain response across the desired frequency band also this resistive feedback (of R1) helps maintain stable operation across temperature variations wherein the resistance value can be optimized for the specific application requirements.
Further, per claims 2 and 5, Gebeyehu also teaches a first transistor (FET 372) that has a gate connected to ground (below resistor 374) via a first capacitor (through the op-Amp 371), and a source (just above the resistor 311) to which the amplification signal (RF coupled out) is input through a second capacitor (314); and
a second transistor (341a) that has a collector connected to the base of the bias transistor (331a), a base connected (through the detector diode 331 to the source of the first transistor (FET 372), and an emitter connected to ground.
Wherein per claims 6 and 7, the gate of the first transistor (372) in the protection circuit is connected to the voltage supply source4 (LDO, through an op-Amp 371). wherein per claim 7 (already discussed regarding claim 1), the first amplifier (first stage of the two-stage amplifier 321, §0133) is configured to operate in accordance with a first voltage supplied from a voltage supply source (battery 808 and power management circuit 805 as shown in Fig. 7, §0151-§0152)
Further per claims 8 and 9, a voltage shift circuit (op-Amp 371, resistors 373, 374 in parallel with resistor 311) that is connected between the gate (through the op-Amp 371) of the first transistor (FET 372) in the protection circuit and the voltage supply source (LDO), and that is configured to shift the first voltage (DC equivalent of the RF output voltage coupled through the output coupler 302), wherein the voltage shift circuit comprises a first diode (323 that rectifies the RF into DC).
wherein per claims 10 and 11, the gate of the first transistor (372) in the protection circuit is connected (connected through the current mirror 363) to the base of the bias transistor (371a).
Further per claims 14 and 15, a second amplifier (326 i.e., the second stage of the amplifier 321) that is in a stage after the first amplifier (325, i.e., the first stage of the amplifier 321); and
a bias supply circuit (322) that is configured to supply a bias to the second amplifier based on a current supplied from a control current source (303),
wherein the gate of the first transistor (372) in the protection circuit is connected to the control current source (303).
Allowable Subject Matter
Claims 12-13 and 16-20 are objected to as being dependent upon a rejected base claim 1 but would be allowable if rewritten in independent form including all of the limitations of the base claim 5 and any intervening claims.
Claims 12 and 13 are allowable because the closest prior art of record, Gebeyehu is not explicit about a second resistor (?, there is a current mirror transistor 363 but no resistor) that is connected between the gate (output of op-Amp 371)of the first transistor (372) in the protection circuit and the base of the bias transistor (371a) as claimed.
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Fig. 5 of Dutta reproduced by the examiner for ease of reference.
Claims 16-19 are allowable because the closest prior art of records, Ding, Gebeyehu or Tsutsui are not explicit about differential pair that comprises a second amplifier and a third amplifier with balun at the output of the first amplifier with multiple electromagnetically coupled inductors supplying the voltage to the amplifiers as claimed. Although such an arrangement is well within the purview of a person of ordinary skill in the art of Radio frequency (RF) amplifiers for portable devices specific, such as, Dutta (US 12375046 B2, effectively filed May 20, 2021).
However, modification to the prior art of record specially implementing the protection circuit as stated in Gebeyehu for differential configuration may not readily yield expected results and thereby rendering obviousness rejection based on differential amplifiers.
Claim 20 is allowable because the closest prior art of record, in Gebeyehu Fig. 6, a second and a third inductor is not apparent where the first end of the second capacitor is connected as claimed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
1 In some embodiments, the transistor Ql is connected or configured in a common emitter (CE) arrangement. The transistor Q2 is connected or configured in a common base (CB) arrangement. The transistor Ql and the transistor Q2 may be configured or connected to define a cascade amplifier (col. 3, lines 1-5).
2 Gebeyehu is not explicit about a resistor at the emitter of the biasing transistor 331a.
3 Vbat is essential for the powering any transistor in the circuit which is true for the clamping transistor 341a.
4 (Gebeyehu: §138) a low dropout (LDO) regulator including an amplifier 371 (receiving a reference voltage Vref), a regulation FET 372, a first voltage divider resistor 373, and a second voltage divider resistor 374. The LDO regulator 371 generates a regulated voltage Vreg that is provided to the resistor 311 and to the rectifying diode 331 to serve as a threshold voltage for the power detector 311. By controlling the reference voltage Vref (and/or other suitable parameter such as the ratio of resistances of the voltage divider resistors), the threshold voltage for power detection can be controlled.