Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final Office Action
DETAILED ACTION
Examiner’s Notes
(a) Claim date: 03/30/2023.
(b) Priority date: NA
(c) Invention: Timing modeling while considering constraints of multiple clock domains.
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1-20, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of record “Abdul” <US 20170337313 A1>.(As to claim 1, 9, 17 Abdul discloses):1. A method for timing analysis of an integrated circuit, the method comprising [0001: “timing analysis of integrated circuit designs”]:
defining a plurality of intent groups for an integrated circuit design [Fig. 3, 310; Note: macro is functionally equivalent to group],
each intent group associated with a different clock type of the integrated circuit design [Fig. 3, 310];
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associating a different timing phase of a plurality of timing phases of one or more clock signals of the integrated circuit design with each intent group [Fig. 2, 320; note: “timing phase” is functionally equivalent to “clock domain”, (which possess different clock/timing phases)];
associating one or more timing constraints with each of the intent groups [0020: “timing constraints associated with the clock domain or domains for which detailed timing analysis was performed (at block 210)”, Note: intent groups is functionally equivalent to “clock domain”]; and
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computing a timing result based on propagating the timing phases of each of the intent groups and applying the associated timing constraints from an input to a timing point of the integrated circuit design [Fig. 5, 550, 560 and 570].
(As to claim 2, 10, 18 Abdul discloses):2. The method of claim 1, further comprising:
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applying a design change to the integrated circuit design to produce a changed integrated circuit design [Fig. 4, 410 (mapping adjustments)]; and
recomputing the timing result based on propagating the timing phases of each of the intent groups [Fig. 5, 550] and applying the associated timing constraints from the input to the timing point of the changed integrated circuit design [Fig. 5, 570].
(As to claim 3, 11, 19 Abdul discloses):3. The method of claim 1, further comprising: generating a timing abstract including an association of each of the intent groups with a respective timing result and applied timing constraint [Fig. 5, 550 and 560; Note: the claim limitation unclear. It is reasonably and broadly interpreted as “perform timing modeling”)].
(As to claim 4, 12, 20 Abdul discloses):4. The method of claim 1, further comprising:
associating each of the plurality of intent groups with a particular intent group index value [Fig. 3, 330; Note: the “generalized timing constraints” is functionally equivalent to “group index”]; and
storing the association of the intent group with the particular intent group index value in an index [Fig. 3, 340 Note: the “generalized timing constraints” is functionally equivalent to “group index”].
(As to claim 5, 14, Abdul discloses):5. The method of claim 4, wherein associating a different timing phase of a plurality of timing phases of one or more clock signals of the integrated circuit design with each intent group further comprises associating a particular timing phase with the particular index value [Note: this limitation is unclear; thus, it is broadly interpreted as one of the functional elements of the “timing modeling” as shown in Fig. 5, 560].
(As to claim 6, 13, Abdul discloses):6. The method of claim 1, wherein the plurality of intent groups includes one or more of a functional intent group, a scan intent group, an array test intent group, and a margining intent group [0020: “timing constraints associated with the clock domain or domains for which detailed timing analysis was performed (at block 210)”, Note: “intent group” is functionally equivalent to “clock domain”. Also, it is well known in the art that each clock domain (i.e. intent group), may have different clock frequency and may perform various logic functions, such as “scan, storage, test and etc.” as claimed].
(As to claim 7, 15, Abdul discloses):7. The method of claim 1, further comprising retrieving the one or more timing constraints from a database [Fig. 3, 340 (obtain timing constraints)].
(As to claim 8, 16, Abdul discloses):8. The method of claim 7, wherein the database includes one or more functional circuitry component designs and associated timing constraints [Claim 14, “obtaining original constraints associated with one or more circuit elements within the component from the clock domain” and “storage medium having program instruction”].
Conclusion
The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851