The present application, filed on or after March 16, 2013, is being examined under first to invent provisions of the AIA .
DETAILED ACTION
This Action is in response to communications filed 10/15/2025.
Claims 1 and 15 are amended.
Claims 1-20 are pending.
Claims 1-14 and 17-20 are rejected. Claims 15 and 16 are allowed.
Response to Arguments
Applicant`s arguments filed October 15, 2025 have been fully considered but they are not persuasive.
As per the prior art rejection of claim1 1, Applicant argued that the combination of Basu/Beard fails to teach or suggest " configured to include a lookup for an additional memory address, the additional memory address selected by the cache coherence controller based on the memory address ". However, Examiner relies on a newly cited references Averill to teach these limitations.
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 07/15/2025 and 10/15/2025. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “data associated with the additional memory address” would have been indefinite to one of ordinary skill in the art at the time of the invention. One of ordinary skill would not have known the metes and bounds of whether the data is part of the memory address or part of metadata related to the memory address or else.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “data stored at the memory address” , where it is unclear if the data is the same data associated with the memory address or part of metadata related to the memory address or else.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “data stored at the memory address”, where it is unclear if the data is the same data from the additional memory address as in claim 15 or else.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “data stored at the memory address and the additional memory address”, where it is unclear if the data is the same data from the additional memory address as in claim 15 or else.
Claim 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “the data at the memory address or the additional memory address”, where there is an insufficient antecedent basis for this limitation there is no reference to any data in the additional memory address.
Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “a memory module”, where it is unclear if this is the same memory module as in claim 19 or else.
All dependent claims are rejected as having the same deficiencies as the claims they depend from.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5 and 14 are rejected under 35 U.S.C. 103(a) as being disclosed by Basu et al. (US PGPUB 2017/0337136 hereinafter referred to as Basu), in view of Beard et al. (US PGPUB 2019/00018786 hereinafter referred to as Beard), and further in view of Averill et al. (US PGPUB 2008/0307169 hereinafter referred to as Averill).
As per independent claim 1, Basu discloses a system comprising: a cache system including a plurality of cache levels [(Paragraphs 0036-0038; FIGs. 1 and 2 and related text) wherein Basu teaches that the caches in computing device 100 include a level-one (L1) cache 114 (“L1 114”) in each CPU 110 and CU 112. Each L1 cache 114 includes memory circuits such as one or more of static random access memory (SRAM), DRAM, DDR SDRAM, and/or other types of memory circuits for storing (i.e., locally caching) copies of data and instructions for use by the corresponding CPU 110 or CU 112, as well as control circuits for handling accesses of the data and instructions that are stored in the memory circuits. In some embodiments, the L1 caches 114 are the smallest of the caches in computing device 100 (in terms of the capacity of the memory circuits) and are located closest to the functional blocks (e.g., execution units, instruction fetch units, etc.) that use the data and instructions in the corresponding CPU 110 or CU 112. The caches in computing device 100 also include a shared level-two (L2) cache in each of CPU cluster 102 (i.e., CPU cluster L2 cache 116) and GPU 104 (GPU L2 cache 118). Each of CPU cluster L2 cache 116 and GPU L2 cache 118 include memory circuits such as one or more of SRAM, DRAM, DDR SDRAM, and/or other types of memory circuits for storing copies of data and instructions for use by each of the CPUs 110 and the CUs 112, respectively, as well as control circuits for handling accesses of the data and instructions that are stored in the memory circuits. In some embodiments, the L2 caches are larger than the L1 caches, and are located further than L1 caches from the functional blocks that use the data and instructions. The caches in computing device 100 further include a shared level-three (L3) cache 120 that includes memory circuits such as one or more of SRAM, DRAM, DDR SDRAM, and/or other types of memory circuits for storing copies of data and instructions for use by CPU cluster 102 (i.e., by the CPUs 110, etc.) and GPU 104 (i.e., by the CUs 112, etc.), as well as control circuits for handling accesses of the data and instructions that are stored in the memory circuits. In some embodiments, L3 cache 120 is the largest of the caches in computing device 100, and is located the furthest from the functional blocks that use the data and instructions (relative to the L1 and L2 caches) to correspond to the claimed limitation]; and a cache coherence controller configured to perform a cache directory lookup using a cache directory [(Paragraphs 0036-0039; FIGs. 1 and 2 and related text) wherein Basu teaches wherein when accessing data, a given CPU 110 or CU 112 may first check the corresponding/local cache hierarchy to determine if the data is stored in a local cache, and may then proceed to perform a lookup in coherence directory 128 when the data is not found to be cached locally (depending on the state of corresponding cache coherency indicators, as described herein to correspond to the claimed limitation], the cache directory lookup: configured to indicate whether data associated with a memory address specified by a memory request is valid in memory [(Paragraphs 0036-0038, 0044 and 0060; FIGs. 1 and 2 and related text) wherein Basu teaches wherein when accessing data, a given CPU 110 or CU 112 may first check the corresponding/local cache hierarchy to determine if the data is stored in a local cache, and may then proceed to perform a lookup in coherence directory 128 when the data is not found to be cached locally (depending on the state of corresponding cache coherency indicators, as described herein; Coherence directory 128 is a functional block that performs operations for enforcing coherency between the caches (L1 caches 114, L2 caches 116 and 118, and L3 cache 120) and memory 106. In some embodiments, coherence directory 128 includes various circuits and/or other hardware that maintain records of cache blocks (e.g., cache lines of a given size) that are stored in caches in computing device 100. In other words, when a copy of data from memory 106 is stored or otherwise changed in a given cache, a corresponding record is added or updated in coherence directory 128. In these embodiments, the records maintained by coherence directory 128 may include an identifiers for cache blocks, the coherence state in which the cache blocks are held (e.g., one of the well-known MESI or MOESI coherence states), the number or identifiers of caches that hold copies of the cache blocks, and/or other information for enforcing coherency. As described herein, depending on the state of the cache coherency indicator, a corresponding CPU 110 or CU 112 may (or may not) perform a lookup in coherence directory 128 to ascertain whether corresponding data is cached is cached in a remote cache hierarchy. For example, based on the state of the cache coherency indicator, a memory management unit 122 in a CPU 110 may (or may not) signal a permission fault to an operating system in CPU 110 that causes the operating system (and/or another hardware or software entity), while searching various caches for the data, to perform a lookup in coherency directory 128 to determine if corresponding data is cached in a cache hierarchy in GPU 104 to correspond to the claimed limitation];.
Basu does not appear to explicitly disclose the cache directory lookup augmented to include an additional memory address based on the memory address.
However, Beard discloses the cache directory lookup augmented to include an additional memory address based on the memory address [(0052-0057 and 0108-0110; FIGs. 1 and 2) where the coherency controller 154 including the snoop filter provides an example of a cache coherency controller configured to coordinate, amongst the cache memories, an access to a memory address by one of the cache memories when the directory indicates that another of the cache memories is caching that memory address. The snoop controller stores or provides a directory such as the directory mentioned above indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable in a coherent cache structure; the range table buffers (RTBs) 105, 115 operate by storing one or more instances of translation data. FIG. 2a schematically illustrates such an instance of translation data. Referring to FIG. 2a, an instance (or indeed each instance) of translation data is formed as a 224-bit word comprising 22 reserved bits 200, 10 bits of administrative data discussed below) 205, 64 bits of address offset data 210, 64 bits of “base virtual address” data 220 and 64 bits of range data 230. The data 220, 230 together define a range of virtual memory addresses between respective virtual memory address boundaries in the virtual memory address space, the range of virtual memory addresses is between the address represented by Base VA up to and including the address represented by Base VA+Range to correspond to the claimed limitation].
Basu and Beard are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Basu and Beard before him or her, to modify the method of Basu to include the coherency controller of Beard because it will enhance fail detection.
The motivation for doing so would be [“enables an out of coherence network device to signal a range of addresses to be modified with a specific coherence state. Subsequently, the range based coherence modification mechanism issues the state modification only for those lines that are extant in the cache and not already in the proper state. This approach greatly reduces the amount of bus traffic required for each range coherence modification” (Paragraph 0031 by Beard)].
Basu/Beard does not appear to explicitly disclose configured to include a lookup for an additional memory address, the additional memory address selected by the cache coherence controller based on the memory address.
However, Averill discloses configured to include a lookup for an additional memory address, the additional memory address selected by the cache coherence controller based on the memory address [(Paragraphs 0050-0053; FIGs. 1 and 5) where FIG. 5A in response to coherence directory 200 receiving a directory lookup request from request handler 208 at block 406 of FIG. 4A and as shown at reference numeral 212 of FIG. 2. In response to receipt of the directory lookup request, the address control logic 320 of each directory slice 310 makes a determination, as shown at block 502, of whether the target real memory address is assigned to that directory slice 310. Each instance of address control logic 320 may make the determination depicted at block 502, for example, by hashing the specified target real memory address or by comparing the target real memory address to the contents of one or more address range registers. In response to address control logic 320 determining at block 502 that the target real memory address is not assigned to its directory slice 310, address control logic 320 discards the directory lookup request, and the process terminates at block 503. If, however, an instance of address control logic 320 determines at block 502 that the directory lookup request is for a real memory address assigned to its directory slice 310, the process proceeds to blocks 504 and 506, which depict operations performed at stage 0 of a directory pipeline 326. Block 504 depicts address control logic 320 enqueuing the directory lookup request in the directory queue (DIRQ) 322 of the directory array bank 314 to which the target real memory address maps. As noted above, in one embodiment, target real memory addresses corresponding to odd multiples of the memory block size (e.g., 128) are assigned to directory array bank 314a, and target real memory addresses corresponding to even multiples of the memory block size are assigned to directory array bank 314b. As shown at block 506, the recipient directory queue 322 initiates a lookup of the target address in prefetch sector cache 324, preferably in parallel with the enqueuing operation illustrated at block 504. Because the prefetch sector cache 324 is small and implemented utilizing latches (or other high speed storage circuitry), results of the lookup of prefetch sector cache 324 can often be obtained in the same clock cycle that the directory lookup request is enqueued in directory queue 322. If the target real memory address hits in prefetch sector cache 324 at block 508 (e.g., due to the other sector 318 of the same directory entry 316 being recently accessed), prefetch sector cache 324 provides a hit indication and the coherency information for the requested sector 318 to the directory queue 322 (block 510). Following block 510 or in response to a determination at block 508 that the directory lookup request missed in prefetch sector cache 324, processing of the directory lookup request proceeds to stage 1 of the directory pipeline 326 to correspond to the claimed limitation].
Basu/Beard and Averill are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Basu/Beard and Averill before him or her, to modify the method of Basu to include the lookup operation of Averill because it will enhance latency performance.
The motivation for doing so would be [“directory access latency is reduced for a sectored directory by utilizing a sector prefetch cache to temporarily cache non-requested sectors of directory entries for which the coherency information is likely to soon be requested” (Paragraph 0061 by Averill)].
Therefore, it would have been obvious to combine Basu/Beard and Averill to obtain the invention as specified in the instant claim.
As per dependent claim 4, Basu wherein the cache directory includes a plurality of cache directory entries that indicate memory addresses are maintained in the cache system [(Paragraph 0044; FIG. 1) where the coherence directory 128 is a functional block that performs operations for enforcing coherency between the caches (L1 caches 114, L2 caches 116 and 118, and L3 cache 120) and memory 106. In some embodiments, coherence directory 128 includes various circuits and/or other hardware that maintain records of cache blocks (e.g., cache lines of a given size) that are stored in caches in computing device 100. In other words, when a copy of data from memory 106 is stored or otherwise changed in a given cache, a corresponding record is added or updated in coherence directory 128. In these embodiments, the records maintained by coherence directory 128 may include an identifiers for cache blocks, the coherence state in which the cache blocks are held (e.g., one of the well-known MESI or MOESI coherence states), the number or identifiers of caches that hold copies of the cache blocks, and/or other information for enforcing coherency. As described herein, depending on the state of the cache coherency indicator, a corresponding CPU 110 or CU 112 may (or may not) perform a lookup in coherence directory 128 to ascertain whether corresponding data is cached is cached in a remote cache hierarchy to correspond to the claimed limitation].
As per dependent claim 5, Basu wherein the plurality of cache directory entries specify, respectively, a location of respective memory addresses in the plurality of cache levels in the cache system and a status of the respective memory addresses [(Paragraph 0044; FIG. 1) where the coherence directory 128 is a functional block that performs operations for enforcing coherency between the caches (L1 caches 114, L2 caches 116 and 118, and L3 cache 120) and memory 106. In some embodiments, coherence directory 128 includes various circuits and/or other hardware that maintain records of cache blocks (e.g., cache lines of a given size) that are stored in caches in computing device 100. In other words, when a copy of data from memory 106 is stored or otherwise changed in a given cache, a corresponding record is added or updated in coherence directory 128. In these embodiments, the records maintained by coherence directory 128 may include an identifiers for cache blocks, the coherence state in which the cache blocks are held (e.g., one of the well-known MESI or MOESI coherence states), the number or identifiers of caches that hold copies of the cache blocks, and/or other information for enforcing coherency. As described herein, depending on the state of the cache coherency indicator, a corresponding CPU 110 or CU 112 may (or may not) perform a lookup in coherence directory 128 to ascertain whether corresponding data is cached is cached in a remote cache hierarchy to correspond to the claimed limitation].
As per dependent claim 14, Basu wherein the memory request is received from a core of a processing unit [(Paragraphs 0003 and 0070) wherein when a requesting processor is to access data (e.g., write the data, read the data, etc.), the requesting processor sends a request to the corresponding coherence directory and the coherence directory causes the data, when the data is stored in a cache in a corresponding other processor, to be returned to the requesting processor from the cache in the other processor (e.g., when the other processor has a modified copy of the data). The requesting processor caches the data locally (i.e., stores the received data in a local cache) and accesses the cached data to correspond to the claimed limitation].
Claims 2 and 3 are rejected under 35 U.S.C. 103(a) as being disclosed by Basu/Beard/Averill, as applied to claim 1, and further in view of Kim et al. (US PGPUB 2023/0418474 hereinafter referred to as Kim).
As per dependent claim 2, Basu/Beard discloses the system of claim 1.
Basu/Beard does not appear to explicitly disclose wherein the cache directory lookup is configured to indicate whether the data associated with the memory address specified by the memory request is valid in memory for use as part of a processing-in-memory operation by a processing-in-memory component.
However, Kim discloses wherein the cache directory lookup is configured to indicate whether the data associated with the memory address specified by the memory request is valid in memory for use as part of a processing-in-memory operation by a processing-in-memory component [(Paragraphs 0120-0127 and 0135; FIG. 8) wherein when the address requested by the memory request received from the outside corresponds to the PIM address information registered in the control register set 52, the operand corresponding to the PIM address information is valid, and the memory request corresponds to a read command or a write command, the PIM Request Identification Unit 54A of the Memory Controller 30 is configured to provide the PIM request identification signal obtained by identifying the PIM request to correspond to the claimed limitation].
Basu/Beard and Kim are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Basu/Beard and Kim before him or her, to modify the method of Basu/Beard to include the PIM operations of Kim because it will enhance system performance.
The motivation for doing so would be [“performs an operation inside the semiconductor memory in order to prevent congestion occurring during data movement, such as may occur in the machine learning, high-performance computing, and big data processing fields” (Paragraph 0004 by Kim)].
Therefore, it would have been obvious to combine Basu/Beard and Kim to obtain the invention as specified in the instant claim.
As per dependent claim 3, Kim wherein the cache directory lookup is configured to indicate whether data associated with the additional memory address is valid in memory for use as part of a processing-in-memory operation by a processing-in- memory component [(Paragraphs 0120-0127 and 0135; FIG. 8) wherein when the address requested by the memory request received from the outside corresponds to the PIM address information registered in the control register set 52, the operand corresponding to the PIM address information is valid, and the memory request corresponds to a read command or a write command, the PIM Request Identification Unit 54A of the Memory Controller 30 is configured to provide the PIM request identification signal obtained by identifying the PIM request to correspond to the claimed limitation].
Claim 11 is rejected under 35 U.S.C. 103(a) as being disclosed by Basu and Beard/Averill, as applied to claim 1, and further in view of Park et al. (US PGPUB 2023/0066662 hereinafter referred to as Park).
As per dependent claim 11, Basu/Beard discloses the system of claim 1.
Basu/Beard does not appear to explicitly disclose wherein the cache coherence controller is further configured to transmit the memory request for receipt by the memory subsequent to receipt of a cache response from the cache system.
However, Park discloses wherein the cache coherence controller is further configured to transmit the memory request for receipt by the memory subsequent to receipt of a cache response from the cache system [(Paragraph 0056) wherein to update the data storage 170 in response to the cache miss, the cache controller device 140 can cause a bus controller device 150 to send a request for data to the primary memory 120 via the bus architecture 120. The request can be sent at a second subsequent clock cycle n.sub.0+2. The request contains the desired instruction address to correspond to the claimed limitation].
Basu/Beard and Park are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Basu/Beard and Park before him or her, to modify the method of Basu/Beard to include the caching subsystem of Park because it will enhance caching system performance.
The motivation for doing so would be [“improve existing I-cache subsystem by multiplexing fetch control signaling and/or data sent to the hardware multi-thread microprocessor. As such, in situations where a program instruction for an execution thread is unavailable at the I-cache subsystem, embodiments of the disclosure avoid blocking another execution thread from obtaining a desired program instructions that is available at the I-cache subsystem” (Paragraph 0031 by Park)].
Therefore, it would have been obvious to combine Basu/Beard and Park to obtain the invention as specified in the instant claim.
Claim 12 is rejected under 35 U.S.C. 103(a) as being disclosed by Basu/Beard/Averill and Park, as applied to claim 1, and further in view of Yoon et al. (US PGPUB 2022/00075713 hereinafter referred to as Yoon).
As per dependent claim 12, Basu/Beard discloses the system of claim 1.
Basu/Beard does not appear to explicitly disclose wherein the memory request is configured to cause a processing-in-memory component of the memory to process data stored at the memory address in the memory.
However, Yoon discloses wherein the memory request is configured to cause a processing-in-memory component of the memory to process data stored at the memory address in the memory [(Paragraphs 0009, 0037-0045, 0049) wherein the processing-in-memory 100 may quickly access a memory 110 by quickly calculating a target physical address of the memory 110. Through this, the processing-in-memory 100 may quickly perform a PIM (processing in memory) operation stored in a predetermined address of the memory 110; the internal processor 120 may perform (or execute) the instruction by accessing the target physical address. The processing-in-memory 100 may perform the read or write instruction by accessing the memory 110 at the target physical address. The PIM operation may be performed according to the content stored at the target physical address on which the instruction is performed to correspond to the claimed limitation].
Basu/Beard and Yoon are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Basu/Beard and Park before him or her, to modify the method of Basu/Beard to include the PIM operation of Yoon because it will enhance caching system performance.
The motivation for doing so would be [“overhead may be reduced” (Paragraph 0061 by Yoon)].
Therefore, it would have been obvious to combine Basu/Beard and Yoon to obtain the invention as specified in the instant claim.
Claims 13 are rejected under 35 U.S.C. 103(a) as being disclosed by Basu and Beard/Averill, as applied to claim 1, and further in view of Dally et al. (US PGPUB 2011/0276762 hereinafter referred to as Dally).
As per dependent claim 13, Basu/Beard discloses the system of claim 1.
Basu/Beard does not appear to explicitly disclose wherein the cache coherence controller is configured to select the additional memory address based on spatial locality.
However, Dally discloses wherein the cache coherence controller is configured to select the additional memory address based on spatial locality [(Paragraph 0019) where the page mode accesses to DRAM require memory controller 110 to have the ability to group requests with adjacent memory addresses (i.e., requests exhibiting spatial locality) to correspond to the claimed limitation].
Basu/Beard and Dally are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Basu/Beard and Dally before him or her, to modify the method of Basu/Beard to include the PIM operations of Dally because it will enhance fail detection.
The motivation for doing so would be [“expanding the effective depth of the memory controller's write queuing resources through leveraging the storage capacity of a lower level cache memory” (Paragraph 0006 by Dally)].
Therefore, it would have been obvious to combine Basu/Beard and Dally to obtain the invention as specified in the instant claim.
a(2) CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 6-10 and 15-20, but would be allowable if claims are amended to overcome the prior art rejections and the 112 rejections above.
The reasons for allowance of claim 6 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the cache coherence controller is configured to transmit a cache request to the cache system based on the cache directory lookup indicating the data associated with the memory address specified by the memory request is not valid in the memory for use as part of a processing-in-memory operation by a processing-in-memory component”.
The reasons for allowance of claim 10 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “wherein the cache coherence controller is configured to transmit a cache request to the cache system based on the cache directory lookup indicating the data associated with the additional memory address specified by the memory request is not valid”.
The reasons for allowance of claim 15 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “the cache request configured to cause the cache system to transmit a cache response to the memory module, the cache response including data from the cache system for a memory address of the memory request and including data from an additional memory address selected by the cache coherence controller as part of the cache directory lookup”.
The reasons for allowance of claim 19 is that the prior art of record, neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “the additional memory address selected by the cache coherence controller based on the memory address specified in the processing-in-memory instruction; transmitting a cache request by the cache coherence controller for receipt by a cache system, the cache request configured to cause the cache system to transmit a cache response to cause the data at the memory address or the additional memory address in the memory to be valid; and transmitting the memory request by the cache coherence controller for receipt by a memory module that includes the memory”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohamed Gebril whose telephone number is (571)270-1857 and email address is mohamed.gebril @uspto.gov. The examiner can normally be reached on Monday-Friday, 8:00am-5:00pm.ALT. Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sanjiv Shah can be reached on 571-272-4098. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135