DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Note
The prior art rejection below cites particular paragraphs, columns, and/or line numbers in the references for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art.
Claims 1 – 20 are pending for examination.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1 - 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
As to claim 1, the claim recites
As to claim 1, An apparatus, comprising:
one or more memories to store instructions; and
one or more processors to execute the instructions to:
receive a first preference for performance or reduced power consumption for a plurality of sets of cores; and
select a core mask for the plurality of sets of cores based on the first preference, a workload type, and at least one of a core utilization or a foreground activity.
Step 2A:
Prong 1: the limitations of select a core mask for the plurality of sets of cores based on the first preference, a workload type, and at least one of a core utilization or a foreground activity recite mental processes since "calculating", "determining", and "identifying" are all functions that can be reasonably performed in the human mind including observations and with or without the use of pen and paper through observation, evaluation, judgement and opinion.
Prong 2: the additional element of receive a first preference for performance or reduced power consumption for a plurality of sets of cores merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
The additional element of An apparatus, one or more memories to store instructions; and one or more processors merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
Thus, these additional elements do not integrate the judicial exception into a practical application.
Step 2B:
the additional element of receive a first preference for performance or reduced power consumption for a plurality of sets of cores merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
The additional element of An apparatus, one or more memories to store instructions; and one or more processors merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
Accordingly, the additional elements do not amount to significantly more than the abstract idea.
As to claim 2. The apparatus of claim 1, wherein: the plurality of sets of cores are of different types; each different type has a different performance and power consumption; and the core mask indicates a number of active cores for each type of the different types.
The additional element merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 3. The apparatus of claim 1, wherein the first preference is selected from among a plurality of preferences which extend in a performance/power consumption spectrum.
The additional element recites mental processes since "calculating", "determining", and "identifying" are all functions that can be reasonably performed in the human mind including observations and with or without the use of pen and paper through observation, evaluation, judgement and opinion.
As to claim 4. The apparatus of claim 1, wherein the workload type is determined from among a plurality of workload types comprising bursty, sustained, battery life and idle.
The additional element recites mental processes since "calculating", "determining", and "identifying" are all functions that can be reasonably performed in the human mind including observations and with or without the use of pen and paper through observation, evaluation, judgement and opinion.
As to claim 5. The apparatus of claim 1, wherein the first preference is received from an original equipment manufacturer.
The additional element merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 6. The apparatus of claim 1, wherein:
the core mask is selected from a table of core masks The additional element recites mental processes since "calculating", "determining", and "identifying" are all functions that can be reasonably performed in the human mind including observations and with or without the use of pen and paper through observation, evaluation, judgement and opinion.
the core masks in the table are cross-referenced to different workload types and to different second preferences The additional element merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d);
one of the second preferences is selected based on the first preference and the at least one of the core utilization or the foreground activity The additional element merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d); and
the selected core mask is cross-referenced to the one of the second preferences and the workload type The additional element recites mental processes since "calculating", "determining", and "identifying" are all functions that can be reasonably performed in the human mind including observations and with or without the use of pen and paper through observation, evaluation, judgement and opinion.
As to claim 7. The apparatus of claim 6, wherein the second preferences extend in a performance/power consumption spectrum The additional element merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 8. The apparatus of claim 6, wherein the second preferences correspond to different core masks with different numbers of active cores, for at least one of the different workload types The additional element merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 9. The apparatus of claim 6, wherein:
the plurality of sets of cores are of different types;
each different type has a different performance The additional element merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d);
and when the workload type is bursty, the different second preferences correspond to different core masks with different numbers of active cores, for a highest performance core type of the different types The additional element recites mental processes since "calculating", "determining", and "identifying" are all functions that can be reasonably performed in the human mind including observations and with or without the use of pen and paper through observation, evaluation, judgement and opinion.
As to claim 10. An apparatus, comprising:
a plurality of sets of cores, wherein each set is of a different type, and each different type has a different performance and power consumption ;
a driver to indicate a preference for performance or reduced power consumption for the plurality of sets of cores, wherein the preference is based on an original equipment manufacturer setting and at least one of a core utilization or a foreground activity; and
firmware to provide core parking hints to an operating system scheduler in response to the preference.
Step 2A:
Prong 1: the limitations of a driver to indicate a preference for performance or reduced power consumption for the plurality of sets of cores, wherein the preference is based on an original equipment manufacturer setting and at least one of a core utilization or a foreground activity; and
firmware to provide core parking hints to an operating system scheduler in response to the preference are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
Prong 2:
The additional element of a plurality of sets of cores, wherein each set is of a different type, and each different type has a different performance and power consumption merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
The additional elements in An apparatus merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
Thus, these additional elements do not integrate the judicial exception into a practical application.
Step 2B:
The additional element of a plurality of sets of cores, wherein each set is of a different type, and each different type has a different performance and power consumption merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
The additional elements in An apparatus merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
Accordingly, the additional elements do not amount to significantly more than the abstract idea.
As to claim 11. The apparatus of claim 10, wherein the original equipment manufacturer setting is selected from among a plurality of settings which extend in a performance/power consumption spectrum.
The additional elements are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 12. The apparatus of claim 10, wherein the core parking hints comprise a selected core mask which is based on the preference and a workload type of the apparatus.
The additional elements are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 13. The apparatus of claim 12, wherein the firmware comprises a table of core masks and the selected core mask is selected from the table based on the preference and a workload type of the apparatus.
The additional elements merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 14. The apparatus of claim 13, wherein the workload type is determined from among a plurality of workload types comprising bursty, sustained, battery life and idle.
The additional elements are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 15. A non-transitory, computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors to:
obtain a first preference for high performance or low power consumption for a plurality of sets of cores, wherein the first preference is selected from among a plurality of preferences which extend in a performance/power consumption spectrum;
determine a second preference based on the first preference and at least one of a core utilization or a foreground activity; and
read a table to determine a core mask which is cross-referenced to the second preference and a workload type.
Step 2A:
Prong 1: the limitations of wherein the first preference is selected from among a plurality of preferences which extend in a performance/power consumption spectrum;
determine a second preference based on the first preference and at least one of a core utilization or a foreground activity; and
read a table to determine a core mask which is cross-referenced to the second preference and a workload type are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
Prong 2:
The additional element of obtain a first preference for high performance or low power consumption for a plurality of sets of cores merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
The additional elements in A non-transitory, computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
Thus, these additional elements do not integrate the judicial exception into a practical application.
Step 2B:
The additional element of obtain a first preference for high performance or low power consumption for a plurality of sets of cores merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
The additional elements in A non-transitory, computer-readable medium comprising instructions that, when executed by one or more processors, cause the one or more processors merely recite instructions to implement an abstract idea on a generic computer, or merely uses a generic computer or computer components as a tool to perform the abstract idea.
Accordingly, the additional elements do not amount to significantly more than the abstract idea.
As to claim 16. The non-transitory, computer-readable medium of claim 15, wherein the second preference is biased toward a relatively high performance when the at least one of a core utilization or a foreground activity is relatively high are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 17. The non-transitory, computer-readable medium of claim 15, wherein the core mask provides core parking hints to an operating system scheduler are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
As to claim 18. The non-transitory, computer-readable medium of claim 15, wherein the first preference is received from an original equipment manufacturer merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
As to claim 19. The non-transitory, computer-readable medium of claim 15, wherein the one or more processors comprise the plurality of sets of cores merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d), and the core mask indicates a number of active cores for each set of cores of the plurality of sets of cores the limitations are functions that can be reasonably carried out in the human mind with the aid of pen and paper, through observation, evaluation, judgment, opinion, thus it is reasonable to identify these limitation as reciting a mental process.
.
As to claim 20. The non-transitory, computer-readable medium of claim 19, wherein performance and power consumption are different for each set of cores of the plurality of sets of cores merely recite insignificant extra solution activity such as gathering, displaying, updating, transmitting and storing data which does not integrate the judicial exception into a practical application. See MPEP 2106.05(d).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 - 4 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al., (US PUB 2021/0064426 hereinafter Gupta) in view of SRINIVASAN et al., (US PUB 2019/0384348 hereinafter SRINIVASAN).
As to claim 1, Gupta teaches an apparatus, comprising:
one or more memories to store instructions; and one or more processors (“...within processor 110 such as uncore logic, and other components such as internal memories, e.g., one or more levels of a cache memory hierarchy and so forth...” para. 0045) to execute the instructions to:
receive a first preference for performance or reduced power consumption for a plurality of sets of cores (“..In an embodiment, these energy performance preference (EPP) values may be so-called EPP hints received by way of one or more configuration registers. In various embodiments such EPP information may be provided on a package, core or thread-level basis, to indicate preference of a user for a given value of a range of values between a highest performance level or highest energy savings. Note that there may be different EPP values associated with different cores/core types.” para. 0155) and (“...different cores are associated with a common EPP value...” para. 0157); and
select a core [mask] for the plurality of sets of cores based on the first preference, a workload type, and at least one of a core utilization or a foreground activity (“...With this information the OS scheduler may make better scheduling decisions, e.g., with regard to selection of appropriate core types for handling certain task...” para. 0164. Note: scheduling would comprise selecting) and (“...With a workload demand policy, operating points are selected based on energy efficiency and/or performance demands of the workload on each core type...” para. 0181) and (“...type of workload demand,...” para. 0032).
Gupta does not but SRINIVASAN teaches core mask (“...Additionally, control register 126 may store an affinity mask to indicate which processing cores 108 are active. In one embodiment, affinity mask 126 is a bit map, where each bit stores an activity status for a corresponding processing core....” para. 0023).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Gupta by applying the teaching of SRINIVASAN because SRINIVASAN would implement core mask to indicate processor core status to be active or inactive for use and save power (para. 0023 – 0024).
As to claim 2. Gupta modified by SRINIVASAN teaches The apparatus of claim 1, wherein: Gupta teaches the plurality of sets of cores are of different types; each different type has a different performance and power consumption (“...In an embodiment, resource allocation between hetero cores may be performed using a lookup table-based technique. In this arrangement a total core power budget may be translated to individual core budgets based on the power/performance differences between different core types. The differences for different core types can be encompassed in a lookup table that reflects variation in operating frequency based on a given power budget...” para. 0166); and
Gupta does not but SRINIVASAN teaches
the core mask indicates a number of active cores for each type of the different types (“Processor 500 includes a front end unit 530 coupled to an execution engine unit 550, and both are coupled to a memory unit 570. The processor 500 may include a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type...” para. 0051).
See motivation for claim 1 above.
As to claim 3. Gupta modified by SRINIVASAN teaches The apparatus of claim 1, Gupta teaches wherein the first preference is selected from among a plurality of preferences which extend in a performance/power consumption spectrum (“..In an embodiment, these energy performance preference (EPP) values may be so-called EPP hints received by way of one or more configuration registers. In various embodiments such EPP information may be provided on a package, core or thread-level basis, to indicate preference of a user for a given value of a range of values between a highest performance level or highest energy savings. Note that there may be different EPP values associated with different cores/core types.” para. 0155).
As to claim 4. Gupta modified by SRINIVASAN teaches The apparatus of claim 1, Gupta teaches wherein the workload type is determined from among a plurality of workload types comprising bursty, sustained, battery life and idle (“...Note that in other embodiments, target utilization values for different core types can be computed dynamically based on power performance bias or workload types...” para. 0173) and (“...With a workload demand policy, operating points are selected based on energy efficiency and/or performance demands of the workload on each core type...” para. 0181).
Claims 5 – 9 and 15 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta in view of SRINIVASAN, and further in view of Iyigun et al., (US PUB 2018/0120920 hereinafter Iyigun).
As to claim 5. Gupta modified by SRINIVASAN teaches The apparatus of claim 1, Gupta and SRINIVASAN do not but Iyigun teaches wherein the first preference is received from an original equipment manufacturer (“...the indications are pre-determined by another device or component, such as a manufacturer of the processor core 102, an original equipment manufacturer (OEM) of the computing device 100...” para. 0031).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Gupta and SRINIVASAN by applying the teaching of Iyigun because Iyigun would provide different second preference values beside most important value for the scheduler to determine on a processor core of the plurality of processor cores (para. 0102).
As to claim 6. Gupta modified by SRINIVASAN teaches The apparatus of claim 1, Gupta teaches wherein:
the core [mask] is selected from a table of core [masks] (“Since this table is accessed with multiple different operating points for different cores or core types,....” para. 0180) and (“...lookup table with at least a portion of the first operating point determined for at least one of the first core and the second operating point determined for the second core to determine the efficiency value for the first core and the efficiency value for the second core...” para. 0201); the core [masks] in the table are cross-referenced to different workload types (“...target utilization values for different core types can be computed dynamically based on power performance bias or workload type...” para. 0173) and to different second preferences (“..In an embodiment, these energy performance preference (EPP) values may be so-called EPP hints received by way of one or more configuration registers...” para. 0155. Note: EPP values would include second value).
Gupta does not but SRINIVASAN core masks (“...Additionally, control register 126 may store an affinity mask to indicate which processing cores 108 are active. In one embodiment, affinity mask 126 is a bit map, where each bit stores an activity status for a corresponding processing core....” para. 0023).
See motivation for claim 1 above.
Gupta and SRINIVASAN do not but Iyigun teaches
one of the second preferences is selected based on the first preference and the at least one of the core utilization or the foreground activity; and the selected core mask is cross-referenced to the one of the second preferences and the workload type (“...one or more processor cores; a thread importance determination module configured to determine an importance level of a first thread scheduled to run on a processor core of the one or more processor cores, the importance level being one of multiple different importance levels; and a core frequency configuration module configured to determine a frequency range associated with the importance level that is one of multiple different frequency ranges or an energy performance preference value associated with the importance level that is one of multiple energy performance preference value” para. 0102).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Gupta and SRINIVASAN by applying the teaching of Iyigun because Iyigun would provide different second preference values beside most important value for the scheduler to determine on a processor core of the plurality of processor cores (para. 0102).
As to claim 7. Gupta modified by SRINIVASAN and Ivigun teaches The apparatus of claim 6, Gupta teaches wherein the second preferences extend in a performance/power consumption spectrum (“... In various embodiments such EPP information may be provided on a package, core or thread-level basis, to indicate preference of a user for a given value of a range of values between a highest performance level or highest energy saving...” para. 0155).
As to claim 8. Gupta modified by SRINIVASAN and Iygun teaches The apparatus of claim 6, Gupta teaches wherein the second preferences correspond to different core [masks with different numbers of active cores], for at least one of the different workload types (“...In various embodiments such EPP information may be provided on a package, core or thread-level basis, to indicate preference of a user for a given value of a range of values between a highest performance level or highest energy savings. Note that there may be different EPP values associated with different cores/core types...” para. 0155) and (“...With a workload demand policy, operating points are selected based on energy efficiency and/or performance demands of the workload on each core type...” para. 0181) and (“...type of workload demand,...” para. 0032).
Gupta does not but SRINIVASAN teaches core mask (“...Additionally, control register 126 may store an affinity mask to indicate which processing cores 108 are active. In one embodiment, affinity mask 126 is a bit map, where each bit stores an activity status for a corresponding processing core....” para. 0023).
See motivation for claim 1 above.
As to claim 9. Gupta modified by SRINIVASAN and Iyigun teaches The apparatus of claim 6, Gupta teaches wherein:
the plurality of sets of cores are of different types; each different type has a different performance (“Each processor core in a computing device supports various different frequency ranges, also referred to as p-states, and can operate to run threads at any one of those different frequency ranges. Threads in the computing device are assigned one of multiple importance levels. A processor core is configured to run at a particular frequency range or in accordance with a particular energy performance preference based on the importance level of the thread it is running....” abstract); and
when the workload type is bursty, the different second preferences preference correspond to different core [masks] with different numbers of active cores, for a highest performance core type of the different types (Optimal design/operating point of a heterogeneous processor (in terms of VF characteristics, instructions per cycle (IPC), functionality/ISA, etc.) is dependent on both inherent/static system constraints (e.g., common voltage rail) and a dynamic execution state (e.g., type of workload demand, power/thermal state, etc.)...” para. 0032) and (“In addition, embodiments may determine an optimal operating point for the heterogeneous processor. Such optimal operating point may be determined based at least in part on a present execution scenario, including varying workload demands (performance, efficiency, responsiveness, throughput, IO response) of different applications, and shifting performance and energy efficiency capabilities of heterogeneous cores” para. 0034) and
Gupta does not but SRINIVASAN core masks (“...Additionally, control register 126 may store an affinity mask to indicate which processing cores 108 are active. In one embodiment, affinity mask 126 is a bit map, where each bit stores an activity status for a corresponding processing core....” para. 0023).
See motivation for claim 1 above.
As to claim 15. Gupta teaches a non-transitory, computer-readable medium comprising instructions (“...a computer readable medium including instructions...” para. 0202) that, when executed by one or more processors (“...within processor 110 such as uncore logic, and other components such as internal memories, e.g., one or more levels of a cache memory hierarchy and so forth...” para. 0045), cause the one or more processors to:
obtain a first preference for high performance or low power consumption for a plurality of sets of cores (“...receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget;...” abstract and para. 0035), wherein the first preference is selected from among a plurality of preferences which extend in a performance/power consumption spectrum (“..In an embodiment, these energy performance preference (EPP) values may be so-called EPP hints received by way of one or more configuration registers. In various embodiments such EPP information may be provided on a package, core or thread-level basis, to indicate preference of a user for a given value of a range of values between a highest performance level or highest energy savings. Note that there may be different EPP values associated with different cores/core types.” para. 0155);
[determine a second preference based on the first preference and at least one of a core utilization or a foreground activity]; and
read a table to determine a core (“Since this table is accessed with multiple different operating points for different cores or core types,....” para. 0180) and (“...lookup table with at least a portion of the first operating point determined for at least one of the first core and the second operating point determined for the second core to determine the efficiency value for the first core and the efficiency value for the second core...” para. 0201) [mask] which is cross-referenced to the second preference and a workload type (“...target utilization values for different core types can be computed dynamically based on power performance bias or workload type...” para. 0173).
Gupta does not but SRINIVASAN masks (“...Additionally, control register 126 may store an affinity mask to indicate which processing cores 108 are active. In one embodiment, affinity mask 126 is a bit map, where each bit stores an activity status for a corresponding processing core....” para. 0023).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Gupta by applying the teaching of SRINIVASAN because SRINIVASAN would implement core mask to indicate processor core status to be active or inactive for use and save power (para. 0023 – 0024).
Gupta and SRINIVASAN do not but Iyigun teaches
determine a second preference based on the first preference and at least one of a core utilization or a foreground activity (“...performance preference values that are associated with different important level...” para. 0102. Note: different preference values associated with different important level are different second preferences).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Gupta and SRINIVASAN by applying the teaching of Ivigun because Ivigun would provide different second preference values beside most important value for the scheduler to determine on a processor core of the plurality of processor cores (para. 0102).
.
As to claim 16. Gupta modified by SRINIVASAN and Iyigun teaches The non-transitory, computer-readable medium of claim 15, Gupta and SRINIVASAN do not but Iyigun teaches wherein the second preference is biased toward a relatively high performance when the at least one of a core utilization or a foreground activity is relatively high (“Threads in a computing device are assigned one of multiple importance levels. There can be two importance levels (e.g., important and unimportant), or alternatively any number of importance levels. The importance level of a thread can be determined on various different factors, such as whether the thread belongs to the foreground process or its descendants, whether the thread owns a foreground or visible window, whether the thread is involved in audio playback, whether a thread is working on behalf of another high importance or high quality of service thread, and so forth. In one or more embodiments, a processor core is configured to run at a particular frequency range based on the importance level of the thread it is running...” para. 0104. Note: second preferences of is biased toward relatively high performance and when core associated thread that is at important level in the foreground, run faster).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Gupta and SRINIVASAN by applying the teaching of Ivigun because Ivigun would provide different second preference values beside most important value for the scheduler to determine on a processor core of the plurality of processor cores (para. 0102).
As to claim 17. Gupta modified by SRINIVASAN and Iyigun teaches The non-transitory, computer-readable medium of claim 15, Gupta teaches wherein the [core mask provides core parking hints to] an operating system scheduler (“...With this information the OS scheduler may make better scheduling decisions, e.g., with regard to selection of appropriate core types for handling certain task...” para. 0164. Note: scheduling would comprise selecting) and (“...With a workload demand policy, operating points are selected based on energy efficiency and/or performance demands of the workload on each core type...” para. 0181) and (“...type of workload demand ...” para. 0032).
Gupta and Iyigun do not but SRINIVASAN teaches core mask provides core parking hints (“...When the bit is set to an inactive status (e.g., “0”), the corresponding processing core is not available to software applications or is idle. In one embodiment, power management circuit 110 may determine which processor cores 108 are active, and to set bits in the affinity mask corresponding to active processing cores to the active status and bits corresponding to inactive processing cores to the inactive status...” para. 0023. Note: parking hint is inactive status).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Gupta and Iyigun by applying the teaching of SRINIVASAN because SRINIVASAN would implement core mask to indicate processor core status to be active or inactive for use and save power (para. 0023 – 0024).
As to claim 18. Gupta modified by SRINIVASAN and Iyigun teaches The non-transitory, computer-readable medium of claim 15, Gupta teaches wherein the first preference (“...receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget;...” abstract and para. 0035);
Gupta and SRINIVASAN do not but Iyigun teaches is received from an original equipment manufacturer (“...the indications are pre-determined by another device or component, such as a manufacturer of the processor core 102, an original equipment manufacturer (OEM) of the computing device 100...” para. 0031).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Gupta and SRINIVASAN by applying the teaching of Ivigun because Ivigun would provide different second preference values beside most important value for the scheduler to determine on a processor core of the plurality of processor cores (para. 0102).
As to claim 19. Gupta modified by SRINIVASAN and Iyigun teaches The non-transitory, computer-readable medium of claim 15, Gupta teaches wherein the one or more processors comprise the plurality of sets of cores “..In an embodiment, these energy performance preference (EPP) values may be so-called EPP hints received by way of one or more configuration registers. In various embodiments such EPP information may be provided on a package, core or thread-level basis, to indicate preference of a user for a given value of a range of values between a highest performance level or highest energy savings. Note that there may be different EPP values associated with different cores/core types.” para. 0155); and
Gupta and Iyigun do not but SRINIVASAN teaches and the core mask indicates a number of active cores for each set of cores of the plurality of sets of cores (“....In one embodiment, affinity mask 126 is a bit map, where each bit stores an activity status for a corresponding processing core. For example, when a bit is set to an active status (e.g., “1”)...” para. 0023).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Gupta and Iyigun by applying the teaching of SRINIVASAN because SRINIVASAN would implement core mask to indicate processor core status to be active or inactive for use and save power (para. 0023 – 0024).
As to claim 20. Gupta modified by SRINIVASAN and Iyigun teaches The non-transitory, computer-readable medium of claim 19, Gupta teaches wherein performance and power consumption are different for each set of cores of the plurality of sets of cores (“.this table may include a plurality of entries each including a voltage for different core types for a corresponding operating point (e.g. frequency). As such, a frequency of the operating point can be used to index in the table to obtain a voltage for each of the different core types....” para. 0178 – 0179) and (“...first core and the at least one second core; and cause a clock generation circuit coupled to the at least one second core to provide a clock signal at a third operating frequency to the at least one second core, the third operating frequency different than the second operating frequency...” para. 0205).
Claims 10 – 11 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al., (US PUB 2021/0064426 hereinafter Gupta) in view of Ivigun et al., (US PUB 2018/0120920 hereinafter Ivigun).
As to claim 10. Gupta teaches an apparatus, comprising:
a plurality of sets of cores, wherein each set is of a different type, and each different type has a different performance and power consumption (“..With varying power/thermal state of a system, the relative power/performance characteristics of different cores change. Embodiments take these differences into account to make both local and globally optimal decisions. As a result, embodiments provide dynamic feedback of per core power/performance characteristics” para. 0032) and (“...processor performance and energy efficiency capabilities....” para. 0033);
an operating system scheduler in response to the preference (“...the dynamically computed processor performance and energy efficiency capabilities may be provided to an OS scheduler...” para. 0035) and (“....dynamically determine hardware feedback information regarding performance and energy efficiency capabilities of hardware circuits such as cores 120 and provide an interface to enable communication of this information to an OS scheduler, for use in making better scheduling decisions...” para. 0043)
Gupta does not but Iyigun teaches
a driver to indicate a preference for performance or reduced power consumption for the plurality of sets of cores (“Each processor core in a computing device supports various different frequency ranges, also referred to as p-states, and can operate to run threads at any one of those different frequency ranges. Threads in the computing device are assigned one of multiple importance levels. A processor core is configured to run at a particular frequency range or in accordance with a particular energy performance preference...” abstract) and (“..., each group of processor cores is configured with a particular energy performance preference (EPP) value. The energy performance preference value indicates to the processor core to run in accordance with a particular energy performance preference preferring higher performance or lower energy usage when executing a thread. A processor core is configured to run in accordance with an energy performance preference based on the importance level of the thread it is running. For example, a processor core can be configured to run in accordance with an energy performance preference that indicates to prefer higher performance (and higher energy usage) to execute threads having an importance level of important...” para. 0016), wherein the preference is based on an original equipment manufacturer setting and at least one of a core utilization or a foreground activity (“..the indications are pre-determined by another device or component, such as a manufacturer of the processor core 102, an original equipment manufacturer (OEM) of the computing device 100, and so forth.” para. 0031); and
firmware to provide core parking hints to (“The core parking module 136 determines whether to park a processor core 102 based on a utilization factor of the processor core...” para. 0059) [an operating system scheduler in response to the preference].
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Gupta by applying the teaching of Ivigun because Ivigun would provide different preference values beside most important value for the scheduler to determine on a processor core of the plurality of processor cores (para. 0102).
As to claim 11. Gupta modified by Iyigun teaches the apparatus of claim 10, Gupta does not but Iyigun teaches wherein the original equipment manufacturer setting is selected from among a plurality of settings which extend in a performance/power consumption spectrum (“...performance preference values that are associated with different important level...” para. 0102. Note: different preference values associated with different important level are different second preference).
See motivation for claim 10 above.
Claim 12 - 14 are rejected under 35 U.S.C. 103 as being unpatentable over Gupta in view of Ivigun, as applied to claim 10, and further in view of SRINIVASAN et al., (US PUB 2019/0384348 hereinafter SRINIVASAN).
As to claim 12. Gupta modified by Iyigun teaches The apparatus of claim 10,
Gupta teaches [wherein the core parking hints] comprises a selected core [mask] which is based on the preference and a workload type of the apparatus (“...With this information the OS scheduler may make better scheduling decisions, e.g., with regard to selection of appropriate core types for handling certain task...” para. 0164. Note: scheduling would comprise selecting) and (“...With a workload demand policy, operating points are selected based on energy efficiency and/or performance demands of the workload on each core type...” para. 0181) and (“...type of workload demand,...” para. 0032).
Gupta does not but Ivigun teaches wherein the core parking hints (“The core parking module 136 determines whether to park a processor core 102 based on a utilization factor of the processor core...” para. 0059)]
See motivation for claim 10 above.
Gupta and Ivigun do not but SRINIVASAN teaches core mask (“...Additionally, control register 126 may store an affinity mask to indicate which processing cores 108 are active. In one embodiment, affinity mask 126 is a bit map, where each bit stores an activity status for a corresponding processing core....” para. 0023).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Gupta and Ivigun by applying the teaching of SRINIVASAN because SRINIVASAN would implement core mask to indicate processor core status to be active or inactive for use and save power (para. 0023 – 0024).
As to claim 13. Gupta modified by Iyigun and SRINIVASAN teaches The apparatus of claim 12, Gupta teaches wherein the firmware comprises a table of core [masks] and the selected core [mask] is selected from the table based on the preference and a workload type of the apparatus (“...With this information the OS scheduler may make better scheduling decisions, e.g., with regard to selection of appropriate core types for handling certain task...” para. 0164. Note: scheduling would comprise selecting) and (“...With a workload demand policy, operating points are selected based on energy efficiency and/or performance demands of the workload on each core type...” para. 0181) and (“...type of workload demand,...” para. 0032).
Gupta and Ivigun do not but SRINIVASAN teaches core mask (“...Additionally, control register 126 may store an affinity mask to indicate which processing cores 108 are active. In one embodiment, affinity mask 126 is a bit map, where each bit stores an activity status for a corresponding processing core....” para. 0023).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention was made to modify Gupta and Ivigun by applying the teaching of SRINIVASAN because SRINIVASAN would implement core mask to indicate processor core status to be active or inactive for use and save power (para. 0023 – 0024).
As to claim 14. Gupta modified by Iyigun and SRINIVASAN teaches The apparatus of claim 13, Gupta teaches wherein the workload type is determined from among a plurality of workload types comprising bursty, sustained, battery life and idle (“...Note that in other embodiments, target utilization values for different core types can be computed dynamically based on power performance bias or workload types...” para. 0173) and (“...With a workload demand policy, operating points are selected based on energy efficiency and/or performance demands of the workload on each core type...” para. 0181).
Conclusion
The prior art made of record but not relied upon request is considered to be pertinent to applicant’s disclosure.
Liu, (US PUB 2021/0397476), discloses a power-performance based system management, wherein table of cores associated with workloads (title, abstract and figures 1 – 7).
Naffziger, (US PUB 2012/0146708), discloses a method of boosting core performance by retaining a higher power allocation until active neighbor cores heat up (title, abstract and figures 1 – 5).
Sistla, (US PUB 2012/0144217), discloses a power management that switch power from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level (title, abstract and figures 1 – 9).
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/PHUONG N HOANG/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194
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