DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The abstract of the disclosure is objected to because of the following informalities:
Line 5: Change “the operands” to “the one or more operands” for clarity.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
[0005-0006]: The paragraphs refer to Figs. 3-4 as referring to the UWRMSR instruction. However, Figs. 3-4 are referring to the URDMSR instruction. Applicant is advised to fix this discrepancy.
[0053], second-to-last line: A comma is missing between “used” and “the” and should be inserted.
[0054]: The paragraph seems to discuss of the URDMSR instruction with respect to Fig. 2. However, Fig. 2 refers to the UWRMSR instruction. Applicant is advised to fix this discrepancy.
[0060], line 6: "not" appears to conflict with the earlier "allowed". Applicant is advised to change the wording of the line or verify the use of the language.
[0060], second-to-last line and last line: The phrase “when an immediate value is used they access control aspects…” is unclear and should be fixed.
[0060], last line: Insert a closing parenthesis after “involved”.
[0061], line 4: "of source operand" should be "of a source operand".
[0063]: The paragraph should be located before paragraph [0061]; see, for example analogous paragraphs [0054]-[0056].
[0086], line 2: Insert “of” before “the single instruction”.
[0093], line 2: Insert “of” before “the single instruction”.
[00114], line 2: Insert “of” before “the single instruction”.
[00139], lien 6: Insert “computing” after “(throughput)”.
[00222], lines 18-19: “a register maps” is grammatically incorrect.
Appropriate correction is required.
A substitute specification excluding the claims is required pursuant to 37 CFR 1.125(a) because the amendments filed on 09/22/2026 makes an indication to replace paragraph [00534], which does not exist, with changes to a paragraph that Examiner raised objections on, creating confusion. Furthermore, Applicant does not address the objection on the rearrangement of paragraph [0063] to be placed before paragraph [0061], but instead merely addresses the issues raised in the paragraph. Due to a large number of amendments, the need for reordering paragraphs, and the clarification of what paragraphs should be replaced, a substitute specification is requested.
A substitute specification must not contain new matter. The substitute specification must be submitted with markings showing all the changes relative to the immediate prior version of the specification of record. The text of any added subject matter must be shown by underlining the added text. The text of any deleted matter must be shown by strike-through except that double brackets placed before and after the deleted characters may be used to show deletion of five or fewer consecutive characters. The text of any deleted subject matter must be shown by being placed within double brackets if strike-through cannot be easily perceived. An accompanying clean version (without markings) and a statement that the substitute specification contains no new matter must also be supplied. Numbering the paragraphs of the specification of record is not considered a change that must be shown.
Drawings
The lengthy set of drawings has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the drawings.
The original drawings (03/30/2023) and the amended drawings (09/21/2026) are objected as failing to comply with 37 CFR 1.83(t) because the numbers representing the numbering of sheets of drawings must be placed in the middle of the top of the sheet, not in the margin.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claim 1: In line 6, insert “one or more” before “operands” to address antecedent basis issues.
Claims 9 and 17 are objected to for the same reasons as claim 1.
Claim 5: In line 3, a hyphen is missing between “3” and “byte” and should be inserted.
Claims 13 and 18 are objected to for the same reasons as claim 5.
Claim 6: In line 1, “the bits” is grammatically incorrect. Applicant is advised to delete the article “the”.
Claims 14 and 19 are objected to for the same reasons as claim 6.
Claim 7: In line 1, insert “circuitry” after “decoder” to improve clarity.
Claim 20 is objected to for the same reasons as claim 7.
Claim 9: In line 2, either delete “is” after “instruction”, or insert “wherein” after the comma.
Claim 17 is objected to for the same reasons as claim 9.
Claim 15: In line 1, change “the decoder” to “a decoder” to address antecedent basis issues.
Claims 2-8, 10-16, and 18-20 are objected for inheriting the objection of the claims in which they depend on.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4 and 12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "one or more operands is memory" in line 1. It’s unclear how “one or more operands” can be “memory”. For the sake of examination, Examiner will interpret this limitation to be “one or more operands is a memory location”.
Claim 12 is rejected for the same reasons as claim 4.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Claim 1, 9, and 17 are directed towards an apparatus claim, a method claim, and a system claim, respectively. Therefore, claims 1, 9, and 17 are directed to a process, machine, manufacture or composition of matter.
Under Prong One of Step 2A of the 2019 Revised Patent Subject Matter Eligibility Guidance (“2019 PEG”), claim 1 recites “the prefix is to indicate support for use of the immediate value” and “execute… using the immediate value”. Such limitations cover mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). Accordingly, the claim recites an abstract idea.
Under Prong Two of Step 2A, this judicial exception is not integrated into a practical application. The element “decoder circuitry to decode an instance of a single instruction, the instance of the single instruction is to include one or more fields for an opcode, one or more fields for one or more operands, one or more fields for a prefix, and a field for an immediate value, wherein the opcode is to indicate one or more operations to be performed by execution circuitry using the operands” is recited at a high level of generality, i.e., generic computer elements performing generic computer operations. Such element amounts to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)). Thus, the element fails to integrate the judicial exception into a practical application.
Under Step 2B, the claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed previously, with respect to Step 2A Prong Two, the additional element in the claim amounts to no more than mere instructions to apply the exception (see MPEP 2106.05(f)). Accordingly, this claim is not patent-eligible under 35 U.S.C. 101.
Claim 2 recites “one of the one or more operands is a general purpose register” Such element amounts to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)). The claim fails to provide an element to integrates the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 3 recites “one of the one or more operands is a vector register”. Such element amounts to no more than mere instructions to apply the exception using computer elements recited at a high level of generality (MPEP 2106.05(f)). The claim fails to provide an element to integrates the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 4 recites “one of the one or more operands is memory”. Such element amounts to no more than mere instructions to apply the exception using generic computer elements (MPEP 2106.05(f)). The claim fails to provide an element to integrates the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 5 recites “the prefix is a 3 byte prefix”. Such element further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element to integrates the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 6 recites “the bits 0-4 of a second byte of the prefix are to indicate usage of the immediate value”. Such element further covers mental processes that are concepts performed in the human mind or with pen and paper (including an observation, evaluation, judgement, or opinion). The claim fails to provide an element to integrates the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 7 recites “the decoder is to treat 32 bits following addressing information in a format of the instance of the single instruction as the immediate value”. Such element amounts to no more than mere instructions to apply the exception using generic computer elements, i.e., generic computer element performing generic functions/steps (MPEP 2106.05(f)). The claim fails to provide an element to integrates the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Claim 8 recites “the immediate value is a 32-bit value”. Such element amounts to no more than mere instructions to apply the exception using generic computer elements, i.e., generic computer element performing generic functions/steps (MPEP 2106.05(f)). The claim fails to provide an element to integrates the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Regarding claims 9-16, the claims recite a method similar to the apparatus of claims 1-8, respectively. Therefore, claims 9-16 are rejected on the same premises.
Regarding claim 17, the claim is mostly rejected for the same reasons as claim 1. The claim also recites “memory to store an instance of a single instruction”. Such element is considered to be an insignificant extra-solution activity of storing data in memory (See MPEP 2106.05(d)(II)(iv), storing and retrieving information in memory), and is deemed to be considered well-understood, routine, and conventional by the courts (MPEP 2106.05(d); See Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93). The claim fails to provide an element to integrates the judicial exception into a practical application under Step 2A Prong Two and does not amount to anything significantly more under Step 2B. Accordingly, the claim is not patent-eligible under 35 U.S.C. 101.
Regarding claims 18-20, the claims recite a system similar to the apparatus of claims 5-7, respectively. Therefore, claims 5-7 are rejected on the same premises.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5, 7-10, 12-13, 15-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shah et al. (US 20210073129 A1).
Felix Cloutier “MOV – Move” is cited as extrinsic evidence to explain the x86 MOV instruction.
OSDev Wiki “Real Mode” is cited as extrinsic evidence to explain that all x86 processors support Real Mode.
Stack Overflow “Is it possible to use 32 bits registers/instructions in real mode?” (hereinafter S1) is cited as extrinsic evidence to explain how 32-bit instructions can be executed in Real Mode.
Regarding claim 1, Shah teaches an apparatus (Fig. 10B: Core 1090) comprising:
decoder circuitry (Fig. 10B: Decoder circuitry 1040) to decode an instance of a single instruction ([00106]: Core 1090 may execute the x86 instruction set, which would include the MOV instruction (see Felix Cloutier, page 2, the website provides details of the MOV instruction using terms from the x86 architecture). The MOV instruction with the “C7 /0 id” opcode as the instance of the single instruction), the instance of the single instruction is to include one or more fields for an opcode (Fig. 7: The instruction format that’s executable by the core 1090 includes opcode field 704), one or more fields for one or more operands (Fig. 7 and [0082]: Addressing field 705 may specify a source/destination register operand), one or more fields for a prefix (Fig. 7 and [0079]: Prefixes 701 is included as part of the instruction), and a field for an immediate value (Fig. 7 and [0078]: Immediate field 709), wherein the opcode is to indicate one or more operations to be performed by execution circuitry using the operands (Figs. 7 and 10B, [0080, 00103]: Opcode, such as the one defined for the MOV instruction, specifies a data movement operation to be performed by the execution engine 1050 (see Felix Cloutier, under “Description”, first paragraph). Execution engine as the execution circuitry) and the prefix is to indicate support for use of the immediate value during execution of the instance of the single instruction ([0079]: When the processor is in Real Mode, in which every x86 processor supports Real Mode (see OSDev Wiki, First Paragraph, all x86 processors begin execution in Real Mode, therefore all x86 processors support Real Mode), the processor can only execute 16-bit instructions (see S1, ninjalj’s answer, first paragraph). When using the 0x66 prefix byte alongside the instructions (such as the MOV instruction), the processor in Real Mode will be able to execute 32-bit instructions, which uses 32-bit operands such as 32-bit registers and 32-bit immediate values (see S1, ninjalj’s answer, instructions are switched to 32-bit from 16-bit in real mode when using the 0x66 prefix). Therefore, the 0x66 prefix indicates support of a 32-bit immediate value during the execution of the MOV instruction); and
the execution circuitry to execute the decoded instance of the single instruction according to the opcode using the immediate value (Fig. 10B and [00103]: Execution engine 1050 does the processing of an instruction, which include scheduling and executing instructions).
Regarding claim 2, Shah teaches the apparatus of claim 1, wherein one of the one or more operands is a general purpose register (The MOV instruction requires the use of a register (such as a 16-bit general register when in Real Mode) to designate a location in memory to store data in (see Felix Cloutier, second-to-last entry of the first table), the register used as the general purpose register).
Regarding claim 4, Shah teaches the apparatus of claim 1, wherein one of the one or more operands is memory (See 112(b) interpretation. The MOV instruction requires the use of a register (such as a 16-bit general register when in Real Mode) to designate a location in memory to store data in (see Felix Cloutier, second-to-last entry of the first table and table under “Instruction Operand Encoding”)).
Regarding claim 5, Shah teaches the apparatus of claim 1, wherein the prefix is a 3 byte prefix ([0079]: The prefix field may comprise multiple prefix bytes, such as a section override byte (e.g., 0x2E) to specify a segment register for memory access and address-size override byte (i.e., 0x67) to enable 32-bit addressing when in Real Mode (see S1, under ninjalj’s answer, second paragraph), which can be applied to the MOV instruction alongside the 0x66 prefix byte. This creates a 3-byte prefix for the MOV instruction).
Regarding claim 7, Shah teaches the apparatus of claim 1, wherein the decoder is to treat 32 bits following addressing information in a format of the instance of the single instruction as the immediate value (Fig. 7: In the instruction format seen in fig. 7, when no displacement is defined, the immediate value follows after the addressing information field 705, in which the 32-bits identified in the immediate field as the immediate value (when the prefix is 0x66 and the processor is operating in Real Mode)).
Regarding claim 8, Shah teaches the apparatus of claim 1, wherein the immediate value is a 32-bit value (See claim 1 rejection. The specific MOV instruction uses a 32-bit immediate value (see Felix Cloutier, second-to-last entry of the first table)).
Regarding claims 9-10, 12-13 and 15-16, the claims recite a method similar to the apparatus of claims 1-2, 4-5, and 7-8, respectively. Therefore, the claims are rejected on the same premises.
Regarding claim 17, the claim is mostly rejected for the same reasons as claim 1. Shah also teaches a system (Figs. 5, 10B, and 12, [0059]: System 500 comprises of processor 510, which may be processor 1200 comprising of processor cores 1202(A-N), wherein one of the processor cores may be processor core 1090) comprising: memory to store an instance of a single instruction (Fig. 5 and [0067]: System 500 includes memory 530, which stores and provide instructions to processor 510).
Regarding claims 18 and 20, the claims recite a systems claim similar to the apparatus of claims 5 and 7, respectively. Therefore, the claims are rejected on the same premises.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Shah et al. (US 20210073129 A1) in view of Stack Overflow (order for encoding x86 instruction prefix bytes) (hereinafter S2).
Regarding claim 6, Shah teaches the apparatus of claim 5, wherein the bits 0-4 of byte of the prefix are to indicate usage of the immediate value (Bits 0-4 of the 0x66 prefix byte helps indicate the usage of the 32-bit immediate value).
Shah does not teach that 0x66 byte is a second byte of the prefix.
S2 teaches that prefix bytes are not set in a defined order for x86 instructions (Under pankaj’s question and under Nathan Fellman’s answer: In response to the question asked, unless for very specific prefixes or for specific cases, ordering of the prefix bytes do not matter for x86 instructions).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Shah with the teachings of S2 to have the 0x66 prefix byte be the second prefix byte of the instruction prefix. One of ordinary skill may set the 0x66 byte to be the second byte of the prefix for the purposes of readability or to have a set standard for the instruction to build upon for future modifications of the instruction. Additionally, rearrangement of parts, i.e., moving the 0x66 byte to the second byte position of the prefix, is deemed a routine expedient, not a patentable distinction (see MPEP 21044.04(VI)(C)).
Regarding claim 14, the claim recites a method similar to the apparatus of claim 6. Therefore, the claim is rejected on the same premises.
Regarding claim 19, the claim recites a system similar to the apparatus of claim 6. Therefore, the claim is rejected on the same premises.
Allowable Subject Matter
Claims 3 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable, over the prior art, if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 3 and 11, the prior art of record has not taught, either individually or in combination, and together with all other claimed features, that the one or more operands is a vector register.
Response to Arguments
Applicant's arguments filed September 21, 2026, with respect to claims 1-20 under 35 U.S.C. 101 have been fully considered but they are not persuasive.
Regarding arguments on page 15, paragraph 2, Applicant argues that a human mind is unequipped to perform hardware-level instruction decoding, parse machine-code prefix bytes, and execute the resulting decoded instruction in processor execution circuitry.
See MPEP 2106 regarding patent subject matter eligibility. Each of the independent claims recite mental limitations with respect to having a prefix of an instruction to indicate support for use of an immediate value(as stated in the 101 rejection analysis). The Applicant uses computer components, such as execution circuitry of a processor, as tools to perform the abstract idea, which doesn't integrate the judicial exception into a practical application or provide an inventive concept (see 2106.05(f)(2), paragraphs 1-2, also see MPEP 2106.04(a)(2)(III)(C)). Therefore, Applicant's remarks regarding that the human mind is unequipped to perform hardware-level instruction decoding, parse machine-code prefix bytes, and execute the resulting decoded instruction in processor execution circuitry are considered not persuasive.
Regarding arguments on page 15, paragraph 3, Applicant argues that the Examiner analyzed the claims at an impermissibly high level of generality.
Examiner respectfully disagrees with this argument. See MPEP 2106 regarding subject matter eligibility. Examiner has explained in the 101 analysis how each of the limitations, both alone and in combination, do not amount to anything significant more and do not integrate the judicial exception into a practical application. At a high level, the Applicant is using a computer as a tool to perform the judicial exception, which does not integrate the judicial exception into a practical application (See MPEP 2106.05(f)(2), also see MPEP 2106.04(a)(2)(III)(C)). See 101 analysis for a complete explanation. Furthermore, Applicant does not explain how Examiner read the claims at an impermissibly high level of generality. Therefore, Applicant's remarks regarding that the Examiner analyzed the claims at an impermissibly high level of generality are considered not persuasive.
Regarding arguments on page 15, paragraph 4 to page 16, paragraph 2, Applicant argues that the claims are directed to an improvement.
Examiner respectfully disagrees. For reference, MPEP 2106.05(a) states that "it is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements" and "it is important to keep in mind that an improvement in the abstract idea itself (e.g. a recited fundamental economic concept) is not an improvement in technology". The "improvement" mentioned is not provided by any additional elements, both alone and in combination, as such additional elements analyzed under Step 2A Prong Two and Step 2B amount to no more than mere instructions to apply the exception using generic computer elements or elements recited at a high level (MPEP 2106.05(f)). Furthermore, Applicant does not provide any distinctive details between the circuitry claimed and generic circuitry. Therefore, the claimed circuitry is recited at a high level and/or generic. As it stands, only the abstract idea provides the "improvement" of the invention as a whole. Furthermore, the steps that Applicant points to as being recited in the claim is part of the abstract idea itself, not from the elements of the independent claims. Therefore, Applicant's remarks regarding that the claimed invention indicates an improvement to the function of a computer are considered not persuasive.
The rejections of claims 1-20 under 35 U.S.C. 101 will be maintained.
Applicant's arguments filed September 21, 2026, with respect to claims 1-2, 4-5, 7-10, 12-13, 15-18, and 20 rejected under 35 U.S.C. 102(a)(1) and claims 1-2, 7-10, and 15-17 alternatively rejected under 35 U.S.C. 102(a)(1) have been fully considered but they are mostly not persuasive.
Regarding arguments on page 17, paragraph 2, Applicant argues that Shah fails to disclose a prefix indicating support for use of an immediate because the use of extrinsic evidence is impermissible.
Examiner respectfully disagrees. See MPEP 2131.01 regarding the use of additional references. First, Examiner makes the assertion that x86 processors (in which Examiner specifically pointed out in the claim mapping) support Real Mode. Since this assertion is made with the current knowledge of the art and not necessarily from the prior art, the characteristic is “inherent”. Examiner provides a citation from the extrinsic evidence to explicitly show that this is a characteristic of an x86 processor. Furthermore, Applicant does not prove that the processor of Shah cannot support Real Mode. Therefore, the use of the citation to show a characteristic that is “inherent” is permissible (see MPEP 2131.01(III)). Therefore, Applicant’s remarks regarding that Shah fails to disclose a prefix indicating support for use of an immediate because the use of extrinsic evidence is impermissible is considered not persuasive.
Regarding arguments on page 17, paragraph 3 and page 19, paragraph 2, Applicant argues that Shah fails to teach the limitation “indicate support for use of the immediate value”.
Examiner respectfully disagrees. The Applicant does not specify what kind of support is to be indicated. Therefore, Examiner points to the 0x66 prefix to indicate the support for use of a 32-bit immediate value. Even if the prefix overrides/changes the previous immediate value size, the prefix is still indicating a type of support of the immediate value itself by indicating that it allows a 32-bit size rather than a 16-bit size (i.e., the support) and the claim limitations do not prohibit it otherwise. Therefore, the mapping of the limitation is proper and anticipates the prior art. Therefore, Applicants remarks regarding that Shah fails to teach the specific limitation is considered not persuasive.
Despite Applicant providing unpersuasive arguments, the alternate rejection of claims 1-2, 7-10, and 15-17 under 35 U.S.C. 102(a)(1), and corresponding rejections of claims 3 and 11 under 35 U.S.C. 103, has been withdrawn due to persuasive arguments on page 18, paragraph 6. However, the main rejection of claims 1-2, 4-5, 7-10, 12-13, 15-18, and 20 under 35 U.S.C. 102(a)(1), and corresponding rejections of claims 6, 14, and 19 under 35 U.S.C. 103, will be maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ALCANTARA-RAMOS whose telephone number is (571)272-4211. The examiner can normally be reached Mon-Fri 8:30-5:00 PST.
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
