DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communication filed on 03/30/2023.
Claims 1-20 are pending.
Claim Objections
Claim 18 is objected to because of the following informalities:
Claim 18: “a flit of a message authentication code (MAC) epoch” should read “the flit of the MAC epoch”; “the cache/mem interface message” should read “the CPI message”; and “a request” should read “the request”.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claims do not include at least one hardware element in the bodies. Claim 1 recites an interface and a link controller which can both be software, claim 9 recites a link controller and a device fabric which can both be software, and claim 17 recites an interface, a device fabric, and a CXL controller which can all be software. Note that the specification does not limit these elements to be hardware only. Thus, the claimed invention is directed to non-statutory subject matter. Claims 2-8, 10-16 and 18-20 are dependent to claims 1, 9, and 17 respectively and are rejected under 35 U.S.C. 101 under similar rationale.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7-13, and 15-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Erickson et al. (US 2023/0325540).
Claim 1, Erickson teaches:
An electronic device comprising:
an interface to communicatively couple with a second electronic device via a communication link; and a link controller configured to: (e.g., fig. 3, [0019], “FIG. 3 illustrates one specific embodiment of a memory system, generally designated 300, that employs a CXL Type 3 memory device in the form of a CXL buffer system-on-chip (SOC) 310. The memory system 300 includes a host 302 that interfaces with a memory module 304 primarily through a CXL link 306. For one embodiment, the host 302 includes a host CXL interface controller 308 for communicating over the CXL link 306 utilizing protocols consistent with the CXL standards, such as CXL.io and CXL.mem. For some embodiments that involve CXL Type 2 devices, an additional CXL.cache protocol may also be utilized” [0021], “Requests received by the CXL interface controller 311 are fed to MAC verification circuitry 312, which, in a containment mode of operation, performs MAC verifications on groups of requests. Tracking circuitry 314 cooperates with selective containment circuitry 316 and memory sub-ops circuitry 318 in a manner similar to that described above”)
identify, from the second electronic device over the communication link, a flit related to a request from the second electronic device to access a resource of the electronic device, wherein the flit is an element of a message authentication code (MAC) epoch; (e.g., figs. 4, 6, [0020], “Further referring to FIG. 3, the memory module 304 is configured to generally support the distributed CXL memory architecture, thus allowing one or more hosts such as host 302 to access module memory 322” [0021], “Requests received by the CXL interface controller 311 are fed to MAC verification circuitry 312, which, in a containment mode of operation, performs MAC verifications on groups of requests. Tracking circuitry 314 cooperates with selective containment circuitry 316 and memory sub-ops circuitry 318 in a manner similar to that described above” [0022], “transfers of requests involving the CXL buffer 310 are carried out using 528-bit packets, referred to as “flits.” Each flit may include one or more commands and/or other information (such as data and/or responses). For one specific protocol, while operating in the containment mode of operation, a given MAC is sent every five flits, with the five flits defining a MAC epoch. Thus, for every group of five flits, CXL.mem protocol responses must not be sent back to the host until the MAC epoch is verified” [0023], “To minimize latency that may arise due to verifying each MAC epoch, one specific embodiment of the CXL buffer 310 employs selective containment circuitry in the form of a multi-queue architecture for temporarily storing write information and responses during MAC epoch verification. FIG. 4 illustrates further details for one embodiment of the architecture, which generally includes a command path 402 and a response path 420. The command path 402 includes a host receive interface 404 that receives flits from the host 302. The host receive interface 404 feeds the received flits to a CXL.mem IDE and MAC verification circuit 406”)
generate, based on the flit, a cache/mem interface message related to the request, wherein the cache/mem interface message includes an indication of the MAC epoch; and (e.g., figs. 4, 6, [0025], “Further referring to FIG. 4, one embodiment of the selective containment circuitry 408 includes tracking circuitry in the form of flit tag circuitry 410 and flit parsing circuitry 412. Multiple distributed buffers in the form of a write containment queue 414 and a response containment queue 424 are also provided by the selective containment circuitry 408. Following initiation of the MAC epoch verification, the flits are passed to the flit tag circuitry 410, where each flit is tagged with a MAC ID. Once the MAC ID is tagged to each flit included in the MAC epoch, flit parsing circuitry 412 sorts the commands by command type and extends the MAC ID to each command. This conveniently provides a command level of granularity for tracking purposes…the flit parsing circuitry 412 also manages a write response flow along path 415, with responses then queued in the response containment queue 424 until the MAC epoch is verified”)
transmit, to a device fabric of the electronic device, the cache/mem interface message prior to receipt of a MAC related to the MAC epoch. (e.g., figs. 4, 6, [0025], “Further referring to FIG. 4, one embodiment of the selective containment circuitry 408 includes tracking circuitry in the form of flit tag circuitry 410 and flit parsing circuitry 412. Multiple distributed buffers in the form of a write containment queue 414 and a response containment queue 424 are also provided by the selective containment circuitry 408. Following initiation of the MAC epoch verification, the flits are passed to the flit tag circuitry 410, where each flit is tagged with a MAC ID. Once the MAC ID is tagged to each flit included in the MAC epoch, flit parsing circuitry 412 sorts the commands by command type and extends the MAC ID to each command. This conveniently provides a command level of granularity for tracking purposes…the flit parsing circuitry 412 also manages a write response flow along path 415, with responses then queued in the response containment queue 424 until the MAC epoch is verified” [0029], “Further referring to FIG. 4, the response containment queue 424 forms a portion of the response path 420 and provides temporary storage for responses associated with the flits undergoing MAC epoch verification. The responses may take the form of alerts, acknowledgements, read data, and the like. A CXL.mem IDE circuit 426 couples to the output of the response containment queue 424 and serves to organize uncontained responses into the proper encrypted IDE protocol for transmission to the host via a host transmit interface 428”)
Claim 2, Erickson teaches:
wherein the link controller is further to: identify, subsequent to transmission of the cache/mem interface message, the MAC; process the MAC; and provide, based on the processing of the MAC, an indication related to authentication of the MAC. (e.g., figs. 4, 6, [0031]-[0033])
Claim 3, Erickson teaches:
wherein the indication of the MAC epoch includes an indication of validity of an identifier related to the MAC epoch. (e.g., figs. 4, 6, [0024]-[0025])
Claim 4, Erickson teaches:
wherein the identifier is an epoch identifier (ID) that identifies the MAC epoch. (e.g., figs. 4, 6, [0024]-[0025])
Claim 5, Erickson teaches:
wherein the epoch ID is a single bit. (e.g., figs. 4, 6, [0024]-[0025])
Claim 7, Erickson teaches:
wherein the link controller is a compute express link (CXL) controller. (e.g., fig. 3, [0019], [0021])
Claim 8, Erickson teaches:
wherein the cache/mem interface message is a compute express link (CXL) cache/mem protocol interface (CPI) message. (e.g., figs. 3-4, [0019], [0022], [0029])
Claim 9, Erickson teaches:
An electronic device comprising:
a link controller to couple with a second electronic device via a communication link; and (e.g., fig. 3, [0019], “FIG. 3 illustrates one specific embodiment of a memory system, generally designated 300, that employs a CXL Type 3 memory device in the form of a CXL buffer system-on-chip (SOC) 310. The memory system 300 includes a host 302 that interfaces with a memory module 304 primarily through a CXL link 306. For one embodiment, the host 302 includes a host CXL interface controller 308 for communicating over the CXL link 306 utilizing protocols consistent with the CXL standards, such as CXL.io and CXL.mem. For some embodiments that involve CXL Type 2 devices, an additional CXL.cache protocol may also be utilized” [0021], “Requests received by the CXL interface controller 311 are fed to MAC verification circuitry 312, which, in a containment mode of operation, performs MAC verifications on groups of requests. Tracking circuitry 314 cooperates with selective containment circuitry 316 and memory sub-ops circuitry 318 in a manner similar to that described above”)
a device fabric configured to:
identify, from the link controller, a cache/mem interface message related to a flit of a message authentication code (MAC) epoch, wherein the cache/mem interface message includes an indication of a request related to the flit, and wherein the cache/mem interface message includes an indication of the MAC epoch; (e.g., figs. 4, 6, [0020], “Further referring to FIG. 3, the memory module 304 is configured to generally support the distributed CXL memory architecture, thus allowing one or more hosts such as host 302 to access module memory 322” [0021], “Requests received by the CXL interface controller 311 are fed to MAC verification circuitry 312, which, in a containment mode of operation, performs MAC verifications on groups of requests. Tracking circuitry 314 cooperates with selective containment circuitry 316 and memory sub-ops circuitry 318 in a manner similar to that described above” [0022], “transfers of requests involving the CXL buffer 310 are carried out using 528-bit packets, referred to as “flits.” Each flit may include one or more commands and/or other information (such as data and/or responses). For one specific protocol, while operating in the containment mode of operation, a given MAC is sent every five flits, with the five flits defining a MAC epoch. Thus, for every group of five flits, CXL.mem protocol responses must not be sent back to the host until the MAC epoch is verified” [0023], “To minimize latency that may arise due to verifying each MAC epoch, one specific embodiment of the CXL buffer 310 employs selective containment circuitry in the form of a multi-queue architecture for temporarily storing write information and responses during MAC epoch verification. FIG. 4 illustrates further details for one embodiment of the architecture, which generally includes a command path 402 and a response path 420. The command path 402 includes a host receive interface 404 that receives flits from the host 302. The host receive interface 404 feeds the received flits to a CXL.mem IDE and MAC verification circuit 406” [0025], “Further referring to FIG. 4, one embodiment of the selective containment circuitry 408 includes tracking circuitry in the form of flit tag circuitry 410 and flit parsing circuitry 412. Multiple distributed buffers in the form of a write containment queue 414 and a response containment queue 424 are also provided by the selective containment circuitry 408. Following initiation of the MAC epoch verification, the flits are passed to the flit tag circuitry 410, where each flit is tagged with a MAC ID. Once the MAC ID is tagged to each flit included in the MAC epoch, flit parsing circuitry 412 sorts the commands by command type and extends the MAC ID to each command. This conveniently provides a command level of granularity for tracking purposes…the flit parsing circuitry 412 also manages a write response flow along path 415, with responses then queued in the response containment queue 424 until the MAC epoch is verified”)
at least partially process the request; and (e.g., figs. 4, 6, [0025], “Further referring to FIG. 4, one embodiment of the selective containment circuitry 408 includes tracking circuitry in the form of flit tag circuitry 410 and flit parsing circuitry 412. Multiple distributed buffers in the form of a write containment queue 414 and a response containment queue 424 are also provided by the selective containment circuitry 408. Following initiation of the MAC epoch verification, the flits are passed to the flit tag circuitry 410, where each flit is tagged with a MAC ID. Once the MAC ID is tagged to each flit included in the MAC epoch, flit parsing circuitry 412 sorts the commands by command type and extends the MAC ID to each command. This conveniently provides a command level of granularity for tracking purposes…the flit parsing circuitry 412 also manages a write response flow along path 415, with responses then queued in the response containment queue 424 until the MAC epoch is verified” [0029], “Further referring to FIG. 4, the response containment queue 424 forms a portion of the response path 420 and provides temporary storage for responses associated with the flits undergoing MAC epoch verification. The responses may take the form of alerts, acknowledgements, read data, and the like. A CXL.mem IDE circuit 426 couples to the output of the response containment queue 424 and serves to organize uncontained responses into the proper encrypted IDE protocol for transmission to the host via a host transmit interface 428”)
identify, from the link controller after at least partially processing the request, an indication of validity of a MAC related to the MAC epoch. (e.g., figs. 4, 6, [0033], “Further referring to FIG. 6, while the memory changing commands and information reside in containment, the selective containment circuitry 408 enables as many sub-operations to be accomplished as possible during the MAC verification interval while still inhibiting any changes to the memory. This background processing involves applying a MAC ID tag at a command level of granularity, at 616, and parsing the tagged commands, at 618, so they may be distributed to various locations in the CXL buffer. The sub-operations associated with the memory changing commands may then be performed, at 620. During the selective containment and background processing, the MAC epoch verification is monitored, at 622. When the verification is successfully completed, the CXL.mem IDE and MAC verification circuitry 406 updates and forwards its tracked verification status and verified MAC IDs to verification tables managed by the write containment queues 414 and the response containment queue 424. Associated commands tagged with the verified MAC ID for the successfully-verified flits identified in the MAC verification tables may then be released from containment and passed to both the memory transmit interface 416 (for writes) to allow performance of memory modifying operations, at 624, and dispatches to the host transmit interface 428 (for responses). In this way, once the verification for the given MAC epoch of flits is completed, and the containment halted, then the actual transfer of information may take place more quickly and with less latency than would otherwise have occurred if the sub-operations had not already been performed”)
Claim 10, Erickson teaches:
wherein the device fabric is further to: completing, based on the indication of validity, the processing of the request; and providing, to the link controller, an indication of a result of processing the request. (e.g., figs. 4, 6, [0031]-[0033])
Claim 11, this claim is directed to a device containing similar limitations as recited in claim 3 and is rejected for similar rationale.
Claim 12, this claim is directed to a device containing similar limitations as recited in claim 4 and is rejected for similar rationale.
Claim 13, this claim is directed to a device containing similar limitations as recited in claim 5 and is rejected for similar rationale.
Claim 15, this claim is directed to a device containing similar limitations as recited in claim 7 and is rejected for similar rationale.
Claim 16, this claim is directed to a device containing similar limitations as recited in claim 8 and is rejected for similar rationale.
Claim 17, Erickson teaches:
An electronic device comprising:
an interface to communicatively couple with a second electronic device via a compute express link (CXL); (e.g., fig. 3, [0019], “FIG. 3 illustrates one specific embodiment of a memory system, generally designated 300, that employs a CXL Type 3 memory device in the form of a CXL buffer system-on-chip (SOC) 310. The memory system 300 includes a host 302 that interfaces with a memory module 304 primarily through a CXL link 306. For one embodiment, the host 302 includes a host CXL interface controller 308 for communicating over the CXL link 306 utilizing protocols consistent with the CXL standards, such as CXL.io and CXL.mem. For some embodiments that involve CXL Type 2 devices, an additional CXL.cache protocol may also be utilized” [0021], “Requests received by the CXL interface controller 311 are fed to MAC verification circuitry 312, which, in a containment mode of operation, performs MAC verifications on groups of requests. Tracking circuitry 314 cooperates with selective containment circuitry 316 and memory sub-ops circuitry 318 in a manner similar to that described above”)
a device fabric; and (e.g., figs. 4, 6, [0025], “Further referring to FIG. 4, one embodiment of the selective containment circuitry 408 includes tracking circuitry in the form of flit tag circuitry 410 and flit parsing circuitry 412. Multiple distributed buffers in the form of a write containment queue 414 and a response containment queue 424 are also provided by the selective containment circuitry 408. Following initiation of the MAC epoch verification, the flits are passed to the flit tag circuitry 410, where each flit is tagged with a MAC ID. Once the MAC ID is tagged to each flit included in the MAC epoch, flit parsing circuitry 412 sorts the commands by command type and extends the MAC ID to each command. This conveniently provides a command level of granularity for tracking purposes…the flit parsing circuitry 412 also manages a write response flow along path 415, with responses then queued in the response containment queue 424 until the MAC epoch is verified”)
a CXL controller configured to:
identify, from the second electronic device over the CXL link, a flit related to a request from the second electronic device to access a resource of the electronic device, wherein the flit is an element of a message authentication code (MAC) epoch; (e.g., figs. 4, 6, [0020], “Further referring to FIG. 3, the memory module 304 is configured to generally support the distributed CXL memory architecture, thus allowing one or more hosts such as host 302 to access module memory 322” [0021], “Requests received by the CXL interface controller 311 are fed to MAC verification circuitry 312, which, in a containment mode of operation, performs MAC verifications on groups of requests. Tracking circuitry 314 cooperates with selective containment circuitry 316 and memory sub-ops circuitry 318 in a manner similar to that described above” [0022], “transfers of requests involving the CXL buffer 310 are carried out using 528-bit packets, referred to as “flits.” Each flit may include one or more commands and/or other information (such as data and/or responses). For one specific protocol, while operating in the containment mode of operation, a given MAC is sent every five flits, with the five flits defining a MAC epoch. Thus, for every group of five flits, CXL.mem protocol responses must not be sent back to the host until the MAC epoch is verified” [0023], “To minimize latency that may arise due to verifying each MAC epoch, one specific embodiment of the CXL buffer 310 employs selective containment circuitry in the form of a multi-queue architecture for temporarily storing write information and responses during MAC epoch verification. FIG. 4 illustrates further details for one embodiment of the architecture, which generally includes a command path 402 and a response path 420. The command path 402 includes a host receive interface 404 that receives flits from the host 302. The host receive interface 404 feeds the received flits to a CXL.mem IDE and MAC verification circuit 406”)
generate, based on the flit, a CXL-cache/mem protocol interface (CPI) message related to the request, wherein the CPI message includes an indication of the MAC epoch; and (e.g., figs. 4, 6, [0025], “Further referring to FIG. 4, one embodiment of the selective containment circuitry 408 includes tracking circuitry in the form of flit tag circuitry 410 and flit parsing circuitry 412. Multiple distributed buffers in the form of a write containment queue 414 and a response containment queue 424 are also provided by the selective containment circuitry 408. Following initiation of the MAC epoch verification, the flits are passed to the flit tag circuitry 410, where each flit is tagged with a MAC ID. Once the MAC ID is tagged to each flit included in the MAC epoch, flit parsing circuitry 412 sorts the commands by command type and extends the MAC ID to each command. This conveniently provides a command level of granularity for tracking purposes…the flit parsing circuitry 412 also manages a write response flow along path 415, with responses then queued in the response containment queue 424 until the MAC epoch is verified”)
transmit, to the device fabric, the CPI message prior to receipt of a MAC related to the MAC epoch. (e.g., figs. 4, 6, [0025], “Further referring to FIG. 4, one embodiment of the selective containment circuitry 408 includes tracking circuitry in the form of flit tag circuitry 410 and flit parsing circuitry 412. Multiple distributed buffers in the form of a write containment queue 414 and a response containment queue 424 are also provided by the selective containment circuitry 408. Following initiation of the MAC epoch verification, the flits are passed to the flit tag circuitry 410, where each flit is tagged with a MAC ID. Once the MAC ID is tagged to each flit included in the MAC epoch, flit parsing circuitry 412 sorts the commands by command type and extends the MAC ID to each command. This conveniently provides a command level of granularity for tracking purposes…the flit parsing circuitry 412 also manages a write response flow along path 415, with responses then queued in the response containment queue 424 until the MAC epoch is verified” [0029], “Further referring to FIG. 4, the response containment queue 424 forms a portion of the response path 420 and provides temporary storage for responses associated with the flits undergoing MAC epoch verification. The responses may take the form of alerts, acknowledgements, read data, and the like. A CXL.mem IDE circuit 426 couples to the output of the response containment queue 424 and serves to organize uncontained responses into the proper encrypted IDE protocol for transmission to the host via a host transmit interface 428”)
Claim 18, Erickson teaches:
wherein the device fabric is configured to:
identify, from the link controller, the CPI message related to a flit of a message authentication code (MAC) epoch, wherein the cache/mem interface message includes an indication of a request related to the flit, and wherein the cache/mem interface message includes an indication of the MAC epoch; (e.g., figs. 4, 6, [0020]-[0023], [0025])
at least partially process, based on the CPI message, the request; and (e.g., figs. 4, 6, [0025], [0029])
identify, from the link controller after at least partially processing the request, an indication of validity of a MAC related to the MAC epoch. (e.g., figs. 4, 6, [0033])
Claim 19, Erickson teaches:
wherein the electronic device is a CXL host device. (e.g., fig. 3, [0019]-[0020])
Claim 20, Erickson teaches:
wherein the second electronic device is a CXL host device. (e.g., fig. 3, [0019]-[0021])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Erickson et al. (US 2023/0325540) in view of Dally et al. (US 2001/0038634).
Claim 6, Erickson teaches the identifier, the flit (see above) and does not appear to explicitly teach but Dally teaches:
a port identifier (ID) that is related to a port on which a flit was received. (e.g., [0088]-[0089])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings described by Dally into the invention of Erickson, and the motivation for such an implementation would be for the purpose of overcoming bandwidth and scalability limitations (Dally [0046], [0084]).
Claim 14, this claim is directed to a device containing similar limitations as recited in claim 6 and is rejected using the same rationale to combine the references.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2021/0089388 teaches techniques for providing data integrity for link communications.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMIE C LIN whose telephone number is (571)272-7752. The examiner can normally be reached M-F 9:00AM -5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GELAGAY SHEWAYE can be reached at (571)272-4219. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AMIE C. LIN/Primary Examiner, Art Unit 2436