CTNF 18/193,237 CTNF 82148 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Madduri et al. US Patent No. 10,224,954 (hereinafter Madduri) in view of Deng US PG-Pub No. 2023/0289558 (hereinafter Deng) . As per claim 1, Madduri teaches an apparatus comprising: decoder circuitry to decode an instance of a single instruction (Fig. 4, element 405 decoder; also abstract), the instance of the single instruction to at least include fields for an opcode (abstract, opcode), an identification of location of a packed data source operand (abstract, packed data source operand identifier), an identification of location of a packed data destination operand (abstract, packed data destination operation identifier), and an indication of a location in each packed data element of the packed data destination to store integer value (Fig. 1, INTEGER in the destination 121), wherein the opcode is to indicate conversion circuitry is to downconvert data of each packed data element of the packed data source operand to an integer value and provide the integer value for storage in the identified location of a corresponding packed data element of the packed data destination (Fig. 1 and abstract, also, Fig. 2, element 207; more details of the conversion in Example 1 and 6 of cols. 17 and 18); and execution circuitry to execute the decoded instance of the single instruction according to the opcode (abstract, execution circuit); Madduri did not specifically teach that the integer is an 8-bit integer (INT8). However, the secondary prior art Deng teaches a conversion from floating point to 8-bit integer (INT8) (Deng, paragraph [0002]), for the purpose of accelerating deep learning operation in neural network model. It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to combine the teaching of Deng of having an 8-bit integer into Madduri. It would result in a reduction in model storage and memory footprint and improves overall computing time. As per claim 2, Madduri further teaches wherein the packed data source operand is a vector register (col. 2, lines 25-30) As per claim 3, Madduri further teaches wherein the packed data source operand is a memory location (col. 2, lines 24-47). As per claims 4 and 5, Madduri further teaches wherein the INT8 value is signed or unsigned (co. 4, lines 31-40, wherein the integer can be a signed or unsigned. Furthermore, as well known in the art, it’s a designed choice to have the integer a signed or unsigned). As per claim 6 and 7, Madduri further teaches wherein the data of each packed data element of the packed data source operand is in a 16-bit or 32-bit floating point format (see examples in Col. 20 and as well known in the art, the size of the floating-point format is a design choice). As per claim 8, Madduri further teaches wherein the data of each packed data element of the packed data source operand is in a 16-bit brain-float floating point (BF16) format (see examples in col. 20. Furthermore, as it would have been obvious to a person of ordinary skill to implement the prior art’s floating ‑ point packed elements in BF16, a known floating ‑ point format, to reduce memory/bandwidth and increase SIMD/throughput while preserving range exponents, a design choice widely adopted in hardware). As per claim 9, Madduri further teaches wherein the indication of a location in each packed data element of the packed data destination to store an INT8 value is to be provided by an immediate (abstract, zero the remaining are equivalent to immediate, also col. 7, line 50). As per claim 10, Madduri further teaches wherein when a downconversion is inexact a floating-point precision exception is raised and a truncated INT8 value is generated (abstract, zero remaining packed data elements is equivalent to truncating integer value). As per claim 11, Madduri further teaches wherein when a downconversion is inexact a floating-point precision exception is raised and a rounded INT8 value is generated (see abstract, zero remaining packed data elements. It would have been an obvious design choice to one of ordinary skill in the art to truncated or round the integer value). As per claims 12-17, they’re rejected for the same reasons set forth above in claims 1-5, 9. As per claims 18-20, they’re rejected for the same reasons set forth above in claims 1, 4-5 . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US PG-Pub 2021/0406012 – loading and storing matrix data with datatype conversion. US Patent 10956160 – multi-level reservation station with instruction recirculation. US Patent 10223114 – fixed point to floating point conversion. Any inquiry concerning this communication or earlier communications from the examiner should be directed to IDRISS N ALROBAYE whose telephone number is (571)270-1023. The examiner can normally be reached Mon-Fri, 8am-4:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Cottingham can be reached at 571-272-1400. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IDRISS N ALROBAYE/ Supervisory Patent Examiner, Art Unit 2181 Application/Control Number: 18/193,237 Page 2 Art Unit: 2181 Application/Control Number: 18/193,237 Page 3 Art Unit: 2181 Application/Control Number: 18/193,237 Page 4 Art Unit: 2181 Application/Control Number: 18/193,237 Page 5 Art Unit: 2181
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