DETAILED ACTION
Applicants’ response filed 8/24/26 has been considered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Prior art rejections are maintained in view of remarks herein. See prior office action for details.
No amendments were made to the claims.
Application is pending.
Response to Arguments
Applicants’ arguments filed 8/24/2026 have been fully considered but they are not persuasive.
For example, claim 1 recites:
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Applicants contend the cited art does not appear to describe, “…a plurality of infield control debug registers to control execution of the test instruction, wherein access to the plurality of infield testing debug registers and the plurality of infield control debug registers is programmable.”
The Examiner respectfully disagrees.
The claim language has not been amended and the claim limitations are broad.
Applicants are reminded that the rejection was presented under 35 USC 103 rationale.
In accordance with MPEP 2111, under broadest reasonable interpretations, the claim basically states the following:
BIST controller to perform test on a logic
Storage to store test instructions
Registers to store execution information of test instructions
Registers to control execution of test instructions
Access to both registers is programmable
As stated in the prior office action D1 substantially teaches all of these concepts which are broad and do not add anything meaningful.
BIST controller to perform test on a logic (i.e., Figure 1, scan test circuit 160 to test logic 150 and paragraph 0011)
Storage to store test instructions (i.e., Figure 1, memory 130 stores test instructions and paragraph 0010)
Registers to store execution information of test instructions (i.e., Figure 1 and paragraph 0010; “…the test pattern generator 122 and debug protocol module 124 are modules that are instantiated as executing program code within the processor 120…”)
Registers to control execution of test instructions (i.e., Figure 1 and paragraphs 0010-0014), “The processor 120 implements a test pattern generator 122 and a debug protocol 124 to perform various forms of scan testing, functional mode testing and debugging of an integrated circuit. The memory 130 stores various types of data such as scan data 132 and internal register state data 134, which is accessed from the integrated circuit 140 when the integrated circuit 140 is scan tested or debugged using the tester 110.” “…debugging of failure conditions and errors of the integrated circuit 140 can be implemented using the internal registers 180, the debug controller 190, and the debug controller interface 192, in conjunction with the scan test circuitry 160 and the scan control circuitry 170 to verify operability of the integrated circuit 140 during actual use.”
Access to both registers is programmable (i.e., Figure 1 and paragraphs 0010-0014), “The processor 120 implements a test pattern generator 122 and a debug protocol 124 to perform various forms of scan testing, functional mode testing and debugging of an integrated circuit.” “… the test pattern generator 122 and debug protocol module 124 are implemented using dedicated logic circuits and firmware, which are part of a special purpose processor designed with the special purpose hardware and/or firmware to perform scan testing and debugging functions.” “…a debug process (which is implemented via the debug protocol 124) provides various debug test signals such as debug test clocks and control signals, as well as debug test data to the integrated circuit 140.”
Therefore it is the Examiner’s conclusion that the claims of the present application, as presented, are not patentably novel over the prior arts.
Applicants are encouraged to formulate claim language that clearly defines the novelty of the application.
Prior rejections are maintained. See prior office action for details.
Application is pending.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUJTABA M CHAUDRY whose telephone number is (571)272-3817. The examiner can normally be reached Monday-Friday 9am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert DeCady can be reached at 571-272-3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MUJTABA M. CHAUDRY
Primary Examiner
Art Unit 2112
/MUJTABA M CHAUDRY/Primary Examiner, Art Unit 2112
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