DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to art rejections of claim(s) 1,3,4,11,15,16,17,18,23,27,28 and 32 have been considered but are moot because due to the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 1/05/2026 regarding the 112 rejections below have been fully considered but they are not persuasive.
Regarding claims 1-32 applicant argues, The voltage code calibrating circuit configured to calibrate at least one voltage code for adjusting a voltage level of the at least one reference voltage based on the at least one comparison signal is disclosed in the patents listed below. Fig. 3 of US 10,665,314 shows a configuration of a control circuit 315 that generates a voltage trim code from the output of the comparator 314 and outputs the code to a variable impedance device 334 that adjusts the voltage according to the voltage trim code. See FIG. 3. The voltage code calibrating circuit set forth in the claims could therefore be readily implemented as described in the detailed description of the Applicant's pending application, for example in paragraph [0031], because a person of ordinary skill in the art is presumed to be aware of relevant prior art.
Examiner acknowledges applicants’ citation of US 10665314 but applicant’s specification fails to disclose what applicant’s voltage code calibrating circuit is. Applicant’s original disclosure fails to provide any structure of applicant’s voltage code calibrating circuit and the original disclose fails to disclose that the voltage code calibrating circuit is a well known circuit. Applicant appears to provide a citation to address enablement which is different than failure of written description. A person of ordinary skill in the art would not know what applicants’ voltage code calibrating circuit is and how it is implemented. Therefore suggesting a lack of written description.
Regarding claims 16 and 17, applicant argues "Internal operations" of electronic devices are well-known by any person of skill in the art to be operations or functions performed internally by the electronic device, simply as the phrase states. A person of skill in the art of electronic devices would clearly understand what functions are performed internally by an electronic device. All operations performed by an electronic device are performed internally, thus any operation performed by an electronic device is performed internally. Operations performed externally to an electronic device, or external operations, would not be performed internally and would not be identified as internal operations.
Examiner respectfully disagrees. The specification does not indicate what is considered internal operations and is therefore it is unclear as to what applicant is claiming.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1,3-32 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, the disclosure does not provide adequate structure of a voltage code calibrating circuit configured to calibrate at least one voltage code for adjusting a voltage level of the at least one reference voltage, based on the at least one comparison signal. (lines 7-9)
Par 0031 of the specification only recites that the voltage code calibrating circuit 109 may receive the first comparison signal COM1 and the second comparison signal COM2 from the comparison signal generating circuit 107. The voltage code calibrating circuit 109 may calibrate the first voltage code VCD1 and the second voltage code VCD2, based on the first comparison signal COM1 and the second comparison signal COM2. The voltage code calibrating circuit 109 may calibrate the first voltage code VCD1 and the second voltage code VCD2 to adjust the voltage level of each of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD according to the logic bit sets of the first comparison signal COM1 and the second comparison signal COM2.
There is no additional disclosure of any particular structure, either explicitly or inherently, of this circuit, sensor, or device. The use of the term circuit, sensor, or device is not adequate structure for performing the function. Examiner acknowledges the labelled box in the Figures for the above element, however the specification does not provide adequate description of the structure such that one of ordinary skill in the art would understand what circuit, sensor, or device performs the claimed functions. The original disclosure doesn’t reasonably demonstrate that applicant had possession of the claim features at issue because it does not reasonably demonstrate the manner in which these features are implemented.
Regarding claim 6, lines 4-9, the disclosure does not provide adequate structure for wherein the voltage code calibrating circuit is configured to calibrate the first voltage code and the second voltage code to increase the voltage level of each of the upper limit reference voltage and the lower limit reference voltage when the first comparison signal and the second comparison signal set to have the first logic bit set are received.
Par. 0031 of the specification only disclose the voltage code calibrating circuit 109 may receive the first comparison signal COM1 and the second comparison signal COM2 from the comparison signal generating circuit 107. The voltage code calibrating circuit 109 may calibrate the first voltage code VCD1 and the second voltage code VCD2, based on the first comparison signal COM1 and the second comparison signal COM2. The voltage code calibrating circuit 109 may calibrate the first voltage code VCD1 and the second voltage code VCD2 to adjust the voltage level of each of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD according to the logic bit sets of the first comparison signal COM1 and the second comparison signal COM2. As an example, the voltage code calibrating circuit 109 may calibrate the first voltage code VCD1 and the second voltage code VCD2 to increase the voltage level of each of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD when the sensing voltage VSEN is set to have a voltage level higher than that of the upper limit reference voltage VREFU and the first comparison signal COM1 and second comparison signal COM2 each set to have the first logic bit set are received.
There is no additional disclosure of any particular structure, either explicitly or inherently, of this circuit, sensor, or device. The use of the term circuit, sensor, or device is not adequate structure for performing the function. Examiner acknowledges the labelled box in the Figures for the above element, however the specification does not provide adequate description of the structure such that one of ordinary skill in the art would understand what is the applicant’s circuit, sensor, or device that performs the claimed functions. The original disclosure doesn’t reasonably demonstrate that applicant had possession of the claim features at issue because it does not reasonably demonstrate the manner in which these features are implemented.
Regarding claim 8, lines 1-6, the disclosure does not provide adequate structure of voltage code calibrating circuit is configured to calibrate the first voltage code and the second voltage code to decrease the voltage level of each of the upper limit reference voltage and the lower limit reference voltage when the first comparison signal and the second comparison signal set to have the second logic bit set are received.
Par. 0031 of the specification only disclose As another example, the voltage code calibrating circuit 109 may calibrate the first voltage code VCD1 and the second voltage code VCD2 to decrease the voltage level of each of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD when the sensing voltage VSEN is set to have a voltage level lower than that of the lower limit reference voltage VREFD and the first comparison signal COM1 and the second comparison signal COM2 each set to have the second logic bit set are received. As further another example, the voltage code calibrating circuit 109 may stop the calibration for the first voltage code VCD1 and the second voltage code VCD2 to maintain the voltage level of each of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD when the sensing voltage VSEN is set to have a voltage level equal to or higher than that of the lower limit reference voltage VREFD and equal to lower than that of the upper limit reference voltage VREFU and the first comparison signal COM1 and the second comparison signal COM2 each set to have the third logic bit set are received.
There is no additional disclosure of any particular structure, either explicitly or inherently, of this circuit, sensor, or device. The use of the term circuit, sensor, or device is not adequate structure for performing the function. Examiner acknowledges the labelled box in the Figures for the above element, however the specification does not provide adequate description of the structure such that one of ordinary skill in the art would understand what is the applicants circuit, sensor, or device that performs the claimed functions. The original disclosure doesn’t reasonably demonstrate that applicant had possession of the claim features at issue because it does not reasonably demonstrate the manner in which these features are implemented.
Regarding claim 10, lines 1-6, the disclosure does not provide adequate structure of the voltage code calibrating circuit is configured to stop calibrating the first voltage code and the second voltage code to maintain the voltage level of each of the upper limit reference voltage and the lower limit reference voltage when the first comparison signal and the second comparison signal set to have the third logic bit set are received.
Par. 0031 of the specification only disclose As further another example, the voltage code calibrating circuit 109 may stop the calibration for the first voltage code VCD1 and the second voltage code VCD2 to maintain the voltage level of each of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD when the sensing voltage VSEN is set to have a voltage level equal to or higher than that of the lower limit reference voltage VREFD and equal to lower than that of the upper limit reference voltage VREFU and the first comparison signal COM1 and the second comparison signal COM2 each set to have the third logic bit set are received.
There is no additional disclosure of any particular structure, either explicitly or inherently, of this circuit, sensor, or device. The use of the term circuit, sensor, or device is not adequate structure for performing the function. Examiner acknowledges the labelled box in the Figures for the above element, however the specification does not provide adequate description of the structure such that one of ordinary skill in the art would understand what is applicant’s circuit, sensor, or device that performs the claimed functions. The original disclosure doesn’t reasonably demonstrate that applicant had possession of the claim features at issue because it does not reasonably demonstrate the manner in which these features are implemented.
Regarding claims 17, Lines 7-8, the disclosure does not provide adequate structure of a processor configured to adjust speed and activation of an internal operation, based on the first voltage code.
Par 0082 of the specification only recites that the processor 403 may adjust the speed, activation status, and the line of the internal operation, based on a first voltage code VCD1 and a second voltage code VCD2.
There is no additional disclosure of any particular structure, either explicitly or inherently, of this processor. The use of the term processor is not adequate structure for performing the function. As such, the specification does not provide adequate description of the structure such that one of ordinary skill in the art would understand what processor performs the claimed functions. Futhermore a remote control for a tv can be interpreted as a processor. The original disclosure doesn’t reasonably demonstrate that applicant had possession of the claim features at issue because it does not reasonably demonstrate what the device is and the manner in which these features are implemented.
Regarding claim 20, lines 2-7, the disclosure does not provide adequate structure of a voltage code calibrating circuit configured to calibrate the first voltage code and the second voltage code to increase the voltage level of each of the upper limit reference voltage and the lower limit reference voltage when the first comparison signal and the second comparison signal set to have the first logic bit set are received.
Par. 0031 of the specification only discloses As an example, the voltage code calibrating circuit 109 may calibrate the first voltage code VCD1 and the second voltage code VCD2 to increase the voltage level of each of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD when the sensing voltage VSEN is set to have a voltage level higher than that of the upper limit reference voltage VREFU and the first comparison signal COM1 and second comparison signal COM2 each set to have the first logic bit set are received. As another example, the voltage code calibrating circuit 109 may calibrate the first voltage code VCD1 and the second voltage code VCD2 to decrease the voltage level of each of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD when the sensing voltage VSEN is set to have a voltage level lower than that of the lower limit reference voltage VREFD and the first comparison signal COM1 and the second comparison signal COM2 each set to have the second logic bit set are received.
There is no additional disclosure of any particular structure, either explicitly or inherently, of this circuit, sensor, or device. The use of the term circuit, sensor, or device is not adequate structure for performing the function. Examiner acknowledges the labelled box in the Figures for the above element, however the specification does not provide adequate description of the structure such that one of ordinary skill in the art would understand what is applicant’s circuit, sensor, or device that performs the claimed functions.
Regarding claim 21, lines 7-12, the disclosure does not provide adequate structure for voltage code calibrating circuit is configured to calibrate the first voltage code and the second voltage code to decrease the voltage level of each of the upper limit reference voltage and the lower limit reference voltage when the first comparison signal and the second comparison signal set to have the second logic bit set are received.
Par. 0031 of the specification only discloses As an example, the voltage code calibrating circuit 109 may calibrate the first voltage code VCD1 and the second voltage code VCD2 to increase the voltage level of each of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD when the sensing voltage VSEN is set to have a voltage level higher than that of the upper limit reference voltage VREFU and the first comparison signal COM1 and second comparison signal COM2 each set to have the first logic bit set are received. As another example, the voltage code calibrating circuit 109 may calibrate the first voltage code VCD1 and the second voltage code VCD2 to decrease the voltage level of each of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD when the sensing voltage VSEN is set to have a voltage level lower than that of the lower limit reference voltage VREFD and the first comparison signal COM1 and the second comparison signal COM2 each set to have the second logic bit set are received.
There is no additional disclosure of any particular structure, either explicitly or inherently, of this circuit, sensor, or device. The use of the term circuit, sensor, or device is not adequate structure for performing the function. Examiner acknowledges the labelled box in the Figures for the above element, however the specification does not provide adequate description of the structure such that one of ordinary skill in the art would understand what is applicant’s circuit, sensor, or device that performs the claimed functions.
Regarding claim 22, lines 8-13, the disclosure does not provide adequate structure of wherein the voltage code calibrating circuit is configured to stop calibration of the first voltage code and the second voltage code to maintain the voltage level of each of the upper limit reference voltage and the lower limit reference voltage when the first comparison signal and the second comparison signal set to have the third logic bit set are received.
Par. 0031 only discloses the voltage code calibrating circuit 109 may stop the calibration for the first voltage code VCD1 and the second voltage code VCD2 to maintain the voltage level of each of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD when the sensing voltage VSEN is set to have a voltage level equal to or higher than that of the lower limit reference voltage VREFD and equal to lower than that of the upper limit reference voltage VREFU and the first comparison signal COM1 and the second comparison signal COM2 each set to have the third logic bit set are received. The method of calibrating the first voltage code VCD1 and the second voltage code VCD2 to increase or decrease the voltage levels of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD may be set in various ways according to embodiments.
There is no additional disclosure of any particular structure, either explicitly or inherently, of this circuit, sensor, or device. The use of the term circuit, sensor, or device is not adequate structure for performing the function. Examiner acknowledges the labelled box in the Figures for the above element, however the specification does not provide adequate description of the structure such that one of ordinary skill in the art would understand what is applicant’s circuit, sensor, or device that performs the claimed functions.
Regarding claim 28, the disclosure does not provide adequate structure of, calibrating a first voltage code, based on the at least one comparison signal (lines 7-8); calibrating a second voltage code, based on at least one comparison signal. (lines 13-14)
Par 0031 of the specification only recites that the voltage code calibrating circuit 109 may receive the first comparison signal COM1 and the second comparison signal COM2 from the comparison signal generating circuit 107. The voltage code calibrating circuit 109 may calibrate the first voltage code VCD1 and the second voltage code VCD2, based on the first comparison signal COM1 and the second comparison signal COM2. The voltage code calibrating circuit 109 may calibrate the first voltage code VCD1 and the second voltage code VCD2 to adjust the voltage level of each of the upper limit reference voltage VREFU and the lower limit reference voltage VREFD according to the logic bit sets of the first comparison signal COM1 and the second comparison signal COM2.
There is no additional disclosure of any particular structure, either explicitly or inherently, of this circuit, sensor, or device. The use of the term circuit, sensor, or device is not adequate structure for performing the function. Examiner acknowledges the labelled box in the Figures for the above element, however the specification does not provide adequate description of the structure such that one of ordinary skill in the art would understand what is applicant’s circuit, sensor, or device that performs the claimed functions.
Regarding claims 1,6,8,10,17,18,20,21,22,28,29,30, 31 containing voltage code calibrating. Applicant’s disclosure does not reasonably demonstrate proper written description for the voltage code calibration, because applicant’s disclosure does not reasonably provide structure for the voltage code calibration circuit, explain the manner in which applicant calibrates the code when it is determined that calibration is needed. The original disclosure is silent as to the manner as to what triggers the calibration, whether the calibration code is increased or decreased and if so by how much. The original disclosure fails to provide any formulas, flow charts, or other reasonable explanation to demonstrate the manner in which applicant implements the voltage code calibration such that a person of ordinary skill in the art would recognize that applicant had possession of this claim feature. As such, this voltage code calibration lacks proper written description.
Claims 4,5, 7,9,11-16,19,23-27,32 stand rejected for incorporating and reciting the above rejected subject matter of their respective parent claim(s) and therefore stand rejected for the same reasons.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 16, line 3, the metes and bounds of an internal operation is unclear. A person of ordinary skill in the art would not reasonably recognize what an internal operation would and would not include. Because applicant does not provide any reasonable explanation or example of an internal operation, it is unclear what operations would and would not be considered an internal operation.
Regarding claim 17, line 8, the metes and bounds of an internal operation is unclear. A person of ordinary skill in the art would not reasonably recognize what an internal operation would and would not include. Because applicant does not provide any reasonable explanation or example of an internal operation, it is unclear what operations would and would not be considered an internal operation.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 28 is rejected under 35 U.S.C. (a)(1) as being anticipated by Goh et al. (US 20090110028).
Regarding claim 28, Goh et al. teach A method of performing an internal calibration operation, the method comprising:
generating a sensing voltage set to have a first voltage level under a first sensing condition that includes at least one of temperature and light intensity; (Note claim 1, supplying at least one of a current and a voltage to a thermistor at a first level via an adjustable power source)
comparing the sensing voltage with at least one reference voltage to generate at least one comparison signal; (Note claim 1, comparing said thermistor voltage with a first threshold and with a second threshold)
calibrating a first voltage code, based on the at least one comparison signal; (Note claim 1, adjusting said at least one of said current and said voltage supplied to said thermistor by controlling said adjustable power source based on said comparison.)
Goh et al. inherently teach the following because the steps are merely being performed twice. (Note steps above)
generating the sensing voltage set to have a second voltage level under a second sensing condition;
comparing the sensing voltage with the at least one reference voltage to generate at least one comparison signal; and
calibrating a second voltage code, based on at least one comparison signal.
Note MPEP 2112.02(I) “Under the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986).”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Goh et al. (US 20090110028) in view of Pertijs et al. (US 20080069176).
Regarding claim 1, Goh et al. teach A sensor circuit comprising:
a sensing voltage generating circuit configured to generate a sensing voltage set to have a voltage level corresponding to a sensing condition that includes at least one of temperature and light intensity; (Note par. 0009)
a sensing condition setting circuit configured to apply the sensing condition to the sensing voltage generating circuit; (Note par. 0009, an auto-range hysteresis logic coupled to the thermistor and the adjustable power source, the auto-range hysteresis logic operable to output a signal to control the adjustable power source by sensing a thermistor voltage across the thermistor.)
a comparison signal generating circuit configured to compare the sensing voltage with at least one reference voltage to generate at least one comparison signal; (Note claim 1, comparing said thermistor voltage with a first threshold and with a second threshold) and
Goh et al. does not teach a voltage code calibrating circuit configured to calibrate at least one voltage code for adjusting a voltage level of the at least one reference voltage based on the at least one comparison signal.
Peretijs et al. teach a voltage code calibrating circuit configured to calibrate at least one voltage code for adjusting a voltage level of the at least one reference voltage based on the at least one comparison signal. (Note par. 0006, the method comprising the steps of determining the value of the internal reference voltage outputted by the reference voltage source, comparing it with the desired reference voltage value, and adjusting the reference voltage source in response to the result of the comparison step; also note [0036] The core of the temperature sensor of FIG. 3 is formed by two substrate PNP transistors (in a CMOS process), which are biased using a set of three current sources: I.sub.high and I.sub.low, which have a well-defined (possibly dynamically matched) ratio m (i.e. I.sub.high=m I.sub.low); and I.sub.trim, the value of which can be digitally adjusted by changing trim_val in PROM.)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. to include the teaching of a voltage code calibrating circuit configured to calibrate at least one voltage code for adjusting a voltage level of the at least one reference voltage based on the at least one comparison signal to perform calibration much faster than a traditional thermal calibration. (Note abstract)
Regarding claim 15, Goh et al. does Goh et al. does not teach a voltage code storage circuit configured to receive and store the voltage code.
Pertis et al. teach a voltage code storage circuit configured to receive and store the voltage code. ([0045] The trim value, to be stored in PROM, can be communicated to the chip using a bus interface, which is also used for reading out the sensor during normal operation.)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. to include the teaching of a voltage code storage circuit configured to receive and store the voltage code to use for calibrating the sensor.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Goh et al. (US 20090110028) in view of Pertijs et al. (US 20080069176) further in view of Uemura (US 20220038054).
Goh et al. as modified teach the instant invention except the following limitations.
Regarding claim 3, Goh et al. does not teach wherein the sensing condition includes a first sensing condition and a second sensing condition, and wherein the sensing voltage generating circuit is configured to generate the sensing voltage set to a first voltage level corresponding to the first sensing condition, and to generate the sensing voltage set to a second voltage level corresponding to the second sensing condition.
Uemura teach wherein the sensing condition includes a first sensing condition and a second sensing condition (Note high temperature and low temperature, [pars. 0072, 0073], and wherein the sensing voltage generating circuit is configured to generate the sensing voltage set to a first voltage level corresponding to the first sensing condition, and to generate the sensing voltage set to a second voltage level corresponding to the second sensing condition. [Note par. 0073]
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. as modified to include the teaching of wherein the sensing condition includes a first sensing condition and a second sensing condition, and wherein the sensing voltage generating circuit is configured to generate the sensing voltage set to a first voltage level corresponding to the first sensing condition, and to generate the sensing voltage set to a second voltage level corresponding to the second sensing condition to help indicate an error regarding temperature. (Note Uemura par. 0081)
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Goh et al. (US 20090110028) in view of Pertijs et al. (US 20080069176) further in view of Kim et al. (KR 20170055676A).
Goh et al. teach the instant invention except the following limitations.
Regarding claim 4, Goh et al. does not teach at least one reference voltage includes an upper limit reference voltage and a lower limit reference voltage, and wherein the upper limit reference voltage is set to have a voltage level higher than that of the lower limit reference voltage.
Kim et al. teach at least one reference voltage includes an upper limit reference voltage and a lower limit reference voltage, and wherein the upper limit reference voltage is set to have a voltage level higher than that of the lower limit reference voltage. (Note par. 0013); also upper limit and lower limit implies wherein the upper limit reference voltage is set to have a voltage level higher than that of the lower limit reference voltage
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. to include the teaching of least one reference voltage includes an upper limit reference voltage and a lower limit reference voltage, and wherein the upper limit reference voltage is set to have a voltage level higher than that of the lower limit reference voltage to provide a protection signal if there is a rise in temperature to indicate a possible abnormality. (Note par. 0013-0014).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Goh et al. (US 20090110028) in view of Pertijs et al. (US 20080069176) further in view of Kim et al. (KR 20170055676A) further in view of Wu et al. (US 20150268103).
Goh et al. teaches the instant invention except the following limitations.
Regarding claim 11, Goh et al. does not teach reference voltage includes an upper limit reference voltage and a lower limit reference voltage, and wherein the voltage code includes a first voltage code and a second voltage code, further comprising a reference voltage generating circuit configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage.
further comprising a reference voltage generating circuit configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage.
Kim et al. teach reference voltage includes an upper limit reference voltage and a lower limit reference voltage, and wherein the voltage code includes a first voltage code and a second voltage code, (Note par. 0013, upper and lower limits)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. to include the teaching of teach reference voltage includes an upper limit reference voltage and a lower limit reference voltage, and wherein the voltage code includes a first voltage code and a second voltage code to provide a protection signal if there is a rise in temperature thereby indicating an overtemperature state. (Note par. 0013-0014).
Wu et al. teach a reference voltage generating circuit (11, Fig. 1) configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage. (Note Examiner’s position is that first and second voltage codes are implicit to the calibration of the upper reference voltage and the lower reference voltage, par. 0040)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. to include the teaching of wherein the at least one reference voltage includes an upper limit reference voltage and a lower limit reference voltage, and wherein the sensor circuit further includes a reference voltage generating circuit configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage to increase the accuracy of the device through calibration.
Claim(s) 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Goh et al. (US 20090110028) in view of Hardt et al. (US 20050244263).
Regarding claim 17, Goh et al. teach An electronic device comprising:
a sensor circuit configured to compare a sensing voltage set to have a first voltage level under a first sensing condition, wherein the first sensing condition is at least one of temperature and light intensity, with at least one reference voltage to generate at least one comparison signal, (Note claim 1, comparing said thermistor voltage with a first threshold and with a second threshold) and configured to calibrate a first voltage code, based on the at least one comparison signal; (Note claim 1, adjusting said at least one of said current and said voltage supplied to said thermistor by controlling said adjustable power source based on said comparison.) and
Goh et al. does not teach a processor configured to adjust speed and activation of an internal operation, based on the first voltage code.
Hardt et al. teach a processor (microcontroller 12, par. 0022, 0027) configured to adjust speed (Note par. 0032) and activation of an internal operation (Note operation of device is terminated claim 7), based on the first voltage code .
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. to include the teaching a processor configured to adjust speed and activation of an internal operation, based on the first voltage code to maximize cooling capacity while minimizing unwanted effects such as noise and power consumption. (Note Hardt et al. par. 0016)
Regarding claim 16, Goh et al. does not teach operation control circuit configured to adjust speed and activation of an internal operation, based on the voltage code.
Hardt et al. teach operation control circuit (microcontroller 12, par. 0022, 0027) configured to adjust speed (Note par. 0032) and activation of an internal operation (Note operation of device is terminated claim 7), based on the voltage code.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. to include the teaching of operation control circuit configured to adjust speed and activation of an internal operation, based on the voltage code to maximize cooling capacity while minimizing unwanted effects such as noise and power consumption. (Note Hardt et al. par. 0016)
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Goh et al. (US 20090110028) in view of Hardt et al. (US 20050244263) in view of Wu et al. (US 20050160323) .
Goh et al. teaches the instant invention except the following limitations.
Regarding claim 18, Goh et al. does not teach wherein the sensor circuit compare the sensing voltage set to have a second voltage level under a second sensing condition with the at least one reference voltage to generate the at least one comparison signal, and configured to calibrate a second voltage code, based on the at least one comparison signal, and wherein the processor is configured to adjust the speed and activation of the internal operation, based on the second voltage code wherein the processor is configured to adjust the speed and activation of the internal operation , based on the second voltage code.
and a processor configured to adjust speed and activation of an internal operation, based on the first voltage code.
Hardt et al. teach a processor (microcontroller 12, par. 0022, 0027) configured to adjust speed (Note par. 0032) and activation of an internal operation (Note operation of device is terminated claim 7), based on the first voltage code .
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. to include the teaching a processor configured to adjust speed and activation of an internal operation, based on the first voltage code to maximize cooling capacity while minimizing unwanted effects such as noise and power consumption. (Note Hardt et al. par. 0016)
Wu et al. teach compare the sensing voltage set to have a second voltage level under a second sensing condition with the at least one reference voltage to generate the at least one comparison signal, (if the digital temperature voltage that the control unit 26 detects is higher than a temperature voltage upper limit, implying that the die of the CPU 14 has a temperature high enough to impact the operation of the CPU 14, the control unit 26 can increase the fan speed of the CPU 16 with the GPIO 36 or with the first DAC 28, or can output a control signal to simply shut down the CPU 14.) [par. 0019] and configured to calibrate a second voltage code, based on the at least one comparison signal, (if the digital temperature voltage that the control unit 26 detects is higher than a temperature voltage upper limit, implying that the die of the CPU 14 has a temperature high enough to impact the operation of the CPU 14, the control unit 26 can increase the fan speed of the CPU 16 with the GPIO 36 or with the first DAC 28, or can output a control signal to simply shut down the CPU 14.)[par. 0019]; Also note comparator used to compare temperature voltage to a temperature voltage lower limit which would also be used to compare to a temperature voltage higher limit) and wherein the processor (26, par. 0019) is configured to adjust the speed [par. 0019] and activation of the internal operation, based on the second voltage code.[Note shut off the computer, par. 0039]
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. to include the teaching of compare the sensing voltage set to have a second voltage level under a second sensing condition with the at least one reference voltage to generate the at least one comparison signal, and configured to calibrate a second voltage code, based on the at least one comparison signal, and wherein the processor is configured to adjust the speed and activation of the internal operation, based on the second voltage code to shutdown the system when temperature is too high.
Claims 23 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Goh et al. (US 20090110028) in view of Hardt et al. (US 20050244263) in view of Wu et al. (US 20050160323) further in view of Wu et al. (US 20150268103, hereafter Wu).
Goh et al. teach the instant invention except the following claim limitations.
Regarding claim 23, Goh et al. does not teach wherein the at least one reference voltage includes an upper limit reference voltage and a lower limit reference voltage, and wherein the sensor circuit further includes a reference voltage generating circuit configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage.
Wu teach wherein the at least one reference voltage includes an upper limit reference voltage and a lower limit reference voltage, (Note par, 0063) and wherein the sensor circuit further includes a reference voltage generating circuit (11, Fig. 1) configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage. (Note Examiner’s position is that firs and second voltage codes are implicit to the calibration of the upper reference voltage and the lower reference voltage, par. 0040)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. to include the teaching of wherein the at least one reference voltage includes an upper limit reference voltage and a lower limit reference voltage, and wherein the sensor circuit further includes a reference voltage generating circuit configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage to increase the accuracy of the device through calibration. (Note Wu par. 0059)
Regarding claim 27, Goh et al. does not teach the sensor circuit further includes a voltage code storage circuit configured to receive and store the first voltage code and the second voltage code.
Wu teach the sensor circuit further includes a voltage code storage circuit (Note memory par. 0059 ) configured to receive and store the first voltage code and the second voltage code.(Note memory par. 0059 and Note arrows leaving ref voltage generator labeled upper reference voltage value limit and lower reference voltage value limit are interested as first voltage code and second voltage code.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. to include the teaching of sensor circuit further includes a voltage code storage circuit configured to receive and store the first voltage code and the second voltage code to allow calibration . (Note Wu par. 0059)
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Goh et al. (US 20090110028) in view of Hsiao (US 9732758).
Goh et al. teach the instant invention except the following claim limitations.
Regarding claim 32, Goh et al. does not teach adjusting speed and activation of an internal operation, based on the first voltage code and the second voltage code.
Hsiao teach adjusting speed and activation of an internal operation (Note the enabling of signals., column 5, lines 49-52 and turning on a switch column 7, lines 15-17), based on the first voltage code and the second voltage code. (Note claim 1, first sensing and second sensing voltage signals are interpreted as voltage codes)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Goh et al. to include the teaching of adjusting speed and activation of an internal operation, based on the first voltage code and the second voltage code to control the temperature by activation of the fan. (Note abstract)
Examiner’s Note:
Claims 5-10, 12-14,19-22,24-26,29, 30-31 and stand rejected under 112(a) as outlined above. No prior art rejection has been applied to these claims because the prior art of record taken alone or in combination fails to teach the following features recited in these claims:
Claim 2, a sensing condition setting circuit configured to apply the sensing condition to the sensing voltage generating circuit, wherein the sensing condition includes temperature and light intensity.
Claim 5, wherein the at least one comparison signal includes a first comparison signal and a second comparison signal, and wherein the comparison signal generating circuit is configured to generate the first comparison signal and the second comparison signal set to have a first logic bit set when the sensing voltage has a voltage level greater than that of the upper limit reference voltage.
Claim 12, wherein the reference voltage generating circuit includes: a first analog signal generating circuit configured to convert the first voltage code into a first analog signal and to output the first analog signal; a second analog signal generating circuit configured to convert the second voltage code into a second analog signal and to output the second analog signal; and a reference voltage output circuit configured to generate the upper limit reference voltage and the lower limit reference voltage that are voltage-divided based on the first analog signal and the second analog signal.
Claim 13, wherein the reference voltage generating circuit includes: a first analog signal generating circuit configured to convert the first voltage code into a first analog signal and to output the first analog signal; a second analog signal generating circuit configured to convert the second voltage code into a second analog signal and to output the second analog signal; a reference voltage output circuit configured to generate the upper limit reference voltage and the lower limit reference voltage that are voltage-divided based on the first analog signal and the second analog signal; and a switch configured to transfer the second analog signal output from the second analog signal generating circuit to the reference voltage output circuit, based on a switching signal generated based on a sensing condition control signal.
Claim 19, wherein the at least one reference voltage includes an upper limit reference voltage and a lower limit reference voltage, wherein the upper limit reference voltage is set to have a voltage level higher than that of the lower limit reference voltage, and wherein the sensor circuit includes a comparison signal generating circuit configured to generate the first comparison signal and the second comparison signal set to have a first logic bit set when the sensing voltage has a voltage level higher than that of the upper limit reference voltage.
Claim 24, wherein the reference voltage generating circuit includes: a first analog signal generating circuit configured to convert the first voltage code into a first analog signal and to output the first analog signal; a second analog signal generating circuit configured to convert the second voltage code into a second analog signal and to output the second analog signal; and a reference voltage output circuit configured to generate the upper limit reference voltage and the lower limit reference voltage that are voltage-divided based on the first analog signal and the second analog signal.
Claim 25, wherein the reference voltage generating circuit includes: a first analog signal generating circuit configured to convert the first voltage code into a first analog signal and to output the first analog signal; a second analog signal generating circuit configured to convert the second voltage code into a second analog signal and to output the second analog signal; a reference voltage output circuit configured to generate the upper limit reference voltage and the lower limit reference voltage that are voltage-divided based on the first analog signal and the second analog signal; and a switch configured to transfer the second analog signal output from the second analog signal generating circuit to the reference voltage output circuit, based on a switching signal generated based on a sensing condition control signal.
Regarding claim 29, wherein the at least one reference voltage includes an upper limit reference voltage and a lower limit reference voltage, wherein the upper limit reference voltage is set to have a voltage level higher than that of the lower limit reference voltage, and wherein the at least one comparison signal includes a first comparison signal and a second comparison signal, further comprising generating the first comparison signal and the second comparison signal set to have a first logic bit set when the sensing voltage has a voltage level higher than that of the upper limit reference voltage, and calibrating the first voltage code and the second voltage code to increase the voltage level of each of the upper limit reference voltage and the lower limit reference voltage as claimed in combination with all other limitations of intervening and base claims.
Conclusion
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/DEMETRIUS R PRETLOW/ Examiner, Art Unit 2858
/LEE E RODAK/ Supervisory Patent Examiner, Art Unit 2858
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