DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1 and 3-32 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specification
The amendment filed 7/7/2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows:
Note par. 0003, operations, including at least one of a read operation, a write operation, and a refresh operation.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 16 and 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 16, Par. 0067, of applicant’s US PGPUB only discloses [0067] The operation control circuit 313 may receive the first voltage code VCD1, the second voltage code VCD2, the third voltage code VCD3, and the fourth voltage code VCD4 from the voltage code calibrating circuit 309. The operation control circuit 313 may adjust the speed, activation status, and the like of the internal operation, based on the first voltage code VCD1, the second voltage code VCD2, the third voltage code VCD3, and the fourth voltage code VCD4. In this embodiment, the sensor circuit 30 includes the operation control circuit 313 and is implemented to adjust the speed and activation of the internal operations, but may be implemented as a processor (423 in FIG. 18) that receives the first voltage code VCD1, the second voltage code VCD2, the third voltage code VCD3, and the fourth voltage code VCD4 from the sensor circuit 30 according to embodiments.
Applicant’s original disclosure does not provide support an operation control circuit configured to adjust speed and activation of an internal operation based on the voltage code, wherein the internal operation includes one of a read operation, a write operation, and a refresh operation and is considered new matter.
Regarding claim 17, Par. [0082] of applicant’s US PGPUB only discloses FIG. 17 is a block diagram illustrating a configuration of an electronic device 40 according to an embodiment of the present disclosure. As illustrated in FIG. 17, the electronic device 40 may include a sensor circuit 401 and a processor 403. The sensor circuit 401 may be implemented to perform a two-point internal calibration operation. The sensor circuit 401 may be implemented as the sensor circuit 10 illustrated in FIG. 1 above. The processor 403 may adjust the speed, activation status, and the line of the internal operation, based on a first voltage code VCD1 and a second voltage code VCD2.
Applicant’s original disclosure does not provide support for a processor configured to adjust speed and activation of an internal operation based on the first voltage code, wherein the internal operation includes one of a read operation, a write operation, and a refresh operation and is considered new matter.
Claims 18-27 are rejected for containing 112 rejections above and for depending on rejected base claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 4 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20170055676) in view of Gobbi (US 20160124029 ) .
Regarding claims 1 and 28, Kim et al. teach teaches a sensor circuit comprising:
a sensing voltage generating circuit configured to generate a sensing voltage at a voltage level corresponding to a sensing condition that includes at least one of temperature and light intensity (see Fig. 2 - sensing unit 21 generates a sensing voltage BJTT whose level fluctuates according to change in temperature);
a sensing condition setting circuit configured to apply the sensing condition to the sensing voltage generating circuit (see para 0005 - heat is generated by internal elements and therefore temperature sensed by sensing unit 21 is created by circuit of LEDs which are considered the claimed "condition setting circuit" configured to apply the condition);
a comparison signal generating circuit (see Fig. 1 - comparison unit 24) configured to compare the sensing voltage with two reference voltages to generate two comparison signals (see Fig. 2 - comparison unit 24 is configured to compare sensing voltage BJTT to two reference voltages, TDH_REF and TDL_REF); and
a voltage code adjusting circuit configured to adjust a voltage code (see Fig. 2 – control unit 25 adjusts a 3-bit temperature state signal TS<1:L>) to adjust a voltage level of the two reference voltages (3-bit temperature signal TS <1:L> is used by temperature range selecting section 23 to select the temperature references TDH_Ref and TDL_Ref, considered the considered two reference voltages) based on the two comparison signals (TDH and TDL from unit 24 are fed back to controller 25 to set the temperature signal TS <1:L> and subsequently reference voltages TDL_Ref and TDH_Ref).
Kim et al. teaches a 3-bit code to adjust the reference voltages as stated above, Kim et al. does not explicitly teach two voltage codes as claimed.
Gobbi teaches (Fig. 10) the use of two voltage codes to adjust a voltage level of two reference voltages (see Fig. 10 - voltage codes DEC and INC are provided to dynamic threshold generator 416b to generate thresholds DT1 and DT2 for comparison with signal S).
One of ordinary skill in the art would have recognized that two voltage codes or one multi-bit code can be considered equivalents for controlling the adjustment of threshold voltages. It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the one known element (3-bit code as taught by Kim et al.) for another known equivalent element (two voltage codes as taught by Gobbi) to achieve the predictable result of sending codes such that the thresholds can be adjusted.
Regarding claim 28, Kim et al. teach A method of performing an internal calibration operation, the method comprising:
generating a sensing voltage at a first voltage level under a first sensing condition that includes at least one of temperature and light intensity; (see Fig. 2 - sensing unit 21 generates a sensing voltage BJTT whose level fluctuates according to change in temperature)
comparing the sensing voltage with two reference voltages to generate two comparison signals; (see Fig. 2 - comparison unit 24 is configured to compare sensing voltage BJTT to two reference voltages, TDH_REF and TDL_REF);
adjusting a first voltage code based on the two comparison signals; (see Fig. 2 – control unit 25 adjusts a 3-bit temperature state signal TS<1:L>) (3-bit temperature signal TS <1:L> is used by temperature range selecting section 23 to select the temperature references TDH_Ref and TDL_Ref, considered the considered two reference voltages)
Kim et al. teaches a 3-bit code to adjust the reference voltages as stated above, Kim et al. does not explicitly teach two voltage codes as claimed.
Gobbi et al. teaches (Fig. 10) the use of two voltage codes to adjust a voltage level of two reference voltages (see Fig. 10 - voltage codes DEC and INC are provided to dynamic threshold generator 416b to generate thresholds DT1 and DT2 for comparison with signal S).
One of ordinary skill in the art would have recognized that two voltage codes or one multi-bit code can be considered equivalents for controlling the adjustment of threshold voltages. It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the one known element (3-bit code as taught by Kim et al.) for another known equivalent element (two voltage codes as taught by Gobbi) to achieve the predictable result of sending codes such that the thresholds can be adjusted.
Kim et al. in view of Gobbi et al. inherently teaches the following because the steps above are merely being performed twice. (Note Kim et al. how there are changes in response to a change in temperature and the varying of reference voltage of par. 0059 which implies performing the initial steps again when there are temperature changes)
generating the sensing voltage at a second voltage level under a second sensing condition;
comparing the sensing voltage with the two reference voltages to generate the two comparison signals; and
Note MPEP 2112.02(I) “Under the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986).”
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to repeat the steps above because it would allow more data to be collected and provide a more robust voltage code adjusting system.
Regarding claim 4, Kim et al. teach wherein the two reference voltages includes an upper limit reference voltage and a lower limit reference voltage and wherein the upper limit reference voltage is at a voltage higher level than a voltage level of the lower limit reference voltage. (Note [0041] The temperature range selection unit (23) selects at least two of the temperature reference voltages (TREF<1:k) in response to the temperature status signal (TS<1:L>) provided by the control unit (25), and provides the selected temperature reference voltages to the comparison unit (24) as upper reference voltage (TDL_REF) and lower reference voltage (TDH_REF).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20170055676) in view of Gobbi (US 20160124029 ) in view of Choi et al. (US 20070098042) .
Kim et al. teach the instant invention except the following claim limitations.
Regarding claim 3, Kim et al. does not teach wherein the sensing condition includes a first sensing condition and a second sensing condition;
wherein the sensing condition includes a first sensing condition and a second sensing condition and wherein the sensing voltage generating circuit is configured to generate the sensing voltage at a first voltage level corresponding to the first sensing condition, and to generate the sensing voltage set at a second voltage level corresponding to the second sensing condition.
Choi et al. teach wherein the sensing condition includes a first sensing condition and a second sensing condition; ([0047] The temperature detection signal generator 14 compares each of the first and second detection voltages VT1 and VT2 to the reference voltage Vref to generate first and second temperature detection signals T1_sig and T2_sig. )
wherein the sensing condition includes a first sensing condition and a second sensing condition and wherein the sensing voltage generating circuit is configured to generate the sensing voltage at a first voltage level corresponding to the first sensing condition, and to generate the sensing voltage set at a second voltage level corresponding to the second sensing condition. ([0046] The reference voltage generator 11 generates a reference voltage Vref corresponding to reference current Ir. The first detection voltage generator 12 changes a first detection current I1 to detect a first set temperature T1 according to a first temperature detection code T1_code to generate a first detection voltage VT1 corresponding to the first changed detection current I1. The second detection voltage generator 13 changes a second detection current I2 to detect a second set temperature T2 according to a second temperature detection code T2_code to generate a second detection voltage VT2 corresponding to the second changed detection current I2.)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Kim et al. to include the teaching of wherein the sensing condition includes a first sensing condition and a second sensing condition;
wherein the sensing condition includes a first sensing condition and a second sensing condition and wherein the sensing voltage generating circuit is configured to generate the sensing voltage at a first voltage level corresponding to the first sensing condition, and to generate the sensing voltage set at a second voltage level corresponding to the second sensing condition because it would create a more robust sensing circuit by utilizing multiple sensing conditions.
Claims 11 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20170055676) in view of Gobbi (US 20160124029 ) in view of Kim (US 20170147019).
Regarding claim 11, Kim et al. teach wherein the two reference voltages includes an upper limit reference voltage and a lower limit reference voltage (Note par. 0041)
Kim et al. teaches a 3-bit code to adjust the reference voltages as stated above, Kim does not explicitly teach two voltage codes as claimed.
Kim et al. does not explicitly teach
wherein the two voltage codes includes a first voltage code and a second voltage code;
further comprising a reference voltage generating circuit configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage.
Gobbi teaches (Fig. 10) the use of two voltage codes to adjust a voltage level of two reference voltages (see Fig. 10 - voltage codes DEC and INC are provided to dynamic threshold generator 416b to generate thresholds DT1 and DT2 for comparison with signal S).
One of ordinary skill in the art would have recognized that two voltage codes or one multi-bit code can be considered equivalents for controlling the adjustment of threshold voltages. It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the one known element (3-bit code as taught by Kim et al.) for another known equivalent element (two voltage codes as taught by Gobbi) to achieve the predictable result of sending codes such that the thresholds can be adjusted.
Kim teach further comprising a reference voltage generating circuit (1300, Fig. 1) configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage. (Note codes entering 1300 and par. ([0036] The reference voltage generator 1300, also described as a reference voltage generating circuit, may receive the temperature code T_CODE, the temperature coefficient T_COEF, the offset coefficient O_COEF, and the offset code O_CODE that are digital signals, and may generate the reference voltage V_REF. As described below with reference to FIG. 2, the reference voltage generator 1300 may generate the reference voltage V_REF by performing a digital calculation on the temperature code T_CODE, the temperature coefficient T_COEF, the offset coefficient O_COEF, and the offset code O_CODE. Accordingly, an error that occurs when analog signals respectively corresponding to the plurality of parameters are processed, for example, amplified, divided, added, or integrated may be removed. Also, as described below, the reference voltage generator 1300 may generate the reference voltage V_REF that is accurate by using the offset coefficient O_COEF in order to accurately compensate for an error caused by a DAC.).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Kim et al. to include the teaching of a reference voltage generating circuit configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage because it would provide a circuit and method of generating a reference voltage that accurately changes according to a temperature change. (Note par. 0005)
Regarding claim 15, Kim et al. does not teach a voltage code storage circuit configured to receive and store the voltage code.
Kim teach comprising a voltage code storage circuit (Note 1200, Fig. 1) configured to receive and store the voltage code. (Note par. 0035)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Kim to include the teaching of a voltage code storage circuit configured to receive and store the voltage code because it would provide the codes to the reference voltage generator for change the amount of the reference voltage. (Note Kim par. 0036)
Claims 16-18 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20170055676) in view of Gobbi (US 20160124029 ) further in view of Chen et al. (CN 1275117 C).
Kim et al. teach the instant invention except the following claim limitations.
Regarding claim 16, Kim et al. does not teach an operation control circuit configured to adjust speed and activation of an internal operation based on the voltage code, wherein the internal operation includes one of a read operation, a write operation, and a refresh operation.
Chen et al. teach an operation control circuit (processor of claim 1) configured to adjust speed and activation of an internal operation based on the voltage code, (Note claim 1, from the read-only memory obtains a set value for setting the processor to a first working state, said setting value having a frequency identification and voltage identification code are respectively used for controlling the processor to an operating frequency and an operating voltage) wherein the internal operation includes one of a read operation, a write operation, and a refresh operation. (Note Examiner’s position that the processor of the computer performs read operation, a write operation, and a refresh operation)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Kim et al. to include the teaching of n operation control circuit configured to adjust speed and activation of an internal operation based on the voltage code, wherein the internal operation includes one of a read operation, a write operation, and a refresh operation because it would provide the ability to adjust the processors speed to the working frequency. (Note Chen claim 8)
Regarding claim 17, Kim et al. teach a sensor circuit configured to compare a sensing voltage at a first voltage level under a first sensing condition, (see Fig. 1 - comparison unit 24) wherein the first sensing condition is at least one of temperature and light intensity,
with two reference voltages to generate two comparison signals, (see Fig. 2 - comparison unit 24 is configured to compare sensing voltage BJTT to two reference voltages, TDH_REF and TDL_REF) and configured to adjust a first voltage code based on the two comparison signals; (see Fig. 2 – control unit 25 adjusts a 3-bit temperature state signal TS<1:L>) (3-bit temperature signal TS <1:L> is used by temperature range selecting section 23 to select the temperature references TDH_Ref and TDL_Ref, considered the considered two reference voltages) and
Kim et al. does not teach a processor configured to adjust speed and activation of an internal operation based on the first voltage code, wherein the internal operation includes one of a read operation, a write operation, and a refresh operation.
Chen et al. teach a processor (processor of claim 1) configured to adjust speed and activation of an internal operation based on the first voltage code, (Note claim 1, from the read-only memory obtains a set value for setting the processor to a first working state, said setting value having a frequency identification and voltage identification code are respectively used for controlling the processor to an operating frequency and an operating voltage) wherein the internal operation includes one of a read operation, a write operation, and a refresh operation. (Note Examiner’s position that the processor of the computer performs read operation, a write operation, and a refresh operation)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Kim et al. to include the teaching of a processor configured to adjust speed and activation of an internal operation based on the first voltage code, wherein the internal operation includes one of a read operation, a write operation, and a refresh operation because it would because it would provide the ability to adjust the processors speed to the working frequency. (Note Chen claim 8)
Regarding claim 18, Kim et al. teach a sensor circuit configured to compare a sensing voltage at a second voltage level under a second sensing condition, (see Fig. 1 - comparison unit 24) wherein the second sensing condition is at least one of temperature and light intensity,
with two reference voltages to generate two comparison signals, (see Fig. 2 - comparison unit 24 is configured to compare sensing voltage BJTT to two reference voltages, TDH_REF and TDL_REF) and configured to adjust a second voltage code based on the two comparison signals; (see Fig. 2 – control unit 25 adjusts a 3-bit temperature state signal TS<1:L>) (3-bit temperature signal TS <1:L> is used by temperature range selecting section 23 to select the temperature references TDH_Ref and TDL_Ref, considered the considered two reference voltages) (Note par. 0059, whose state changes in response to a change in temperature, and varies the channel reference voltage) Examiner interprets the function of change in temperature and carrying reference voltage as implying that the system of Kim et al. uses more than one condition because the condition of Kim varies and further more the above limitations)
Kim et al. does not teach a processor configured to adjust speed and activation of an internal operation based on the first voltage code, wherein the internal operation includes one of a read operation, a write operation, and a refresh operation.
Chen et al. teach a processor (processor of claim 1) configured to adjust speed and activation of an internal operation based on the second voltage code, (Note claim 1, from the read-only memory obtains a set value for setting the processor to a first working state, said setting value having a frequency identification and voltage identification code are respectively used for controlling the processor to an operating frequency and an operating voltage) wherein the internal operation includes one of a read operation, a write operation, and a refresh operation. (Note Examiner’s position that the processor of the computer performs read operation, a write operation, and a refresh operation)
Regarding claim 32, Kim et al. as modified by Gobbi et al. first voltage code and the second voltage code.
Kim et al. does not teach adjusting speed and activation of an internal operation based on the first voltage code and the second voltage code.
Kim teach adjusting speed and activation of an internal operation based on the first voltage code and the second voltage code. (Note claim 1, from the read-only memory obtains a set value for setting the processor to a first working state, said setting value having a frequency identification and voltage identification code are respectively used for controlling the processor to an operating frequency and an operating voltage)
Claim(s) 23 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (KR 20170055676) in view of Gobbi (US 20160124029 ) further in view of Chen et al. (CN 1275117 C) further in view of Kim (US 20170147019).
Kim et al. teach the instant invention except the following claim limitations.
Regarding claim 27, Kim et al. does not teach a voltage code storage circuit configured to receive and store the voltage code.
Kim teach comprising a voltage code storage circuit (Note 1200, Fig. 1) configured to receive and store the voltage code. (Note par. 0035)
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Kim et al. to include the teaching of a voltage code storage circuit configured to receive and store the voltage code because it would provide the codes to the reference voltage generator to change the amount of the reference voltage. (Note Kim par. 0036)
Regarding claim 23, Kim et al. teach wherein the at least one two reference voltages includes an upper limit reference voltage and a lower limit reference voltage. (Note [0041] The temperature range selection unit (23) selects at least two of the temperature reference voltages (TREF<1:k) in response to the temperature status signal (TS<1:L>) provided by the control unit (25), and provides the selected temperature reference voltages to the comparison unit (24) as upper reference voltage (TDL_REF) and lower reference voltage (TDH_REF).
Kim et al. does not teach and wherein the sensor circuit further includes a reference voltage generating circuit configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage.
Kim teach further comprising a reference voltage generating circuit (1300, Fig. 1) configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage. (Note codes entering 1300 and par. ([0036] The reference voltage generator 1300, also described as a reference voltage generating circuit, may receive the temperature code T_CODE, the temperature coefficient T_COEF, the offset coefficient O_COEF, and the offset code O_CODE that are digital signals, and may generate the reference voltage V_REF. As described below with reference to FIG. 2, the reference voltage generator 1300 may generate the reference voltage V_REF by performing a digital calculation on the temperature code T_CODE, the temperature coefficient T_COEF, the offset coefficient O_COEF, and the offset code O_CODE. Accordingly, an error that occurs when analog signals respectively corresponding to the plurality of parameters are processed, for example, amplified, divided, added, or integrated may be removed. Also, as described below, the reference voltage generator 1300 may generate the reference voltage V_REF that is accurate by using the offset coefficient O_COEF in order to accurately compensate for an error caused by a DAC.).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Kim et al. to include the teaching of a reference voltage generating circuit configured to receive the first voltage code and the second voltage code to adjust a voltage level of each of the upper limit reference voltage and the lower limit reference voltage because it would provide a circuit and method of generating a reference voltage that accurately changes according to a temperature change. (Note par. 0005)
Allowable Subject Matter
Claims 5-10,12-14,19-22,24-26, 29-32 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 5, sensor circuit of wherein the two comparison signals includes a first comparison signal and a second comparison signal, and wherein the comparison signal generating circuit is configured to generate the first comparison signal and the second comparison signal including a first logic bit set when the sensing voltage is at a voltage level greater than a voltage level of the upper limit reference voltage.
Regarding claim 12, herein the reference voltage generating circuit includes: a first analog signal generating circuit configured to convert the first voltage code into a first analog signal and to output the first analog signal; a second analog signal generating circuit configured to convert the second voltage code into a second analog signal and to output the second analog signal; and a reference voltage output circuit configured to generate the upper limit reference voltage and the lower limit reference voltage that are voltage-divided based on the first analog signal and the second analog signal.
Regarding claim 19, the electronic device of wherein the two reference voltages include an upper limit reference voltage and a lower limit reference voltage wherein the upper limit reference voltage is at a voltage level higher than a voltage level of the lower limit reference voltage and wherein the sensor circuit includes a comparison signal generating circuit configured to generate the first comparison signal and the second comparison signal including a first logic bit set when the sensing voltage is at a voltage level higher than a voltage level of the upper limit reference voltage.
Regarding claim 24, wherein the reference voltage generating circuit includes: a first analog signal generating circuit configured to convert the first voltage code into a first analog signal and to output the first analog signal; a second analog signal generating circuit configured to convert the second voltage code into a second analog signal and to output the second analog signal; and a reference voltage output circuit configured to generate the upper limit reference voltage and the lower limit reference voltage that are voltage-divided based on the first analog signal and the second analog signal.
Regarding claim 29, generating the first comparison signal and the second comparison signal set to have including a first logic bit set when the sensing voltage has a voltage level higher than a voltage level of the upper limit reference voltage and calibrating adjusting the first voltage code and the second voltage code to increase the voltage level of each of the upper limit reference voltage and the lower limit reference voltage.
Prior art:
Jeong (US 20100061160) teach a reference voltage generator for generating a plurality of reference voltages each having different voltage levels in response to a self refresh enable control signal, and a voltage comparator for generating a result signal that controls a self refresh operation cycle by comparing each of the plurality of reference voltages with a temperature information voltage that represents an internal temperature of an integrated circuit.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEMETRIUS R PRETLOW whose telephone number is (571)272-3441. The examiner can normally be reached M-F, 5:30-1:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DEMETRIUS R PRETLOW/Examiner, Art Unit 2858
/LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
Prosecution Insights