Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the RCE filed on 10/23/2025.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 10/23/2025 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-16, 21, and 22 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Cottell (US Patent Application Publication US 2014/0203843 A1). Regarding claim 1, Cottell discloses (see Fig. 2) an apparatus, comprising: a transistor device (20) coupled between a first terminal (C) and a second terminal (E); a driver circuit (comprising the two transistors connected to GD_V+, GD_V-, and G via Rg) having a power terminal (top-side terminal of the two transistors) coupled to a third terminal (terminal connected to GD_V+) and an output (output coupled to G) coupled to a control terminal of the transistor device (G of 20); and a detection circuit (200) having inputs coupled to the first terminal (input coupled to C via D1, D2) and the third terminal (coupled to GD_V+ via Q1), the detection circuit configurable to provide a signal (signal output at 220) indicative of whether the transistor device is in a particular operation condition (desaturation detection) responsive to voltages of the first and third terminals (see [0035] “The desaturation detection circuit 200 comprises a threshold setting element 202 and a detector element 206. The threshold setting element 202 has an input 208 and an output 210. The input 208 is for connection to the output of a power transistor 20 (e.g. the collector of an IGBT) via the Vce sense diodes D1 and D2. The threshold setting element 202 sets the voltage at the input 208 at which the desaturation detection circuit 200 will provide an output control signal for provision to the desaturation detection input of the IC 10 to trigger a desaturation routine. The threshold setting element 202 provides an output at the output 210 of the threshold setting element 202 when the input voltage is exceeded.”). Regarding claim 2, Cottell discloses (see Fig. 2) wherein, in operation, the third terminal has a higher voltage than the second terminal (GD_V+ has a higher voltage than voltage at E, i.e. VE, as VE is a voltage in between GD_V+ and GD_V-), and a voltage at the second terminal tracks a voltage at the first terminal when the transistor device is turned on by the driver circuit (when 20 is turned on, voltage at C tracks voltage at E ). Regarding claim 3, Cottell discloses (see Fig. 2) wherein the transistor device is a first transistor device, and the detection circuit includes a second transistor device (Q1) and a third transistor device (Q2). Regarding claim 4, Cottell discloses (see Fig. 2) wherein the detection circuit includes a resistor (R6) coupled between the third terminal and the second transistor device (R6 is coupled between GD_V+ and gate of Q1). Regarding claim 5, Cottell discloses (see Fig. 2) wherein a control terminal of the second transistor device (gate of Q1) is coupled to a control terminal of the third transistor device (gate of Q2) (gate of Q1 is coupled to gate of Q2 via R7, D5, R9, and R4). Regarding claim 6, Cottell discloses (see Fig. 2) wherein the third transistor device is coupled between the first terminal and the second transistor device (Q2 is coupled between Q1 and C via D5, R9, and R4). Regarding claim 7, Cottell discloses (see Fig. 2) wherein a control terminal of the second transistor device (gate of Q1) and a control terminal of the third transistor device (gate of Q2) are each coupled to the third terminal (gate of Q1 is coupled to GD_V+ via R6, gate of Q2 is coupled to GD_V+ via R4, R9, D5, R7, and R6). Regarding claim 8, Cottell discloses (see Fig. 2) further comprising a logic circuit (10) coupled to an output of the detection circuit (220), the logic circuit configurable to turn off the transistor device responsive to the signal (see [0052] “When the IGBT is pulled out of saturation due to a short circuit fault and into desaturation, Q1 and Q2 turn off quickly, which then allows the Desat input (pin 14) of the IC to charge to its internally set threshold trip level via R1 and a soft turn-off is then initiated by the IC.”). Regarding claim 9, Cottell discloses (see Fig. 2) an apparatus, comprising: an input voltage rail (voltage at C of 20); a bootstrapped voltage rail (GD_V+); a switch (20) coupled between the input voltage rail and a switching terminal (terminal of E of 20), the switch including a transistor device (IGBT of 20): and a detection circuit (200) having inputs coupled to the bootstrapped voltage rail and the input voltage rail (input coupled to GD_V+ via top-side of Q1, and input coupled to voltage at C of 20 via D1, D2), the detection circuit configurable to provide a signal indicative of whether the transistor device is in a particular operation mode (see [0035] “The desaturation detection circuit 200 comprises a threshold setting element 202 and a detector element 206. The threshold setting element 202 has an input 208 and an output 210. The input 208 is for connection to the output of a power transistor 20 (e.g. the collector of an IGBT) via the Vce sense diodes D1 and D2. The threshold setting element 202 sets the voltage at the input 208 at which the desaturation detection circuit 200 will provide an output control signal for provision to the desaturation detection input of the IC 10 to trigger a desaturation routine. The threshold setting element 202 provides an output at the output 210 of the threshold setting element 202 when the input voltage is exceeded.”). Regarding claim 10, Cottell discloses (see Fig. 2) wherein in operation, the bootstrapped voltage rail has a higher voltage than the input voltage rail (GD_V+ has a higher voltage than voltage at E, i.e. VE, as VE is a voltage in between GD_V+ and GD_V-). Regarding claim 11, Cottell discloses (see Fig. 2) further comprising: a driver circuit (comprising the two transistors connected to GD_V+, GD_V-, and G via Rg) having a power terminal (top-side terminal of the two transistors) coupled to the bootstrapped voltage rail and an output (output coupled to G) coupled to a control terminal of the switch (G of 20) and a capacitor coupled between the bootstrapped voltage rail and the switching terminal (see capacitor coupled between GD_V+ and terminal of E). Regarding claim 12, Cottell discloses (see Fig. 2) wherein the transistor device is a first transistor device, and the detection circuit includes a second transistor device (Q1) and a third transistor device (Q2). Regarding claim 13, Cottell discloses (see Fig. 2) wherein the detection circuit includes a resistor (R6) coupled between the bootstrapped voltage rail and the second transistor device (R6 is coupled between GD_V+ and gate of Q1). Regarding claim 14, Cottell discloses (see Fig. 2) wherein a control terminal of the second transistor device (gate of Q1) is coupled to a control terminal of the third transistor device (gate of Q2) (gate of Q1 is coupled to gate of Q2 via R7, D5, R9, and R4). Regarding claim 15, Cottell discloses (see Fig. 2) wherein the third transistor device is coupled between the input voltage rail and the second transistor device (Q2 is coupled between Q1 and C via D5, R9, and R4). Regarding claim 16, Cottell discloses (see Fig. 2) wherein a control terminal of the second transistor device (gate of Q1) and a control terminal of the third transistor device (gate of Q2) are each coupled to the bootstrapped voltage rail (gate of Q1 is coupled to GD_V+ via R6, gate of Q2 is coupled to GD_V+ via R4, R9, D5, R7, and R6). Regarding claim 21, Cottell discloses (see Fig. 2) wherein the particular operation condition is a saturation operation condition (see [0052] “When the IGBT is pulled out of saturation due to a short circuit fault and into desaturation, Q1 and Q2 turn off quickly, which then allows the Desat input (pin 14) of the IC to charge to its internally set threshold trip level via R1 and a soft turn-off is then initiated by the IC.”).. Regarding claim 22, Cottell discloses (see Fig. 2) wherein the second and third transistor devices are of opposite types (Q1 is a PNP transistor and Q2 is a PNP transistor).
Allowable Subject Matter
Claims 17-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 17, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “a first field effect transistor (FET) device coupled between an input voltage rail and a first voltage terminal; a second FET device having a drain terminal, a source terminal, and a gate terminal, the gate terminal coupled to a second voltage terminal; a third FET device having a drain terminal coupled to the input voltage rail, a source terminal coupled to the source terminal of the second FET device, and a gate terminal coupled to the second voltage terminal; and a fourth FET device having a gate terminal coupled to the drain terminal of the second FET device and having a source terminal coupled to the second voltage terminal.”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Patent Application Publication 2009/0153223 A1 discloses an IGBT-driver circuit for desaturated turn-off with high desaturation level. US Patent Application Publication 2014/0118874 A1 discloses a gate driver with desaturation detection. US Patent Application Publication 2018/0183228 A1 discloses a gate driver with desaturation detection.
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/JYE-JUNE LEE/Examiner, Art Unit 2838
/JUE ZHANG/Primary Examiner, Art Unit 2838