Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed on 05/13/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 9, 10, 11, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Jodka et al. (US Patent US 10,673,337 B1, hereinafter “Jodka”) in view of Gerna et al. (US Patent Application Publication US 2017/0010316 A1, hereinafter “Gerna”). Regarding claim 1, Jodka discloses (see Fig. 1) an apparatus comprising: a transistor device (high-side NMOS power transistor Mhs) coupled between a first terminal (the output voltage Vout node coupled to the drain of Mhs) and a second terminal (switch-node SW coupled to the source of Mhs); and a driver circuit (high-side gate-driver 102) having a power terminal (high-side terminal of 102) coupled to a third terminal (bootstrap voltage Vboot at the top-side terminal of bootstrap capacitor Cboot) and an output coupled to a control terminal (gate) of the transistor device (see col. 6, gate-driver 102 supplied by Vboot provides a control signal to the gate of Mhs).
Jodka does not disclose a detection circuit having inputs coupled to the first terminal and the third terminal, the detection circuit configurable to provide a signal indicating that the transistor device enters or is in a saturation operation condition based on voltages of the first and third terminals.
However, Gerna teaches (see Fig. 7) a detection circuit (a saturation detector 700 comprising a second transistor device 20 and current detection circuitry including a current source 50 or resistor 55 and an inverter 60) that provides a signal indicating whether a transistor device (first transistor device 10) is in a saturation operation condition based on a voltage at a first terminal (drain terminal of the transistor device 20) and a voltage at a third terminal (gate-drive voltage of the transistor device; see [0004] “a MOS transistor is in saturation when VDS > VGS − VTH”; see also [0031]-[0032] and [0044]-[0045]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Jodka to include the detection circuit of Gerna, because it provides knowledge of whether the high-side power transistor is operating in its saturation region throughout the full operation range of the transistor and without perturbing the transistor when it operates in the linear region (see [0011]-[0012] of Gerna).
Regarding claim 2, Jodka discloses (see Fig. 1) wherein, in operation, the third terminal (Vboot) has a higher voltage than the second terminal (SW) (see col. 8 “Vboot reaches a value greater than the switch-node voltage Vsw by Vdd”), and a voltage at the second terminal (Vsw) tracks a voltage at the first terminal (Vout) when the transistor device is turned on by the driver circuit (see col. 4 “switch-node SW is connected to Vout when Mhs is on”).
Regarding claim 9, Jodka discloses (see Fig. 1) an apparatus comprising: an input voltage rail (the output voltage Vout node coupled to the drain of high-side transistor Mhs); a bootstrapped voltage rail (bootstrap voltage Vboot); and a switch (high-side NMOS power transistor Mhs) coupled between the input voltage rail and a switching terminal (switch-node SW), the switch including a transistor device (Mhs). Jodka does not disclose a detection circuit having inputs coupled to the bootstrapped voltage rail and the input voltage rail, the detection circuit configurable to provide a signal indicating that the transistor device enters or is in a saturation operation mode.
However, Gerna teaches (see Fig. 7) a detection circuit (a saturation detector comprising a second transistor device 20 and current detection circuitry 50/55, 60) that provides a signal indicating whether a transistor device (first transistor device 10) is in a saturation operation mode based on the voltage at the drain (input voltage rail) of the transistor device and the gate-drive voltage (bootstrapped voltage rail) of the transistor device (see [0004], [0031]-[0032], and [0044]-[0045]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Jodka to include the detection circuit of Gerna, because it provides knowledge of whether the high-side power transistor is operating in its saturation region throughout the full operation range of the transistor and without perturbing the transistor when it operates in the linear region (see [0011]-[0012] of Gerna).
Regarding claim 10, Jodka discloses (see Fig. 1) wherein in operation, the bootstrapped voltage rail (Vboot, approximately 15 V) has a higher voltage than the input voltage rail (Vout, approximately 10 V) (see col. 6 “Vsw rises to near 10 volts and Vboot rises to near 15 volts”).
Regarding claim 11, Jodka discloses (see Fig. 1) further comprising: a driver circuit (high-side gate-driver 102) having a power terminal coupled to the bootstrapped voltage rail (Vboot) and an output coupled to a control terminal (gate) of the switch (Mhs); and a capacitor (bootstrap capacitor Cboot) coupled between the bootstrapped voltage rail (Vboot, the first terminal of Cboot) and the switching terminal (switch-node SW, the second terminal of Cboot) (see col. 6).
Regarding claim 21, Jodka discloses (see Fig. 1) wherein the third terminal is coupled to a bootstrapped voltage rail (the third terminal, i.e., the power terminal of high-side gate-driver 102, is coupled to bootstrap voltage Vboot).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jodka in view of Gerna, and further in view of Lalithambika et al. (US Patent Application Publication US 2007/0200590 A1, hereinafter “Lalithambika”). Regarding claim 8, Jodka does not disclose a logic circuit coupled to an output of the detection circuit, the logic circuit configurable to turn off the transistor device responsive to the signal.
However, Lalithambika teaches (see Fig. 2) a logic circuit (controller 204) coupled to an output (comparator 232 output 234) of a detection circuit and configurable to turn off a transistor device responsive to the signal (see [0045] “the controller can turn the power device off by pulling the gate-drive low” when the on-state voltage exceeds the threshold).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Jodka to include the logic circuit of Lalithambika, because turning off the transistor device in response to the detected saturation protects the device from the power losses that can damage or destroy it during saturation (see [0011] of Lalithambika).
Allowable Subject Matter
Claims 17-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 17, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “a first field effect transistor (FET) device coupled between an input voltage rail and a first voltage terminal; a second FET device having a drain terminal, a source terminal, and a gate terminal, the gate terminal coupled to a second voltage terminal; a third FET device having a drain terminal coupled to the input voltage rail, a source terminal coupled to the source terminal of the second FET device, and a gate terminal coupled to the second voltage terminal; and a fourth FET device having a gate terminal coupled to the drain terminal of the second FET device and having a source terminal coupled to the second voltage terminal.”.
Claims 3-7, 12-16, and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 3, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “…the detection circuit includes a second transistor device and a third transistor device coupled between the third terminal and the first terminal.”. Claims 4-7, and 22 are objected due to their dependency on claim 3. Regarding Claim 12, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “…the detection circuit includes a second transistor device and a third transistor device coupled in series between the bootstrapped voltage rail and the input voltage rail.”. Claims 13-16 are objected due to their dependency on claim 12.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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/JYE-JUNE LEE/Examiner, Art Unit 2838
/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
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