DETAILED ACTION
Claims 1 and 3-20 are pending in this application.
Claims 13 and 18 are objected to.
Claims 1, 3-12, 14-17 and 19-20 are rejected.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/28/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa et al. (U.S. PGPub No. 2017/0249002) in view of Agarwal et al. (U.S. PGPub No. 2024/0205127).
Claim 1
Costa (2017/0249002) teaches:
An apparatus, the apparatus comprising interface circuitry, machine-readable instructions, and a semiconductor die comprising processing circuitry to execute the machine-readable instructions to: P. 0007 system-on-a-chip (SoC) device includes a processor and on-chip memory
obtain data associated with the processing circuitry; and P. 0021 SoC state information 106 can include data copied from registers of the processor 102; P. 0025 metadata 108 can also include indicators to resume the system to specific states
store the data in non-volatile memory integrated into the semiconductor die, P. 0014 on-chip non-volatile memory can store metadata that relates to the SoC device; P. 0019 non-volatile memory 104 can store SoC state information 108 and metadata 108
Costa does not explicitly teach the data indicating a usage of the processing circuitry.
Agarwal (2024/0205127) teaches:
wherein the data associated with the processing circuitry is data indicating at least one of cumulative usage time of the processing circuitry, how often the processing circuitry has been used at an elevated temperature, a life expectancy of the processing circuitry, provenance of the processing circuitry, a deployment model of the processing circuitry, a recorded failure of the processing circuitry, or recorded malfunction of the processing circuitry. P. 0207 the first set of metrics includes metrics regarding total CPU cycles, idle cycles, and busy cycles. the aggregation criteria computes the average usage percentage, the top used core, the mean usage of a core, the lifetime sum, and/or an aggregate value from the raw metrics
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Costa with the data indicating a usage of the processing circuitry taught by Agarwal.
The motivation being to present to a user a composite component's health score and information(see Agarwal P. 0152)
The systems of Costa and Agarwal are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Costa with Agarwal to obtain the invention as recited in claims 1, 3-14.
Claim 3
Agarwal (2024/0205127) teaches:
The apparatus of claim 1, wherein the machine-readable instructions further comprise machine-readable instructions to determine the data by monitoring a usage of the processing circuitry. P. 0099 metrics for the data plane 330 include metrics of its CPU, which are maintained and collected by the OS
Claim 4
Costa (2017/0249002) teaches:
The apparatus of claim 1, wherein the machine-readable instructions further comprise machine-readable instructions to tag the data as not to be erased from the non-volatile memory. P. 0063 metadata 108 and 304 in on-chip non-volatile memory 104 are write protected to prevent unauthorized modification of the metadata
Claim 19
Costa (2017/0249002) teaches:
A method, comprising:
obtaining data associated with processing circuitry; and P. 0021 SoC state information 106 can include data copied from registers of the processor 102; P. 0025 metadata 108 can also include indicators to resume the system to specific states
storing the data in non-volatile memory integrated into a semiconductor die comprising the processing circuitry, P. 0014 on-chip non-volatile memory can metadata that relates to the SoC device; P. 0019 non-volatile memory 104 can store SoC state information 108 and metadata 108
Costa does not explicitly teach the data indicating a usage of the processing circuitry.
Agarwal (2024/0205127) teaches:
wherein the data associated with the processing circuitry is data indicating at least one of cumulative usage time of the processing circuitry, how often the processing circuitry has been used at an elevated temperature, a life expectancy of the processing circuitry, provenance of the processing circuitry, a deployment model of the processing circuitry, a recorded failure of the processing circuitry, or recorded malfunction of the processing circuitry. P. 0207 the first set of metrics includes metrics regarding total CPU cycles, idle cycles, and busy cycles. the aggregation criteria computes the average usage percentage, the top used core, the mean usage of a core, the lifetime sum, and/or an aggregate value from the raw metrics
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Costa with the data indicating a usage of the processing circuitry taught by Agarwal.
The motivation being to present to a user a composite component's health score and information(see Agarwal P. 0152)
The systems of Costa and Agarwal are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Costa with Agarwal to obtain the invention as recited in claims 19-20.
Claim 20
Costa (2017/0249002) teaches:
A non-transitory machine-readable storage medium including program code, when executed, to cause a machine to perform the method of claim 19. P. 0013 the on-chip non-volatile memory can store boot instructions that are executed by the SoC device to perform the resuming of the SoC device
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa et al. (U.S. PGPub No. 2017/0249002) in view of Agarwal et al. (U.S. PGPub No. 2024/0205127) in view of Tayeb et al. (U.S. PGPub No. 2019/0121652).
Claim 10
The systems of Costa and Agarwal do not explicitly teach storing the data in a trusted environment.
Tayeb (2019/0121652) teaches:
The apparatus of claim 1, wherein the machine-readable instructions further comprise machine-readable instructions to determine the data and store the data within a trusted execution environment implemented in the semiconductor die. P. 0022 CPU 100 can be formed in a semiconductor die that includes at least processor 102 and tuning engine 104, activity data of processors 102 can be stored by tuning agent 104 in a secure memory region, secure memory region can be implemented in a secure enclave
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Costa and Agarwal with storing the data in a trusted environment taught by Tayeb
The motivation being to limit input/output access to specific devices or agents or with proper authentication credentials (see Tayeb P. 0022)
The systems of Costa, Agarwal and Tayeb are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Costa and Agarwal with Tayeb to obtain the invention as recited in claim 10.
Claim(s) 5-6 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa et al. (U.S. PGPub No. 2017/0249002) in view of Agarwal et al. (U.S. PGPub No. 2024/0205127) in view of Choi et al. (U.S. Patent No. 5809553)
Claim 5
The systems of Costa and Agarwal do not teach erasing data that is not tagged as “not to be erased” in response to an erase request.
Choi (5809553) teaches:
The apparatus of claim 4, wherein the machine-readable instructions further comprise machine-readable instructions to, in response to a request for data erasure, erase further data from the non-volatile memory, wherein the further data is different from the data tagged as not to be erased. Col. 3 line 58 – Col. 4 line 19 Upon receiving an address to be programmed (it would be obvious to a POSITA that a program operation of all 0’s is analogous to an erase operation), the lockable cell of the selected word line corresponding to the address is read to determine the lock status. If the lockable cell is storing a “1”, the cells of the word line are not erase locked and can be erased (block 58)
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Costa and Agarwal with erasing data that is not tagged as “not to be erased” in response to an erase request taught by Choi
The motivation being the user often desires that memory cells should not be erased or programmed, in order to protect the data which is stored therein (see Choi Col. 1 line 12-18)
The systems of Costa, Agarwal and Choi are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Costa and Agarwal with Choi to obtain the invention as recited in claims 5-6.
Claim 6
Choi (5809553) teaches:
The apparatus of claim 5, wherein the machine-readable instructions further comprise machine-readable instructions to: tag the further data as to be erased from the non-volatile memory; and Col. 6 line 4-35 command control circuit 15 receives an address to be unlocked, voltage control circuit 14 applies the ground voltage Vss to the lockable cell of the word line corresponding to the address, therefore unlocking the normal cells of the corresponding word line
in response to a request for data erasure, exclusively erase the tagged further data from the non-volatile memory. Col. 4 lines 8-19 if the lockable cell of a selected word line is programmed to 1, the normal cells of the selected word line are not erase-locked and can be erased
Claim 12
The systems of Costa and Agarwal do not explicitly teach receiving a policy for exposing data, and exposing the data based on the policy.
Choi (5809553) teaches:
The apparatus of claim 1, wherein the machine-readable instructions further comprise machine-readable instructions to: receive a policy for exposing the data; and Col. 6 line 4-35 command control circuit 15 receives an address to be unlocked [analogous to a policy], voltage control circuit 14 applies the ground voltage Vss to the lockable cell of the word line corresponding to the address, therefore unlocking the normal cells of the corresponding word line
in response to a request for exposing the data, expose the data based on the received policy. Col. 4 lines 8-19 if the lockable cell of a selected word line is programmed to 1, the normal cells of the selected word line are not erase-locked and can be erased
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Costa and Agarwal with receiving a policy for exposing data, and exposing the data based on the policy taught by Choi
The motivation being the user often desires that memory cells should not be erased or programmed, in order to protect the data which is stored therein (see Choi Col. 1 line 12-18)
The systems of Costa, Agarwal and Choi are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Costa and Agarwal with Choi to obtain the invention as recited in claim 12.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa et al. (U.S. PGPub No. 2017/0249002) in view of Agarwal et al. (U.S. PGPub No. 2024/0205127) in view of Choi et al. (U.S. Patent No. 5809553) in view of Jean et al. (U.S. Patent No. 11023164)
Claim 7
The systems of Costa, Agarwal and Choi do not explicitly teach storing data tagged as “not to be erased” in a contiguous memory region.
Jean (11023164) teaches:
The apparatus of claim 6, wherein the machine-readable instructions further comprise machine-readable instructions to store the tagged further data in a contiguous memory region of the non-volatile memory. Col. 20 lines 52-57 maintain the tagged identified data contiguously on the group of non-volatile memory cells during garbage collection
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Costa, Agarwal and Choi with storing data tagged as “not to be erased” in a contiguous memory region taught by Jean
The motivation being to take advantage of efficient, high-speed data transfer from contiguous locations of the storage system (See Jean Col. 3 lines 38-61)
The systems of Costa, Agarwal and Choi and Jean are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Costa, Agarwal and Choi with Jean to obtain the invention as recited in claim 7.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa et al. (U.S. PGPub No. 2017/0249002) in view of Agarwal et al. (U.S. PGPub No. 2024/0205127) in view of Choi et al. (U.S. Patent No. 5809553) in view of Horii et al. (U.S. PGPub No. 2004/0210729)
Claim 8
The systems of Costa, Agarwal and Choi do not explicitly teach a policy indicating whether erasure is to be performed in an interleaved or simultaneous manner.
Horii (2004/0210729) teaches:
The apparatus of claim 5, wherein the machine-readable instructions further comprise machine-readable instruction to: receive a policy indicating whether the data erasure is to be performed in at least one of an interleaved and a simultaneous manner; and erase the further data based on the policy. P. 0025 control unit determines, for an instruction of an erase operation, whether to perform the operation interleaved, or perform the in parallel, according to whether only one memory bank or a plurality of memory banks are designated [difference in command format analogous to a policy]
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Costa, Agarwal and Choi with the policy indicating whether erasure is to be performed in an interleaved or simultaneous manner taught by Horii
The motivation being to reduce the duration of the busy state due to an erase operation (See Horii P. 0005)
The systems of Costa, Agarwal, Choi and Horii are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Costa and Choi with Horii to obtain the invention as recited in claim 8.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa et al. (U.S. PGPub No. 2017/0249002) in view of Agarwal et al. (U.S. PGPub No. 2024/0205127) in view of Choi et al. (U.S. Patent No. 5809553) in view of Russo et al. (U.S. PGPub No. 2012/0023303)
Claim 9
The systems of Costa, Agarwal and Choi do not explicitly teach storing the progress of a data erasure operation.
Russo (2012/0023303) teaches:
The apparatus of claim 5, wherein the machine-readable instructions further comprise machine-readable instructions to store an indication of a progress of the data erasure in the non-volatile memory. P. 0023 control field 200 also includes a status section 206, which can be used to indicate an approximation of the percent of the secure erase operation that remains until completion
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Costa, Agarwal and Choi with storing the progress of a data erasure operation taught by Russo
The motivation being to convert percentile values into total time involved to complete the requested operation and amount of time left for the full completion (See Russo P. 0023)
The systems of Costa, Agarwal, Choi and Russo are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Costa and Choi with Russo to obtain the invention as recited in claim 9.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa et al. (U.S. PGPub No. 2017/0249002) in view of Agarwal et al. (U.S. PGPub No. 2024/0205127) in view of Seo et al. (U.S. Patent No. 10424346)
Claim 11
The systems of Costa and Agarwal do not explicitly teach sending and receiving data using NVMe.
Seo (10424346) teaches:
The apparatus of claim 1, wherein the machine-readable instructions further comprise machine-readable instructions to send or receive the data based on a non-volatile memory express, NVMe, protocol. Col. 15 lines 32-42 processing device 4100 and the electronic devices 4300, 4400, . . . , 4800, 4900 may various interface protocols such as NVMe
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Costa with sending and receiving data using NVMe taught by Seo
The motivation being it is a well-known storage protocol.
The systems of Costa and Seo are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Costa with Seo to obtain the invention as recited in claim 11.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa et al. (U.S. PGPub No. 2017/0249002) in view of Agarwal et al. (U.S. PGPub No. 2024/0205127) in view of Kursun et al. (U.S. PGPub No. 2011/0271141)
Claim 14
The systems of Costa and Agarwal do not explicitly teach the machine readable instructions being microcode (to be executed by a microprocessor).
Kursun (2011/0271141) teaches:
The apparatus of claim 1, further comprising microcode memory integrated into the semiconductor die, wherein the microcode memory is to store the machine-readable instructions. P. 0007 system-on-a-chip (SoC) device includes a processor and on-chip memory; P. 0080 operation outlined in FIG. 5 may be implemented in hardware of a microprocessor chip
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Costa with the machine readable instructions being microcode (to be executed by a microprocessor) taught by Kursun
The motivation being microprocessors are a well-known type of hardware that is frequently used in the technology.
The systems of Costa and Kursun are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Costa with Kursun to obtain the invention as recited in claim 14.
Claim(s) 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Costa et al. (U.S. PGPub No. 2017/0249002) in view of Agarwal et al. (U.S. PGPub No. 2024/0205127) in view of Vaidya et al. (U.S. PGPub No. 2023/0297485)
Claim 15
The systems of Costa and Agarwal do not explicitly teach an apparatus comprising an interface and instructions executed by a processor to send an erase request.
Vaidya (2023/0297485) teaches:
An apparatus, the apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to send a request for data erasure to an apparatus according to claim 1. P. 0071 The parallel processing unit (PPU) 202 performs a write operation to a trigger block register to cause the trigger block to transmit a flush request; P. 0033 and FIG. 2 PPU 202 includes Memory interface 214; P. 0038 the general processing cluster (GPC) 208 in PPU 202 executes instructions
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Costa with the apparatus comprising an interface and instructions executed by a processor to send an erase request taught by Vaidya
The motivation being to allow multiple applications to execute serially and share the same physical hardware resources over time (see Vaidya P. 0068)
The systems of Costa and Vaidya are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Costa with Vaidya to obtain the invention as recited in claims 15-17.
Claim 16
Vaidya (2023/0297485) teaches:
The apparatus of claim 15, wherein the machine-readable instructions further comprise machine-readable instructions to send the request for data erasure in response to a request for ownership transfer. P. 0074 the performance monitoring subsystem 250 flushes out and saves to memory the performance monitoring data for the context switching
Claim 17
Vaidya (2023/0297485) teaches:
The apparatus of claim 15, wherein the machine-readable instructions further comprise machine-readable instructions to: send a policy for exposing data associated with a processing circuitry of the apparatus according to claim 1; and store the exposed data based on the policy. P. 0071 The parallel processing unit (PPU) 202 performs a write operation to a trigger block register [sending a policy] to cause the trigger block to transmit a flush request; P. 0074 the performance monitoring subsystem 250 flushes out and saves to memory the performance monitoring data for the context switching out
Allowable Subject Matter
Claims 13 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 13 recites the limitation “wherein the machine-readable instructions further comprise machine-readable instructions to expose the data by storing the data on a distributed ledger.”
Said limitation is taught by the specification of the instant application as originally filed at least at [Page 11 lines 19-24]. Said limitations, in combination with the other recited limitations of claim 13, are not taught or suggested by the prior art of record.
The closest prior art of record includes Choi et al. (U.S. Patent No. 5809553) which teaches tagging data with a “1” bit to unlock the data and allow it to be erased from memory; and Vaidya et al. (U.S. PGPub No. 2023/0297485) which teaches flushing performance monitoring data to a memory during context switching. None of the references teach tagging data to be erase-unlocked resulting in the data being stored in a distributed ledger.
Claim 18 contains similar limitations to claim 13, and is considered allowable for at least the same reasons as claim 13.
Response to Arguments
Applicant's arguments filed 9/2/2025 have been fully considered but they are not persuasive.
The applicant states on page 4: “Agarwal discloses collecting metrics regarding total CPU cycles and computing a lifetime sum from the raw data. However, the total CPU cycles and lifetime sum are not equivalent to the cumulative usage time of the processing circuitry. The total CPU cycles or lifetime sum are cycle counts, not elapsed-time values. In order to convert the CPU cycles to a time value, it would require the clock-frequency knowledge of the CPU. The clock frequency of a CPU is not fixed but varies dynamically depending on several factors, such as load, temperature, performance requirements, operating state, etc. Therefore, the CPU clock cycles or a lifetime sum thereof alone cannot determine the cumulative usage time of the processing circuitry. Agarwal has no disclosure about converting the CPU cycles to a time value.”
The examiner respectfully notes Agarwal P. 0066 states “one client application can require that all metrics be averaged over a specific time period”. P. 0018 states “operational data aggregator presents a set of one or more time controls in a UI to allow a user to specify a time period for which the user requests to view the metric data”, and P. 0105 states “metrics manager 620 may store these metrics in a local memory until an aggregation timer fires”. Based on this, it would be obvious to a person of ordinary skill in the art Agrawal teaches a executing machine-readable instructions to obtain a cumulative usage time of the processing circuitry. Further, P. 0105 states “the metrics manager 620 may aggregate five-minute metrics up to one-hour metrics, and then one-hour metrics up to one day”. A person of ordinary skill in the art that the metrics manager is able to track a cumulative usage time of a processing unit.
Applicant's arguments filed 9/2/2025 have been fully considered but they are not persuasive.
The applicant states on page 5: “The problems and solutions of Costa and Agarwal are completely different. Agarwal discloses collecting and storing the total cycles, idle cycles, and busy cycles of CPU for monitoring the performance of the network elements. Costa stores the SoC state information (that is copied from the registers of the processor and a cache) in the non-volatile memory to use in resuming the system to a prior state. There is no teaching to store the total cycles, idle cycles, and busy cycles of CPU or a lifetime sum thereof in a non-volatile memory to resume the CPU to a prior state. The Examiner's argument is a piece-meal argument. The total cycles, idle cycles, and busy cycles of CPU or a lifetime sum thereof is not the information that is needed to restore the system to a prior state“
The examiner respectfully notes the purpose for which metrics of a processor are collected do not prevent the combination of two different methods for collecting processor metrics. Adding the instructions for collecting CPU metrics taught by Agarwal could be easily included in instructions for obtaining metadata from an SoC (which includes a processor) taught by Costa, as both Agarwal and Costa teach systems with similar components. Even if Costa does not explicitly state metadata includes processor specific metrics, the processor is necessary for operation of the SoC, so metadata such as an indicator for whether the SoC device is to be resumed or booted (P. 0025) inherently involves the processor. Including the CPU metrics of Agarwal into the SoC of Costa
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tanaka et al. (U.S. PGPub No. 2006/0164886) teaches executing an erase command on a memory block when the protect flag has a first value, and not executing the erase command when the protect flag has a second value.
Ngai et al. (U.S. PGPub No. 2005/0086263) recording database performance statistics to a memory module, where the statistics include processor usage time.
Srinivasan et al. (U.S. PGPub No. 2019/0205150) teaches utilization data, including processor activity, being stored on memory resources, and cleansing the utilization data.
Kodalapura et al. (U.S. PGPub No. 2019/0132115) teaches monitoring processes of processing circuitry, and a monitor memory stored on the same die as the processing circuitry.
Varma et al. (U.S. PGPub No. 2014/0006761) teaches storing different processor frequency settings for a number of different configurations, and acquiring the frequency settings and writing them to on-die non-volatile storage.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHANIE WU whose telephone number is (571)272-0257. The examiner can normally be reached 1pm to 6pm, and 10pm to 1am Eastern time (10am to 3pm, and 7pm to 10pm Pacific time).
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/STEPHANIE WU/Primary Examiner, Art Unit 2133