DETAILED ACTION
This action is responsive to the communication filed on 14 January 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Election/Restrictions
Applicant’s election without traverse of the Species III embodiment in the reply filed on 14 September 2025 is acknowledged.
Regarding Applicant’s listing of claims 1-20 as readable on the elected species, however, the Examiner respectfully notes that claims 8 and 20 do not belong to the elected Species III embodiment. Each of claim 8 and 20 recite the limitation “and both of an orthographic projection of the first channel sub-portion on the base and an orthographic projection of the second channel sub-portion on the base are within an orthographic projection of the light-shielding layer on the base,” depicted in FIG. 2. Applicant' s elected Species III embodiment is depicted in FIG. 4, however, which does not depict wherein the orthographic projections of the first and second channel sub-portions are within the orthographic projection of the light shielding portion.
Accordingly, claims 8 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim.
Response to Arguments
Applicant's arguments filed 14 January 2025 have been fully considered but they are not persuasive.
Applicant states:
That is, Chung aims to reduce interlayer interference and parasitic effects by vertically stacking transistors (the first TFT and the second TFT) in different layers and incorporating planarization layers and a shielding electrode (400), ensuring that the upper-layer transistor is unaffected by voltage fluctuations from the lower layer transistor. Therefore, the key to achieving this objective lies in Chung’s design of heterolayer source and drain electrodes separated by the shielding electrode 400.
Although Cha discloses source and drain electrodes disposed on layer IL5, forcibly applying Cha’s same-layer source and drain electrodes to Chung would render Chung’s display panel inoperable.
Applicant Arguments/Remarks Made in an Amendment (filed 14 January 2026) at 2-3. To the extent Applicant argues against the combination of Chung and Cha, the Examiner respectfully notes that Cha is cited twice in the Non-Final Rejection, once in the rejection of independent claim 1 and again in the rejection of independent claim 13. See Non-Final Rejection (mailed 22 October 2025) at 5-11. Cha is cited in the same way for the same reasons in each instance:
Chung does not specifically disclose wherein the second transistor comprises a second active portion made of a metal oxide material.
In the same field of endeavor, Cha discloses a transistor including an active layer formed from an oxide semiconductor material including metal oxides (FIG. 3, [0091]: “The driving active pattern 320 a and the second active layer 350 b and 350 c may be formed of polysilicon or an oxide semiconductor. The oxide semiconductor may include oxides based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In).”)
Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select a known active layer material such as one including a metal oxide, as shown by Cha in [0091], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose a metal oxide active layer material over other materials depending on manufacturing considerations such as cost of materials or time it takes to process the layer.
Id. The Non-Final Rejection clearly combines Chung and Cha in a manner supported by well-established legal principles and case law. The Examiner respectfully notes that the citation and combination of Chung and Cha appearing in the Non-Final Rejection is entirely different than the combination contemplated (and argued against) by Applicant’s remarks, which appears to be based on a misunderstanding of the manner in which the references were combined—reinforced by other portions of Applicant’s remarks. See, e.g., Applicant Arguments/Remarks Made in an Amendment (filed 14 January 2026) at 2-3 (stating “Inagaki is silent on the arrangement of any transistor.”). But see Non-Final Rejection (mailed 22 October 2025) at 11-21 (citing Inagaki several times regarding transistor configurations).
Accordingly Applicant’s arguments unpersuasive.
Claim Rejections - 35 USC § 112
The § 112(b) rejection of claim 12 is withdrawn, responsive to Applicant’s amendment of claim 12.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-7, 9-13, 15-19, 21, and 22 are rejected under 35 U.S.C. § 103 as being unpatentable over U.S. Patent Publication No. 2019/0229131 (filed Jan. 25, 2019) (hereinafter “Chung”) in view of 2020/0135825 (filed Sept. 17, 2019) (hereinafter “Cha”), and further in view of U.S. Patent Publication No. 2018/0248131 (filed July 21, 2016) (hereinafter “Inagaki”).
Regarding independent claim 1, Chung discloses: A display panel (FIG. 9, display unit 130, [0113]), comprising
a first transistor (FIG. 14, first TFT 200, [0159]) and a second transistor (FIG. 14, second TFT 300, [0159]) electrically connected to each other (FIG. 14, depicting wherein the first and second TFT 200/300 are electrically connected by, e.g., second electrode 802),
wherein the first transistor (FIG. 14, first TFT 200) comprises a first active portion made of a low-temperature polysilicon material ([0085]: “A semiconductor layer may be formed on the first buffer layer 101, and then patterned to be formed as the first active layer 201 of the first TFT 200. The semiconductor layer may include various materials. For example, the semiconductor layer may include an inorganic semiconductor material, such as amorphous silicon or crystalline silicon. As another example, the semiconductor layer may include an oxide semiconductor or an organic semiconductor material.”) and a first gate (FIG. 14, gate electrode 202, [0160]), and
the second transistor comprises a second active portion (FIG. 14, the portion of the active layer 301 shown in FIG. 14 a second gate (FIG. 14, second gate electrode 302, [0161]):
wherein the display panel (FIG. 9, display unit 130) further comprises:
a base (FIG. 14, substrate 100, [0083]);
a first active layer (FIG. 14, first active layer 201, [0160]) disposed on the base (FIG. 14, depicting wherein the first active layer 201 is disposed on the substrate 100) and comprising a first active portion (FIG. 14, the portion of the active layer 201 shown in FIG. 14);
a second active layer (FIG. 14, second active layer 301, [0161]) disposed on a side of the first active layer away from the base (FIG. 14, depicting wherein the second active layer 301 is disposed on a side of the first active layer 201 facing away from the substrate 100) and comprising a second active portion (FIG. 14, the portion of the active layer 301 shown in FIG. 14) located on a side of the first active portion away from the base (FIG. 14, depicting wherein the portion of the active layer 301 shown in FIG. 14 is disposed on a side of the portion of the active layer 201 shown in FIG. 14 facing away from the substrate 100);
a first metal layer (FIG. 14, depicting a layer disposed on a fifth insulation layer 107 formed from metal; [0106]: “For example, the second gate electrode 302 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and have a single-layered or a multi-layered structure.”) disposed on a side of the second active layer away from the first active layer (FIG. 14, depicting wherein the metal layer disposed on the fifth insulation layer 107 is disposed on a side of the second active layer 301 facing away from the first active layer 201) and
comprising the second gate (FIG. 14, depicting wherein the metal layer disposed on the fifth insulation layer 107 includes the second gate electrode 302) located on a side of the second active portion away from the first active portion (FIG. 14, depicting wherein the second gate electrode 302 is disposed on a side of the portion of the active layer 301 shown in FIG. 14 facing away from the portion of the active layer 201 shown in FIG. 14),
wherein an orthographic projection of the second active portion on the base at least partially overlaps an orthographic projection of the first active portion on the base (FIG. 14, depicting wherein a projection of the portion of the active layer 301 shown in FIG. 14 on the substrate 100 at least partially overlaps with a projection of the portion of the active layer 201 shown in FIG. 14 on the substrate 100).
Chung further discloses wherein the first transistor (Chung FIG. 14, first TFT 200) comprises a first source (Chung FIG. 14, first power line 901, [0168]) and a first drain (Chung FIG. 14, second electrode 802, [0169]) and the second transistor (Chung FIG. 14, second TFT 300) further comprises a second source (Chung FIG. 14, second source electrode 303, [0161]) and a second drain (Chung FIG. 14 second drain electrode 304, [0161]).
Chung does not specifically disclose wherein the second transistor comprises a second active portion made of a metal oxide material.
In the same field of endeavor, Cha discloses a transistor including an active layer formed from an oxide semiconductor material including metal oxides (FIG. 3, [0091]: “The driving active pattern 320 a and the second active layer 350 b and 350 c may be formed of polysilicon or an oxide semiconductor. The oxide semiconductor may include oxides based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In).”)
Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select a known active layer material such as one including a metal oxide, as shown by Cha in [0091], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose a metal oxide active layer material over other materials depending on manufacturing considerations such as cost of materials or time it takes to process the layer.
Chung does not specifically disclose a second metal layer disposed between the second active layer and the first active layer, wherein the second metal layer comprises the first source, the first drain, the second source, and the second drain that are formed in a same layer, and the first gate and the second gate are disposed on opposite sides of the second metal layer.
In the same field of endeavor, Inagaki discloses a transistor (FIG. 1, depicting an organic transistor, [0175]) including source and drain contacts formed as a metal layer underneath an active layer (FIG. 1, source/drain contacts 5 and 6, [0175]), such that the source and drain contacts are connected to two ends of the active portion (FIG. 1, semiconductor layer 4, [0175]). Regarding the configuration of the source and drain contacts, in [0151], Inagaki states: “bottom contact type (hereinafter, BC type) has more practical structure from the aspect that the organic semiconductor material which is more deteriorated than other element forming materials (metal for electrode material and resin for gate insulating material) regarding heat resistance, weather resistance, and solvent resistance.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the display unit of Chung adding the bottom contact configuration of Inagaki such that the second source electrode 303 and second drain electrode 304 are formed as a second metal layer underneath the active layer 301 and connected to two ends of the active layer 301 in order to reduce the number of manufacturing steps performed on the active layer, thereby reducing the possibility of deterioration of the active layer due to the additional steps. See Inagaki [0151].
Moreover, the bottom contact configuration of the second source electrode 303 and second drain electrode 304 would result in a configuration wherein the first power line 901, the second electrode 802, the second source electrode 303, and the second drain electrode 304 are disposed between the active layer 301 and the active layer 201, and the first gate electrode 202 and the second gate electrode 302 are disposed on opposite sides of the layer in which the first power line 901, the second electrode 802, the second source electrode 303, and the second drain electrode 304 are disposed.
Regarding claim 3, Chung in view of Cha and Inagaki further discloses wherein the second active portion (Chung FIG. 14, the portion of the active layer 301 shown in FIG. 14) comprises a second source contact sub-portion (Inagaki FIG. 1, the portion of the semiconductor layer 4 disposed above the contact 5) located on a side of the second source away from the first active portion (Chung FIG. 14, depicting wherein with the configuration of Inagaki FIG. 1, the active layer 301 would be located on a side of the second source electrode 303 facing away from the portion of the active layer 201 shown in FIG. 14),
a second drain contact sub-portion (Inagaki FIG. 1, the portion of the semiconductor layer 4 disposed above the contact 6) located on a side of the second drain away from the first active portion (Chung FIG. 14, depicting wherein with the configuration of Inagaki FIG. 1, the active layer 301 would be located on a side of the second drain electrode 304 facing away from the portion of the active layer 201 shown in FIG. 14), and
a second channel sub-portion (Inagaki FIG. 1, the portion of the semiconductor layer 4 disposed between the contacts 5 and 6) connected between the second source contact sub-portion and the second drain contact sub-portion (Inagaki FIG. 1, depicting wherein the portion of the semiconductor layer 4 disposed between the contacts 5 and 6 is connected to the portions of the semiconductor layer located above the contacts 5 and 6), and the second channel sub-portion is located between the second source and the second drain (Chung FIG. 14, depicting wherein with the configuration of Inagaki FIG. 1, the portion of the active layer 301 shown in FIG. 14 corresponding to the portion of the semiconductor layer 4 disposed between the contacts 5 and 6 would be disposed between the second source electrode 303 and the second drain electrode 304).
Regarding claim 4, Chung in view of Cha and Inagaki further discloses wherein each of a resistivity of a material of the second source contact sub-portion and a resistivity of a material of the second drain contact sub-portion is equal to a resistivity of a material of the second channel sub-portion (Chung FIG. 14; depicting wherein the active layer 301, formed from a metal oxide as disclosed in Cha, is formed as a single layer, such that all portions of the active layer 301 would be formed from the same material and thus have the same resistivity; see also Inagaki FIG. 1, depicting wherein the semiconductor layer 4 is formed from a single layer, such that all portions of the semiconductor layer 4 would be formed from the same material and thus have the same resistivity).
Regarding claim 5, Chung in view of Cha and Inagaki further discloses wherein the first source (Chung FIG. 14, first power line 901, [0168]) and the first drain (Chung FIG. 14, second electrode 802, [0169]) connected to two ends of the first active portion (Chung FIG. 14, depicting wherein the first power line 901 and the second electrode 802 are electrically connected to two ends of the portion of the active layer 201 shown in FIG. 14), respectively, and the second source (Chung FIG. 14, second source electrode 303, [0161]) and the second drain (Chung FIG. 14, second drain electrode 304, [0161]) are connected to two ends of the second active portion (Chung FIG. 14, depicting wherein the second source electrode 303 and the second drain electrode 304 are electrically connected to two ends of the portion of the active layer 301 shown in FIG. 14), respectively; and the second active portion is between the first source and the first drain (Chung FIG. 14, depicting wherein the portion of the active layer 301 shown in FIG. 14 is between the first power line 901 and the second electrode 802).
Regarding claim 6, Chung in view of Cha and Inagaki further discloses wherein the first active portion (Chung FIG. 14, the portion of the active layer 201 shown in FIG. 14) comprises a first source contact sub-portion connected to the first source (Chung FIG. 14, the portion of the portion of the active layer 201 shown in FIG. 14 disposed under the first power line 901 and electrically connected to the first power line 901) and a first drain contact sub-portion connected to the first drain (Chung FIG. 14, the portion of the portion of the active layer 201 shown in FIG. 14 disposed under the first second electrode 802 and electrically connected to the second electrode 802), and the second source is electrically connected to the first drain contact sub-portion (Chung FIG. 14, depicting wherein the second source electrode 303 is electrically connected to the portion of the portion of the active layer 201 shown in FIG. 14 disposed under the first second electrode 802 and electrically connected to the second electrode 802).
Regarding claim 7, Chung in view of Cha and Inagaki further discloses wherein the first source (Chung FIG. 14, first power line 901) is spaced apart from the second drain (Chung FIG. 14, depicting wherein the first power line 901 is spaced apart from the second drain electrode 304).
Regarding claim 9, Chung in view of Cha and Inagaki further discloses wherein the display panel (Chung FIG. 9, display unit 130, [0113]) further comprises an anode layer (Chung FIG. 14, the portion of the first electrode 601 shown in FIG. 14) disposed on a side of the first metal layer away from the second active layer (Chung FIG. 14, depicting wherein the portion of the first electrode 601 shown in FIG. 14 is disposed on a side of the metal layer disposed on the fifth insulation layer 107 facing away from the second active layer 301), wherein the anode layer comprises an anode (Chung FIG. 14, first electrode 601, [0174]) electrically connected to the first transistor (Chung FIG. 14, depicting wherein the first electrode 601 is electrically connected to the first TFT 200); and the first metal layer (Chung FIG. 14, depicting the metal layer disposed on the fifth insulation layer 107) comprises an adapting portion (Chung FIG. 14, depicting wherein the second electrode 802 includes a portion located on the fifth insulation layer 107, that portion of the second electrode 802 comprising an adapting portion) located between the anode and the first drain (Chung FIG. 14, depicting wherein the adapting portion may be located between another portion of the second electrode 802 and the first electrode 601), and the anode is connected to the first drain by the adapting portion (Chung FIG. 14, depicting wherein the adapting portion connects another portion of the second electrode 802 and the first electrode 601).
Regarding claim 10, Chung in view of Cha and Inagaki further discloses wherein an orthographic projection of the second channel sub-portion (Chung FIG. 14, depicting wherein with the configuration of Inagaki FIG. 1, the portion of the active layer 301 shown in FIG. 14 corresponding to the portion of the semiconductor layer 4 disposed between the contacts 5 and 6 would be disposed between the second source electrode 303 and the second drain electrode 304) on the base is located within an orthographic projection of the anode on the base (Chung FIG. 14, depicting wherein an orthographic projection in the direction of the substrate 100 of the portion of the active layer 301 shown in FIG. 14 corresponding to the portion of the semiconductor layer 4 disposed between the contacts 5 and 6 and that would be disposed between the second source electrode 303 and the second drain electrode 304 would be located within an orthographic projection in the direction of the substrate 100 of the first electrode 601).
Regarding claim 11, Chung in view of Cha and Inagaki further discloses wherein the display panel (Chung FIG. 9, display unit 130, [0113]) further comprises an inorganic passivation layer (Chung FIG. 14, sixth insulating layer 108 which may be an inorganic insulating layer, [0108]) and an organic planarization layer (Chung FIG. 14, eighth insulating layer 110, which may be an organic planarizing layer, [0132]-[0133]) disposed between the second active layer and the anode layer (Chung FIG. 14, depicting wherein the sixth insulating layer 108 and the eighth insulating layer 110 are disposed between the second active layer 301 and the portion of the first electrode 601 shown in FIG. 14), wherein the inorganic passivation layer covers the second active portion (FIG. 14, depicting wherein the sixth insulating layer 108 covers the portion of the active layer 301 shown in FIG 14), and the organic planarization layer covers the inorganic passivation layer (FIG. 14, depicting wherein the eighth insulating layer 110 covers the sixth insulating layer 108).
Regarding claim 12, Chung in view of Cha and Inagaki further discloses wherein the first transistor (Chung FIG. 14, first TFT 200) further comprises an electrode plate (Chung FIG. 14, conductive layer 400, which is an electrode, [0128]) disposed between the first gate and the second active portion (Chung FIG. 14, depicting wherein the conductive layer 400 is disposed between the first gate electrode 202 and the portion of the active layer 301 shown in FIG. 14); and
an orthographic projection of the second channel sub-portion (Chung FIG. 14, depicting wherein with the configuration of Inagaki FIG. 1, the portion of the active layer 301 shown in FIG. 14 corresponding to the portion of the semiconductor layer 4 disposed between the contacts 5 and 6 would be disposed between the second source electrode 303 and the second drain electrode 304) on the base is located in at least part of an orthographic projection of the first gate on the base (Chung FIG. 14, depicting wherein an orthographic projection in the direction of the substrate 100 of the portion of the active layer 301 shown in FIG. 14 corresponding to the portion of the semiconductor layer 4 disposed between the contacts 5 and 6 and that would be disposed between the second source electrode 303 and the second drain electrode 304 would be located within an orthographic projection in the direction of the substrate 100 of the first gate electrode 202),
and the orthographic projection of the second channel sub-portion (Chung FIG. 14, depicting wherein with the configuration of Inagaki FIG. 1, the portion of the active layer 301 shown in FIG. 14 corresponding to the portion of the semiconductor layer 4 disposed between the contacts 5 and 6 would be disposed between the second source electrode 303 and the second drain electrode 304) on the base is located in an orthographic projection of the electrode plate on the base (Chung FIG. 14, depicting wherein an orthographic projection in the direction of the substrate 100 of the portion of the active layer 301 shown in FIG. 14 corresponding to the portion of the semiconductor layer 4 disposed between the contacts 5 and 6 and that would be disposed between the second source electrode 303 and the second drain electrode 304 would be located within an orthographic projection in the direction of the substrate 100 of the conductive layer 400).
Regarding independent claim 13, Chung discloses: A display device (FIG. 9, display apparatus 1, [0112]), comprising a display panel (FIG. 9, display unit 130, [0113]),
wherein the display panel (FIG. 9, display unit 130) comprises
a first transistor (FIG. 14, first TFT 200, [0159]) and a second transistor (FIG. 14, second TFT 300, [0159]) electrically connected to each other (FIG. 14, depicting wherein the first and second TFT 200/300 are electrically connected by, e.g., second electrode 802),
the first transistor (FIG. 14, first TFT 200) comprises a first active portion made of a low-temperature polysilicon material ([0085]: “A semiconductor layer may be formed on the first buffer layer 101, and then patterned to be formed as the first active layer 201 of the first TFT 200. The semiconductor layer may include various materials. For example, the semiconductor layer may include an inorganic semiconductor material, such as amorphous silicon or crystalline silicon. As another example, the semiconductor layer may include an oxide semiconductor or an organic semiconductor material.”) and a first gate (FIG. 14, gate electrode 202, [0160]), and
the second transistor comprises a second active portion (FIG. 14, the portion of the active layer 301 shown in FIG. 14 a second gate (FIG. 14, second gate electrode 302, [0161]):
the display panel (FIG. 9, display unit 130) further comprises:
a base (FIG. 14, substrate 100, [0083]);
a first active layer (FIG. 14, first active layer 201, [0160]) disposed on the base (FIG. 14, depicting wherein the first active layer 201 is disposed on the substrate 100) and comprising a first active portion (FIG. 14, the portion of the active layer 201 shown in FIG. 14);
a second active layer (FIG. 14, second active layer 301, [0161]) disposed on a side of the first active layer away from the base (FIG. 14, depicting wherein the second active layer 301 is disposed on a side of the first active layer 201 facing away from the substrate 100) and comprising a second active portion (FIG. 14, the portion of the active layer 301 shown in FIG. 14) located on a side of the first active portion away from the base (FIG. 14, depicting wherein the portion of the active layer 301 shown in FIG. 14 is disposed on a side of the portion of the active layer 201 shown in FIG. 14 facing away from the substrate 100);
a first metal layer (FIG. 14, depicting a layer disposed on a fifth insulation layer 107 formed from metal; [0106]: “For example, the second gate electrode 302 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), and have a single-layered or a multi-layered structure.”) disposed on a side of the second active layer away from the first active layer (FIG. 14, depicting wherein the metal layer disposed on the fifth insulation layer 107 is disposed on a side of the second active layer 301 facing away from the first active layer 201) and
comprising the second gate (FIG. 14, depicting wherein the metal layer disposed on the fifth insulation layer 107 includes the second gate electrode 302) located on a side of the second active portion away from the first active portion (FIG. 14, depicting wherein the second gate electrode 302 is disposed on a side of the portion of the active layer 301 shown in FIG. 14 facing away from the portion of the active layer 201 shown in FIG. 14),
wherein an orthographic projection of the second active portion on the base at least partially overlaps an orthographic projection of the first active portion on the base (FIG. 14, depicting wherein a projection of the portion of the active layer 301 shown in FIG. 14 on the substrate 100 at least partially overlaps with a projection of the portion of the active layer 201 shown in FIG. 14 on the substrate 100).
Chung further discloses wherein the first transistor (Chung FIG. 14, first TFT 200) comprises a first source (Chung FIG. 14, first power line 901, [0168]) and a first drain (Chung FIG. 14, second electrode 802, [0169]) and the second transistor (Chung FIG. 14, second TFT 300) further comprises a second source (Chung FIG. 14, second source electrode 303, [0161]) and a second drain (Chung FIG. 14 second drain electrode 304, [0161]).
Chung does not specifically disclose wherein the second transistor comprises a second active portion made of a metal oxide material.
In the same field of endeavor, Cha discloses a transistor including an active layer formed from an oxide semiconductor material including metal oxides (FIG. 3, [0091]: “The driving active pattern 320 a and the second active layer 350 b and 350 c may be formed of polysilicon or an oxide semiconductor. The oxide semiconductor may include oxides based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In).”)
Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select a known active layer material such as one including a metal oxide, as shown by Cha in [0091], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose a metal oxide active layer material over other materials depending on manufacturing considerations such as cost of materials or time it takes to process the layer.
Chung does not specifically disclose a second metal layer disposed between the second active layer and the first active layer, wherein the second metal layer comprises the first source, the first drain, the second source, and the second drain that are formed in a same layer, and the first gate and the second gate are disposed on opposite sides of the second metal layer.
In the same field of endeavor, Inagaki discloses a transistor (FIG. 1, depicting an organic transistor, [0175]) including source and drain contacts formed as a metal layer underneath an active layer (FIG. 1, source/drain contacts 5 and 6, [0175]), such that the source and drain contacts are connected to two ends of the active portion (FIG. 1, semiconductor layer 4, [0175]). Regarding the configuration of the source and drain contacts, in [0151], Inagaki states: “bottom contact type (hereinafter, BC type) has more practical structure from the aspect that the organic semiconductor material which is more deteriorated than other element forming materials (metal for electrode material and resin for gate insulating material) regarding heat resistance, weather resistance, and solvent resistance.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the display unit of Chung adding the bottom contact configuration of Inagaki such that the second source electrode 303 and second drain electrode 304 are formed as a second metal layer underneath the active layer 301 and connected to two ends of the active layer 301 in order to reduce the number of manufacturing steps performed on the active layer, thereby reducing the possibility of deterioration of the active layer due to the additional steps. See Inagaki [0151].
Moreover, the bottom contact configuration of the second source electrode 303 and second drain electrode 304 would result in a configuration wherein the first power line 901, the second electrode 802, the second source electrode 303, and the second drain electrode 304 are disposed between the active layer 301 and the active layer 201, and the first gate electrode 202 and the second gate electrode 302 are disposed on opposite sides of the layer in which the first power line 901, the second electrode 802, the second source electrode 303, and the second drain electrode 304 are disposed.
Regarding claim 15, Chung in view of Cha and Inagaki further discloses wherein the second active portion (Chung FIG. 14, the portion of the active layer 301 shown in FIG. 14) comprises a second source contact sub-portion (Inagaki FIG. 1, the portion of the semiconductor layer 4 disposed above the contact 5) located on a side of the second source away from the first active portion (Chung FIG. 14, depicting wherein with the configuration of Inagaki FIG. 1, the active layer 301 would be located on a side of the second source electrode 303 facing away from the portion of the active layer 201 shown in FIG. 14),
a second drain contact sub-portion (Inagaki FIG. 1, the portion of the semiconductor layer 4 disposed above the contact 6) located on a side of the second drain away from the first active portion (Chung FIG. 14, depicting wherein with the configuration of Inagaki FIG. 1, the active layer 301 would be located on a side of the second drain electrode 304 facing away from the portion of the active layer 201 shown in FIG. 14), and
a second channel sub-portion (Inagaki FIG. 1, the portion of the semiconductor layer 4 disposed between the contacts 5 and 6) connected between the second source contact sub-portion and the second drain contact sub-portion (Inagaki FIG. 1, depicting wherein the portion of the semiconductor layer 4 disposed between the contacts 5 and 6 is connected to the portions of the semiconductor layer located above the contacts 5 and 6), and the second channel sub-portion is located between the second source and the second drain (Chung FIG. 14, depicting wherein with the configuration of Inagaki FIG. 1, the portion of the active layer 301 shown in FIG. 14 corresponding to the portion of the semiconductor layer 4 disposed between the contacts 5 and 6 would be disposed between the second source electrode 303 and the second drain electrode 304).
Regarding claim 16, Chung in view of Cha and Inagaki further discloses wherein each of a resistivity of a material of the second source contact sub-portion and a resistivity of a material of the second drain contact sub-portion is equal to a resistivity of a material of the second channel sub-portion (Chung FIG. 14; depicting wherein the active layer 301, formed from a metal oxide as disclosed in Cha, is formed as a single layer, such that all portions of the active layer 301 would be formed from the same material and thus have the same resistivity; see also Inagaki FIG. 1, depicting wherein the semiconductor layer 4 is formed from a single layer, such that all portions of the semiconductor layer 4 would be formed from the same material and thus have the same resistivity).
Regarding claim 17, Chung in view of Cha and Inagaki further discloses wherein the first source (Chung FIG. 14, first power line 901, [0168]) and the first drain (Chung FIG. 14, second electrode 802, [0169]) connected to two ends of the first active portion (Chung FIG. 14, depicting wherein the first power line 901 and the second electrode 802 are electrically connected to two ends of the portion of the active layer 201 shown in FIG. 14), respectively, and the second source (Chung FIG. 14, second source electrode 303, [0161]) and the second drain (Chung FIG. 14, second drain electrode 304, [0161]) are connected to two ends of the second active portion (Chung FIG. 14, depicting wherein the second source electrode 303 and the second drain electrode 304 are electrically connected to two ends of the portion of the active layer 301 shown in FIG. 14), respectively; and the second active portion is between the first source and the first drain (Chung FIG. 14, depicting wherein the portion of the active layer 301 shown in FIG. 14 is between the first power line 901 and the second electrode 802).
Regarding claim 18, Chung in view of Cha and Inagaki further discloses wherein the first active portion (Chung FIG. 14, the portion of the active layer 201 shown in FIG. 14) comprises a first source contact sub-portion connected to the first source (Chung FIG. 14, the portion of the portion of the active layer 201 shown in FIG. 14 disposed under the first power line 901 and electrically connected to the first power line 901) and a first drain contact sub-portion connected to the first drain (Chung FIG. 14, the portion of the portion of the active layer 201 shown in FIG. 14 disposed under the first second electrode 802 and electrically connected to the second electrode 802), and the second source is electrically connected to the first drain contact sub-portion (Chung FIG. 14, depicting wherein the second source electrode 303 is electrically connected to the portion of the portion of the active layer 201 shown in FIG. 14 disposed under the first second electrode 802 and electrically connected to the second electrode 802).
Regarding claim 19, Chung in view of Cha and Inagaki further discloses wherein the first source (Chung FIG. 14, first power line 901) is spaced apart from the second drain (Chung FIG. 14, depicting wherein the first power line 901 is spaced apart from the second drain electrode 304).
Regarding claim 21, Chung in view of Cha and Inagaki further discloses wherein both the second source (Chung FIG. 14, second source electrode 303, [0161]) and the second drain (Chung FIG. 14, second drain electrode 304, [0161]) are electrically insulated from the first gate (Chung FIG. 14, depicting wherein the second source electrode 303 and second drain electrode 304 are electrically insulated from the first gate electrode 202 by, e.g., third insulating layer 104, [0059]).
Regarding claim 22, Chung in view of Cha and Inagaki further discloses wherein both the second source (Chung FIG. 14, second source electrode 303, [0161]) and the second drain (Chung FIG. 14, second drain electrode 304, [0161]) are electrically insulated from the first gate (Chung FIG. 14, depicting wherein the second source electrode 303 and second drain electrode 304 are electrically insulated from the first gate electrode 202 by, e.g., third insulating layer 104, [0059]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813