DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 6 and 7 recite the limitation "the bottom wafer" and “the top wafer” in line 1. There is insufficient antecedent basis for this limitation in the claim. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 1, 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirano (JP 2015-226189) in view of Stoemmer et al (US 2006/0164186) . Hirano discloses, regarding, Claim 1, A dual resonator chip 6 , comprising: a kilohertz frequency resonator 3B in the chip; and a megahertz frequency resonator 3A in the same chip 6 (see Fig. 1) , wherein the kilohertz frequency resonator 3B and the megahertz frequency resonator 3A are MEMS resonators. Stoemmer et al is being used for explicitly showing that a first resonator R1 and second resonator R2 can be placed in the same chip (see Figs. 6, 7; since the resonators are embedded in the same substrate) and the resonators can be microelectronic resonators [0021]. The Prior Art further discloses, regarding, Claim 2 , the kilohertz frequency resonator and the megahertz frequency resonator are attached to each other (Hirano, Fig. 1; Stoemmer et al, Fig. 6) . It would have been obvious before the effective filing date of the claimed invention to disclose the resonator chip as disclosed by Hirano and to show explicitly the limitations pertaining to Stoemmer et al for the purpose of efficiently protecting resonator devices. Claim(s) 3, 4, 8 – 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirano and Stoemmer et al as applied to claim 1 above, and further in view of Yamamoto et al (US 5,844,452) . The combined resonator discloses all of the elements above. However, the combined resonator does not disclose the elements below. On the other hand, Yamamoto et al discloses, regarding, Claim 3, the kilohertz frequency resonator 26 and the megahertz frequency resonator 28 are positioned on top of each other (see Fig. 7A) . Claim 4, the kilohertz frequency resonator 26 and the megahertz frequency resonator 28 are positioned side by side (Fig. 2A) . Claim 8 , the megahertz frequency resonator is configured adapted to resonate in an in-plane length extensional resonance mode (see Fig. 4A) . Claim 9 , the kilohertz frequency resonator is adapted to resonate in an out of plane resonance mode (since the resonator can operate at different resonating frequencies; see Stoemmer et al, 0049, 0052; Yamamoto et al, column 9, lines 22 – 45) . Claim 10 , the megahertz frequency resonator and the kilohertz frequency resonator are integrated into one package, each comprising their own individual contact pads ( see Hirano, Fig. 3; Yamamoto et al, Fig s . 6, 7A ). Claim 11 , the kilohertz frequency resonator is a kilohertz frequency resonator having a 32.768 kHz resonance frequency , since it has been held that discovering the optimum value of result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980). . Claim 12 , through silicon vias, TSVs, configured adapted to provide electrical connection through the top wafer portion to both the megahertz frequency resonator and the kilohertz frequency resonator (since the resonators are connected via electric wires; see Figs. 2A, 12A) . It would have been obvious before the effective filing date of the claimed invention to disclose the combined resonator chip as disclosed above and to disclose the limitations pertaining to Yamamoto et al for the purpose of fabricating a low-cost resonator. Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirano and Stoemmer et al as applied to claim 1 above, and further in view of Handtmann et al (US 2009/0265903) . The combined resonator discloses all of the elements above. However, the combined resonator does not disclose the elements below. On the other hand, Handtmann et al discloses, regarding, Claim 5, the chip comprises a top wafer portion and a bottom wafer portion bonded together to form the chip (Fig. 5A; 0045, 0097). It would have been obvious before the effective filing date of the claimed invention to disclose the combined resonator chip as disclosed above and to disclose the limitations pertaining to Handmann et al for the purpose of accurately controlling resonance frequencies of resonators. Claim(s) 6, 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hirano and Stoemmer et al as applied to claim 1 above, and further in view of Stevenson (US 7,639,094) . The combined resonator discloses all of the elements above. However, the combined resonator does not disclose the elements below. On the other hand, Stevenson discloses, regarding, Claim 6, t he bottom wafer portion comprises the megahertz frequency resonator 303, 310 (see Fig. 3) . It is reminded that the changing of the location is relative, since all that is required is for the chip/container to be flipped over, at which point, the megahertz resonator can be on the bottom and vice-versa. Claim 7, the top wafer portion comprises the kilohertz frequency resonator 317, 316 (see Fig. 3) It would have been obvious before the effective filing date of the claimed invention to disclose the combined resonator chip as disclosed above and to disclose the limitations pertaining to Stevenson for the purpose of easily designing and testing resonators. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT Julio C. Gonzalez whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-2024 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-F . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Abdullah Riyami can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 5712703119 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. FILLIN "Examiner Stamp" \* MERGEFORMAT /Julio C. Gonzalez/ Primary Examiner Art Unit 2831 February 26, 2026