DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
Examiner acknowledges the amendment to the title filed on November 10, 2025. The objection to specification in the previous Office Action filed on October 02, 2025 is hereby withdrawn.
Claim Rejections - 35 USC § 112
Examiner acknowledges the amendment to claims 5 and 17 filed on November 10, 2025. The 35 U.S.C. § 112 rejections in the previous Office Action filed on October 02, 2025 are hereby withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 5, 13, 17, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US PG-Pub No.: 2023/0006025 A1, hereinafter, “Lee”), prior art of record.
Regarding claim 19, Lee discloses a display panel (see Lee, FIGs. 1 and 9), comprising:
a light emitting device layer (OLED, FIG. 9), provided with a plurality of light emitting devices (OLED, FIG. 1 shows a plurality of devices);
an array substrate (100-119, FIG. 9), the light emitting device layer (OLED) disposed on the array substrate (100-119);
the array substrate (100-119) comprising:
a substrate layer (100+111+112);
an insulation module (113-119), disposed on the substrate layer (100+111+112, FIG. 9);
a first conductive layer (1610+S1+D1 inside 117, FIG. 9) and a second conductive layer (1720+CM inside 118, FIG. 9), disposed in the insulation module (113-119) at different layers, the first conductive layer (1610+S1+D1 inside 117) located at a side of the second conductive layer (1720+CM inside 118) close to the substrate layer (100+111+112, FIG. 9);
wherein first grooves (grooves inside 112 for S1 and D1) are provided on a surface of the substrate layer (100+111+112) facing the insulation module (113-119), and orthographic projections of the first grooves (grooves inside 112 for S1 and D1) and the second conductive layer (1720+CM inside 118) on the substrate layer (100+111+112) are overlapped (FIG. 9).
Regarding claim 5, Lee discloses the display panel according to claim 19, wherein the insulation module (113-119) comprises: a gate insulating layer (115), disposed on the substrate layer (100+111+112), the first conductive layer (1610+S1+D1 inside 117) disposed on a surface of the gate insulating layer (115) away from an active layer (OA, FIG. 9) of the array substrate; an interlayer dielectric layer (117, FIG. 9), disposed on the substrate layer (100+111+112) and covering the gate insulating layer (115) and the first conductive layer (1610+S1+D1 inside 117), the second conductive layer (CM+1720 inside 118) disposed at a side of the interlayer dielectric layer (117) away from the first conductive layer (1610+S1+D1 inside 117); a passivation layer (118, FIG. 9), disposed on the interlayer dielectric layer (117) and covering the second conductive layer (CM+1720 inside 118); a flat layer (119, FIG. 9), disposed on the passivation layer (118); wherein second grooves are provided on a surface of the interlayer dielectric layer (117) facing the second conductive layer (CM+1720), and the second conductive layer (CM+1720 inside 118) is located in the second grooves (FIG. 9).
Regarding claim 13, Lee discloses a display device (see Lee, FIGs.1 and 9), comprising the display panel of claim 19.
Regarding claim 17, Lee discloses the display device of claim 13, wherein the insulation module (113-119) comprises: a gate insulating layer (115, FIG. 9), disposed on the substrate layer (100+111+112), the first conductive layer (1610+S1+D1 inside 117) disposed on a surface of the gate insulating layer (115) away from an active layer (OA, FIG. 9) of the array substrate; an interlayer dielectric layer (117, FIG. 9), disposed on the substrate layer (100+111+112) and covering the gate insulating layer (115) and the first conductive layer (1610+S1+D1 inside 117), the second conductive layer (CM+1720 inside 118) disposed at a side of the interlayer dielectric layer (117) away from the first conductive layer (1610+S1+D1 inside 117); a passivation layer (118, FIG. 9), disposed on the interlayer dielectric layer (117) and covering the second conductive layer (CM+1720 inside 118); a flat layer (119, FIG. 9), disposed on the passivation layer (118); wherein second grooves are provided on a surface of the interlayer dielectric layer (117) facing the second conductive layer (CM+1720 inside 118), and the second conductive layer (CM+1720 inside 118) is located in the second grooves (FIG. 9).
Allowable Subject Matter
Claims 1, 7, 9-10, and 12 are allowed.
Claims 2-3, 6, 14-15, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record neither anticipates nor renders obvious all the claimed subject of claim 1, in particular, the second conductive layer comprises: a first electrode layer; a second electrode layer, located at a side of the first electrode layer; a wiring layer, located at a side of the second electrode layer away from the first electrode layer; wherein the first electrode layer, the second electrode layer and the wiring layer are located on the same plane in the insulation module and are electrically insulated from each other; wherein the orthographic projections of the pad layers on the substrate layer are located at two sides of the wiring layer.
The prior art of record neither anticipates nor renders obvious all the claimed subject of claims 2 and 14, in particular, the substrate layer comprises: a base layer; a light shielding layer, disposed on the base layer; a buffer layer, disposed on the base layer and covering the light shielding layer; wherein the first grooves are provided on a surface of the buffer layer away from the light shielding layer; wherein an active layer in the array substrate is disposed in the first grooves. Claim 3 depends upon claim 2; and claim 15 depends upon claim 14.
The prior art of record neither anticipates nor renders obvious all the claimed subject of claims 6 and 18, in particular, the gate insulating layer comprises: a first insulating layer, disposed on a surface of the active layer of the array substrate away from the substrate layer; a second insulating layer, disposed on the substrate layer and corresponding to the wiring layer in the second conductive layer; wherein the second insulating layer is disposed in one of the first grooves; wherein the first conductive layer further comprises a gate layer, and the gate layer is disposed on a surface of the first insulating layer away from the active layer.
The prior art of record neither anticipates nor renders obvious all the claimed subject of base claim 7, in particular, the step of preparing the substrate layer comprises: forming a light shielding layer on a base layer; forming a buffer layer covering the light shielding layer on the base layer; forming the first grooves on a surface of the buffer layer away from the light shielding layer; after the step of preparing the substrate layer, the method further comprising: forming an active layer in the first grooves. Claims 9-10 and 12 depend upon claim 7.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/XIA L CROSS/Primary Examiner, Art Unit 2892