DETAILED ACTION
Claims 1 through 20 originally filed 31 March 2023. By amendment received 6 April 2026; claims 1, 3, 5 through 7, 9, 11, 13 through 16, and 18 are amended, claim 4 is cancelled, and claim 21 is added. Claims 1 through 3 and 5 through 21 are addressed by this action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments have been fully considered; they are addressed below.
Applicant argues that the amendments to the drawings overcome the previous drawing objections. This argument is not persuasive.
Each of figures 2 through 5 illustrate different stages in an assembly process such that each of figures 2 through 5 contain modified forms in each figure. Modified forms of construction must be shown in separate views (37 CFR 1.84(h)(5)). The present amendment employs reference characters to identify different "diagrams" within each figure. This manner of labeling does not comply with the requirements of 37 CFR 1.84(u)(1) regarding the labeling of separate views. Specifically, view numbers must be preceded by the abbreviation "FIG.". Proper compliance with the requirements of 37 1.84(u)(1) would entail modifying figure 2 to include labels "FIG. 2A" and "FIG. 2B" rather than the label "FIG. 2" and modifying figures 3 through 5 similarly. This modification would also require amending the disclosure in a commensurate manner. An example of this manner of labeling can be found in previously cited Tsuji (US Pub. 2020/0412086) (see Tsuji, especially, Figures 8A and 8B). Since the present drawings are not labeled in a manner that complies with 37 CFR 1.84(h)(5) and 37 CFR 1.84(u)(1), this objection is maintained. As such, this argument is not persuasive.
Applicant argues that the amended features of the independent claims define these claims over the cited prior art. Upon further search and consideration, it is determined that a different combination of the previously cited art reads on that which is now claimed. As such, the previous rejection is withdrawn and a new rejection has been formulated as set forth below.
Additional explanation of a particularly notable interpretation underlying this new rejection is provided due to statements made in the interview dated 2 April 2026. With respect to this argument, exemplary claim 1 requires "Wherein the dummy pillar extends from the first isolation layer to the surface layer, or extends from the surface layer to the first isolation layer." It is understood that extension of an element "to" a particular layer is met by that element at least reaching that layer in extension and does not preclude that element extending beyond that layer. This understanding of the breadth of this limitation is underpinned by dependent claim 6 being a proper dependent claim while also further requiring "Wherein the slot comprises a recess extending through a surface layer of the carrier into a base layer of the carrier." By this understanding, Tabuchi (US Patent 5,909,524) teaches dummy pillars that extend from the first isolation layer to the surface layer of the carrier (see Tabuchi, Figures 6A, 6B, and 6C in which support bump 23a atop insulating layer 206 slots into groove 14 and through a surface layer composed of electrical connections 15). Since the dummy pillar of Tabuchi extends through the surface layer of the carrier and since the present claim language must be construed as allowing the dummy pillar to extend through the surface layer of the carrier, Tabuchi renders obvious this aspect of the present claim when combined in the manner of the new rejection set forth below regarding this claim.
As such, all claims are addressed as follows:
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(u)(1).
Each of figures 2, 3, 4, and 5 include multiple views that are not separately labeled. Each view must be individually labeled.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3, 5, 6, 8 through 11, 13, 16, 17, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ishida et al. (Ishida, US Pub. 2021/0399523) in view of Tabuchi (US Patent 5,909,524).
Regarding claim 1, Ishida discloses, "A vertical cavity surface emitting laser (VCSEL) chip comprising a plurality of VCSELs" (p. [0046] and Fig. 6, pts. 140 and 159). "A first isolation layer" (p. [0062] and Fig. 4, pt. 153). "A plurality of first electrical contacts" (p. [0062] and Fig. 5, pts. 148 and 154). "A carrier including a surface layer" (p. [0066] and Fig. 4, pts. 120, 122, and 123). "A base layer" (p. [0066] and Fig. 4, pts. 120 and 121). "The surface layer including a plurality of second electrical contacts" (p. [0066] and Fig. 4, pts. 122 and 123). "A plurality of conductive pillars electrically connecting the VCSEL chip and the carrier" (p. [0066] and Fig. 4, pts. 121, 122, 123, 155, and 157). "The plurality of conductive pillars extend from respective electrical contacts of the first plurality of contacts or the second plurality of electrical contacts" (p. [0066] and Fig. 4, pts. 121, 122, 123, 155, and 157). Ishida does not explicitly disclose, "A second isolation layer between the surface layer and the base layer." "A dummy pillar." "[The dummy pillar] electrically isolated from the VCSEL chip." "[The dummy pillar] mating with a slot." "Wherein the dummy pillar extends from the first isolation layer to the surface layer, or extends from the surface layer to the first isolation layer." Tabuchi discloses, "A second isolation layer between the surface layer and the base layer" (col. 4, lines 32-39 and Fig. 2B, pts. 2, 10, and 15). "A dummy pillar" (col. 3, lines 58-64 and Fig. 6A, pt. 23a). "[The dummy pillar] electrically isolated from the VCSEL chip" (col. 4, lines 17-20 and Fig. 6A, pts. 23a and 206). "[The dummy pillar] mating with a slot" (col. 4, lines 21-31 and Figs. 6A and 6B, pts. 14 and 23a). "Wherein the dummy pillar extends from the first isolation layer to the surface layer, or extends from the surface layer to the first isolation layer" (col. 4, lines 17-20 and Fig. 6A, pts. 23a and 206). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Tabuchi. In view of the teachings of Ishida regarding a VCSEL array including multiple connection pillars, the additional inclusion of alignment pillars to assist with alignment as taught by Tabuchi would enhance the teachings of Ishida by allowing for improved alignment between the laser chip and the carrier.
Regarding claim 3, Ishida does not explicitly disclose, "Wherein an upper recess portion having a first width is defined in the slot." "A lower recess portion having a second width is defined in the slot." "The second width being less than the first width." Tabuchi discloses, "Wherein an upper recess portion having a first width is defined in the slot" (col. 4, lines 21-23 and Fig. 6B, pt. 14). "A lower recess portion having a second width is defined in the slot" (col. 4, lines 21-23 and Fig. 6B, pt. 14). "The second width being less than the first width" (col. 4, lines 21-23 and Fig. 6B, pt. 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Tabuchi for the reasons provided above regarding claim 1.
Regarding claim 5, Ishida does not explicitly disclose, "Wherein the slot comprises a recess in a surface layer of the carrier." Tabuchi discloses, "Wherein the slot comprises a recess in a surface layer of the carrier" (col. 4, lines 21-46 and Fig. 6B, pts. 2, 10, and 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Tabuchi for the reasons provided above regarding claim 1.
Regarding claim 6, Ishida does not explicitly disclose, "Wherein the slot comprises a recess extending through a surface layer of the carrier into a base layer of the carrier." Tabuchi discloses, "Wherein the slot comprises a recess extending through a surface layer of the carrier into a base layer of the carrier" (col. 4, lines 21-46 and Fig. 6B, pts. 2, 10, and 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Tabuchi for the reasons provided above regarding claim 1.
Regarding claim 8, The combination of Ishida and Tabuchi does not explicitly disclose, "Wherein each of the plurality of conductive pillars has a maximum diameter less than 25 micrometers." It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to dimension the conductive pillars to within the noted range so as to balance minimizing the overall footprint of the device against minimum practical dimensions of the pillars, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 9, Ishida discloses, "A vertical cavity surface emitting laser (VCSEL) chip comprising a plurality of VCSELs" (p. [0046] and Fig. 6, pts. 140 and 159). "[The plurality of VCSELs] in a bottom-emitting configuration" (p. [0046], [0061], [0068] and Figs. 3 and 5, pts. 141, 150a, and 162, where light is emitted from lasers 150a through substrate 141 toward lenses 162 in a manner consistent with bottom-emitting devices). "A first isolation layer" (p. [0062] and Fig. 4, pt. 153). "Wherein the plurality of VCSELs are respectively associated with a plurality of first electrical contacts" (p. [0047] and Fig. 6, pts. 159). "A carrier having a surface layer" (p. [0066] and Fig. 4, pts. 120, 122, and 123). "A base layer" (p. [0066] and Fig. 4, pts. 120 and 121). "Wherein the surface layer includes a plurality of second electrical contacts" (p. [0066] and Fig. 4, pts. 122 and 123). "Wherein the VCSEL chip is in a flip chip configuration with the carrier" (p. [0066] and Fig. 4, pts. 120 and 140). "A plurality of conductive pillars that electrically connect the plurality of first electrical contacts and the plurality of second electrical contacts" (p. [0047], [0066], and Fig. 4, pts. 121, 122, 123, 155, 157, and 159). "Wherein the plurality conductive pillars extend from respective electrical contacts of the first plurality of contacts or the second plurality of electrical contacts" (p. [0066] and Fig. 4, pts. 121, 122, 123, 155, and 157). Ishida does not explicitly disclose, "A second isolation layer between the surface layer and the base layer." "A dummy pillar." "[The dummy pillar] is electrically isolated from the plurality of first electrical contacts and the plurality of second electrical contacts." "Wherein the dummy pillar extends from the first isolation layer to the surface layer, or extends from the surface layer to the first isolation layer." Tabuchi discloses, "A second isolation layer between the surface layer and the base layer" (col. 4, lines 32-39 and Fig. 2B, pts. 2, 10, and 15). "A dummy pillar" (col. 3, lines 58-64 and Fig. 6A, pt. 23a). "[The dummy pillar] is electrically isolated from the plurality of first electrical contacts and the plurality of second electrical contacts" (col. 4, lines 17-20 and Fig. 6A, pts. 23a and 206). "Wherein the dummy pillar extends from the first isolation layer to the surface layer, or extends from the surface layer to the first isolation layer" (col. 4, lines 17-20 and Fig. 6A, pts. 23a and 206). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Tabuchi for the reasons provided above regarding claim 1.
Regarding claim 10, Ishida discloses, "Wherein the carrier comprises an integrated circuit chip or a substrate" (p. [0066] and Fig. 4, pt. 120).
Regarding claim 11, Ishida does not explicitly disclose, "Wherein the slot extends from one of the VCSEL chip or the surface layer." "Wherein the dummy pillar mates with the slot of the one of the VCSEL chip or the surface layer." Tabuchi discloses, "Wherein the slot extends from one of the VCSEL chip or the surface layer" (col. 4, lines 21-46 and Fig. 6B, pts. 2, 10, and 14). "Wherein the dummy pillar mates with the slot of the one of the VCSEL chip or the surface layer" (col. 4, lines 21-31 and Figs. 6A and 6B, pts. 14 and 23a). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Tabuchi for the reasons provided above regarding claim 1.
Regarding claim 13, Ishida discloses, "Wherein the plurality of conductive pillars extend from the respective electrical contacts of the first plurality of contacts to the carrier" (p. [0066] and Fig. 4, pts. 121, 122, 123, 155, and 157). Ishida does not explicitly disclose, "Wherein the dummy pillar extends from the first isolation layer to the surface layer." Tabuchi discloses, "Wherein the dummy pillar extends from the first isolation layer to the surface layer" (col. 4, lines 17-20 and Fig. 6A, pts. 23a and 206). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Tabuchi for the reasons provided above regarding claim 1.
Regarding claim 16, Ishida does not explicitly disclose, "Wherein the plurality of conductive pillars extend from the respective electrical contacts of the second plurality of contacts to the VCSEL chip." "Wherein the dummy pillar extends from the first isolation layer to the surface layer." Tabuchi discloses, "Wherein the plurality of conductive pillars extend from the respective electrical contacts of the second plurality of contacts to the VCSEL chip" (col. 4, lines 32-39 and Fig. 6B, pts. 15c and 16). "Wherein the dummy pillar extends from the first isolation layer to the surface layer" (col. 4, lines 17-20 and Fig. 6A, pts. 23a and 206). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Tabuchi for the reasons provided above regarding claim 1.
Regarding claim 17, The combination of Ishida and Tabuchi does not explicitly disclose, "Wherein a spacing of the plurality of first electrical contacts defines a pitch that is less than 45 micrometers." It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to dimension the spacing between the contacts to within the noted range so as to balance minimizing the overall footprint of the device against minimum practical pitch between the contacts, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 21, Ishida does not explicitly disclose, "Wherein an upper recess portion having a first width is defined in the slot." "A lower recess portion having a second width is defined in the slot." "The second width being less than the first width." Tabuchi discloses, "Wherein an upper recess portion having a first width is defined in the slot" (col. 4, lines 21-23 and Fig. 6B, pt. 14). "A lower recess portion having a second width is defined in the slot" (col. 4, lines 21-23 and Fig. 6B, pt. 14). "The second width being less than the first width" (col. 4, lines 21-23 and Fig. 6B, pt. 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Tabuchi for the reasons provided above regarding claim 1.
Claims 2, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ishida, in view of Tabuchi, and further in view of Barwicz et al. (Barwicz, US Pub. 2018/0358778).
Regarding claim 2, The combination of Ishida and Tabuchi does not explicitly disclose, "Wherein the slot comprises a hollow extension from the VCSEL chip." Barwicz discloses, "Wherein the slot comprises a hollow extension from the VCSEL chip" (p. [0017] and Fig. 1, pts. 50b, 50c, and 201). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida and Tabuchi with the teachings of Barwicz. In view of the teachings of Ishida regarding a VCSEL array including multiple connection pillars and the alternate configuration of the alignment pillar to extend from the carrier to a slot in on the emitter chip as taught by Barwicz would enhance the teachings of Ishida and Tabuchi by indicating a suitably alternate arrangement for the alignment pillar.
Regarding claim 14, Ishida discloses, "Wherein the plurality of conductive pillars extend from the respective electrical contacts of the first plurality of contacts to the carrier" (p. [0066] and Fig. 4, pts. 121, 122, 123, 155, and 157).
The combination of Ishida and Tabuchi does not explicitly disclose, "Wherein the dummy pillar extends from the surface layer to the first isolation layer." Barwicz discloses, "Wherein the dummy pillar extends from the surface layer to the first isolation layer" (p. [0017] and Fig. 1, pts. 200 and 201). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida and Tabuchi with the teachings of Barwicz for the reasons provided above regarding claim 2.
Regarding claim 15, Ishida does not explicitly disclose, "Wherein the plurality of conductive pillars extend from the respective electrical contacts of the second plurality of contacts to the VCSEL chip." Tabuchi discloses, "Wherein the plurality of conductive pillars extend from the respective electrical contacts of the second plurality of contacts to the VCSEL chip" (col. 4, lines 32-39 and Fig. 6B, pts. 15c and 16). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Tabuchi for the reasons provided above regarding claim 1.
The combination of Ishida and Tabuchi does not explicitly disclose, "Wherein the dummy pillar extends from the surface layer to the first isolation layer." Barwicz discloses, "Wherein the dummy pillar extends from the surface layer to the first isolation layer" (p. [0017] and Fig. 1, pts. 200 and 201). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida and Tabuchi with the teachings of Barwicz for the reasons provided above regarding claim 2.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ishida, in view of Tabuchi, and further in view of Tsuji (US Pub. 2020/0412086).
Regarding claim 7, The combination of Ishida and Tabuchi does not explicitly disclose, "Wherein the dummy pillar is electrically isolated from the carrier." Tsuji discloses, "Wherein the dummy pillar is electrically isolated from the carrier" (p. [0040], [0077], [0093], and Figs. 1A and 10B, pts. 18 and 50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida and Tabuchi with the teachings of Tsuji. In view of the teachings of Ishida regarding a VCSEL array including multiple connection pillars and the teachings of Tabuchi regarding the use of alignment pillars to assist with alignment, the additional configuration the alignment elements to be electrically isolated on both connection ends as taught by Tsuji would enhance the teachings of Ishida and Tabuchi by allowing accidental electrical currents through the alignment pillars to be avoided.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ishida, in view of Tabuchi, and further in view of Mathai et al. (Mathai, US Patent 9,798,087).
Regarding claim 12, The combination of Ishida and Tabuchi does not explicitly disclose, "Wherein the surface layer comprises a redistribution layer." Mathai discloses, "Wherein the surface layer comprises a redistribution layer" (col. 4-5, lines 60-3 and Fig. 2, pts. 220 and 222). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida and Tabuchi with the teachings of Mathai. In view of the teachings of Ishida regarding a VCSEL array including multiple connection pillars, the additional inclusion of an RDL layer on the carrier to which the lasers are mounted as taught by Mathai would enhance the teachings of Ishida and Tabuchi by allowing signals to be routed from the connection points to elsewhere in the carrier chip to facilitate further connections.
The combination of Ishida, Tabuchi, and Mathai does not explicitly disclose, "[The redistribution layer] configured to decrease a pitch of the plurality of second electrical contacts." Mathai teaches that an RDL layer may be used for routing electrical signals to or from an optoelectronic device mounted thereon (col. 4, lines 61-67). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the pitch of the traces within the RDL layer such that the traces provide a reduction in pitch at for the second electrodes so as to facilitate external connections by exhibiting a larger pitch between external connections than between the second electrodes, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 18 through 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ishida, in view of Tabuchi, and further in view of Han et al. (Han, US Pub. 2011/0085760).
Regarding claim 18, Ishida discloses, "Assembling a vertical cavity surface emitting laser (VCSEL) chip in a flip chip configuration with a carrier to produce an emitter assembly" (p. [0066] and Fig. 4, pts. 120 and 140). "Wherein a plurality of conductive pillars electrically connect the VCSEL chip and the carrier" (p. [0066] and Fig. 4, pts. 121, 122, 123, 155, and 157). "Wherein the plurality of conductive pillars extend from respective electrical contacts of a first plurality of contacts of the VCSEL chip or from respective electrical contacts of a second plurality of electrical contacts of the carrier" (p. [0066] and Fig. 4, pts. 121, 122, 123, 155, and 157). Ishida does not explicitly disclose, "Wherein one of the VCSEL chip or the carrier comprises a dummy pillar." "[The dummy pillar] electrically isolated from the VCSEL chip and the carrier." "The other of the VCSEL chip or the carrier comprises a slot for the dummy pillar." "Wherein the dummy pillar extends from a first isolation layer of the VCSEL chip to a surface layer of the carrier, or extends from the surface layer of the carrier to the first isolation layer." Tabuchi discloses, "Wherein one of the VCSEL chip or the carrier comprises a dummy pillar" (col. 3, lines 58-64 and Fig. 6A, pt. 23a). "[The dummy pillar] electrically isolated from the VCSEL chip and the carrier" (col. 4, lines 17-20 and Fig. 6A, pts. 23a and 206). "The other of the VCSEL chip or the carrier comprises a slot for the dummy pillar" (col. 4, lines 21-31 and Figs. 6A and 6B, pts. 14 and 23a). "Wherein the dummy pillar extends from a first isolation layer of the VCSEL chip to a surface layer of the carrier, or extends from the surface layer of the carrier to the first isolation layer" (col. 4, lines 17-20 and Fig. 6A, pts. 23a and 206). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Tabuchi for the reasons provided above regarding claim 1.
The combination of Ishida and Tabuchi does not explicitly disclose, "Performing a solder reflow procedure on the emitter assembly." Han discloses, "Performing a solder reflow procedure on the emitter assembly" (p. [0059] and Figs 1A and 1B, pt. 140c, where this melting of solder 140c is a solder reflow process). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida and Tabuchi with the teachings of Han. In view of the teachings of Ishida regarding a VCSEL array including multiple connection pillars and the teachings of Tabuchi regarding the inclusion of alignment pillars in the form of bumps, the additional inclusion of steps specific to attaching solder bumps as taught by Han would enhance the teachings of Ishida and Tabuchi by allowing the bumps of Tabuchi to be more securely attached.
Regarding claim 19, Ishida does not explicitly disclose, "Wherein assembling the VCSEL chip in the flip chip configuration with the carrier comprises assembling the VCSEL chip in the flip chip configuration with the carrier such that the dummy pillar mates with the slot." Tabuchi discloses, "Wherein assembling the VCSEL chip in the flip chip configuration with the carrier comprises assembling the VCSEL chip in the flip chip configuration with the carrier such that the dummy pillar mates with the slot" (col. 4, lines 21-31 and Figs. 6A and 6B, pts. 14 and 23a). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Tabuchi for the reasons provided above regarding claim 1.
Regarding claim 20, The combination of Ishida and Tabuchi does not explicitly disclose, "Applying solder flux on the carrier prior to assembling the VCSEL chip in the flip chip configuration with the carrier." Han discloses, "Applying solder flux on the carrier prior to assembling the VCSEL chip in the flip chip configuration with the carrier" (p. [0073], [0074], and Fig. 2E, pts. 130, 140b, and 140c). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida and Tabuchi with the teachings of Han for the reasons provided above regarding claim 18.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SEAN P HAGAN/Examiner, Art Unit 2828
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