DETAILED ACTION
Claims 1 through 20 originally filed 31 March 2023. Claims 1 through 20 are addressed by this action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(u)(1).
Each of figures 2, 3, 4, and 5 include multiple views that are not separately labeled. Each view must be individually labeled.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 7 through 11, 13, and 17 through 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ishida et al. (Ishida, US Pub. 2021/0399523), in view of Han et al. (Han, US Pub. 2011/0085760), and further in view of Tsuji (US Pub. 2020/0412086).
Regarding claim 1, Ishida discloses, "A vertical cavity surface emitting laser (VCSEL) chip comprising a plurality of VCSELs" (p. [0046] and Fig. 6, pts. 140 and 159). "A plurality of conductive pillars electrically connected to the VCSEL chip" (p. [0047] and Figs. 4 and 6, pts. 155, 157, and 159). Ishida does not explicitly disclose, "A dummy pillar." "[The dummy pillar] mating with a slot." "Wherein the VCSEL chip includes one of the dummy pillar or the slot." Han discloses, "A dummy pillar" (p. [0059] and Figs 1A and 1B, pts. 136 and 140c). "[The dummy pillar] mating with a slot" (p. [0059] and Figs 1A and 1B, pts. 119, 136, and 140c). "Wherein the VCSEL chip includes one of the dummy pillar or the slot" (p. [0059] and Figs 1A and 1B, pts. 130, 136, and 140c). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Han. In view of the teachings of Ishida regarding a VCSEL array including multiple connection pillars, the additional inclusion of alignment pillars to assist with alignment as taught by Han would enhance the teachings of Ishida by allowing for improved alignment between the laser chip and the carrier.
The combination of Ishida and Han does not explicitly disclose, "[The dummy pillar] electrically isolated from the VCSEL chip." Tsuji discloses, "[The dummy pillar] electrically isolated from the VCSEL chip" (p. [0040] and Fig. 1A, pt. 50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida and Han with the teachings of Tsuji. In view of the teachings of Ishida regarding a VCSEL array including multiple connection pillars and the teachings of Han regarding the use of alignment pillars to assist with alignment, the configuration of the alignment elements as dummy elements that are electrically isolated from the device as taught by Tsuji would enhance the teachings of Ishida and Han by allowing the alignment pillars to be employed exclusively for alignment without accommodating electrical connections.
Regarding claim 3, Ishida does not explicitly disclose, "Wherein a step is defined in the slot." Han discloses, "Wherein a step is defined in the slot" (p. [0054] and Fig. 1B, pts. 118 and 119, where trench 119 includes has a step structure that extends from the top of terrace 118 to the bottom of trench 119). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Han for the reasons provided above regarding claim 1.
Regarding claim 4, Ishida discloses, "A carrier" (p. [0066] and Fig. 4, pts. 121, 122, and 123). "Wherein the plurality of conductive pillars electrically connect the VCSEL chip and the carrier" (p. [0066] and Fig. 4, pts. 121, 122, 123, 155, and 157).
Regarding claim 7, The combination of Ishida and Han does not explicitly disclose, "Wherein the dummy pillar is electrically isolated from the VCSEL chip and electrically isolated from the carrier." Tsuji discloses, "Wherein the dummy pillar is electrically isolated from the VCSEL chip and electrically isolated from the carrier" (p. [0040] and Fig. 1A, pt. 50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida and Han with the teachings of Tsuji for the reasons provided above regarding claim 1.
Regarding claim 8, The combination of Ishida, Han, and Tsuji does not explicitly disclose, "Wherein each of the plurality of conductive pillars has a maximum diameter less than 25 micrometers." It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to dimension the conductive pillars to within the noted range so as to balance minimizing the overall footprint of the device against minimum practical dimensions of the pillars, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 9, Ishida discloses, "A vertical cavity surface emitting laser (VCSEL) chip comprising a plurality of VCSELs" (p. [0046] and Fig. 6, pts. 140 and 159). "[The plurality of VCSELs] in a bottom-emitting configuration" (p. [0046], [0061], [0068] and Figs. 3 and 5, pts. 141, 150a, and 162, where light is emitted from lasers 150a through substrate 141 toward lenses 162 in a manner consistent with bottom-emitting devices). "Wherein the plurality of VCSELs are respectively associated with a plurality of first electrical contacts" (p. [0047] and Fig. 6, pts. 159). "A carrier having a plurality of second electrical contacts" (p. [0066] and Fig. 4, pts. 121, 122, and 123). "Wherein the VCSEL chip is in a flip chip configuration with the carrier" (p. [0066] and Fig. 4, pts. 120 and 140). "A plurality of conductive pillars that electrically connect the plurality of first electrical contacts and the plurality of second electrical contacts" (p. [0047], [0066], and Fig. 4, pts. 121, 122, 123, 155, 157, and 159). Ishida does not explicitly disclose, "A dummy pillar." "Wherein the dummy pillar extends from one of the VCSEL chip or the carrier and mates with a slot of the other of the VCSEL chip or the carrier." Han discloses, "A dummy pillar" (p. [0059] and Figs 1A and 1B, pts. 136 and 140c). "Wherein the dummy pillar extends from one of the VCSEL chip or the carrier and mates with a slot of the other of the VCSEL chip or the carrier" (p. [0059] and Figs 1A and 1B, pts. 119, 130, 136, and 140c). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Han for the reasons provided above regarding claim 1.
The combination of Ishida and Han does not explicitly disclose, "[The dummy pillar] is electrically isolated from the plurality of first electrical contacts and the plurality of second electrical contacts." Tsuji discloses, "[The dummy pillar] is electrically isolated from the plurality of first electrical contacts and the plurality of second electrical contacts" (p. [0040] and Fig. 1A, pt. 50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida and Han with the teachings of Tsuji for the reasons provided above regarding claim 1.
Regarding claim 10, Ishida discloses, "Wherein the carrier comprises an integrated circuit chip or a substrate" (p. [0066] and Fig. 4, pt. 120).
Regarding claim 11, Ishida does not explicitly disclose, "Wherein the carrier comprises a surface layer and a base layer." "Wherein the dummy pillar extends from one of the VCSEL chip or the surface layer and mates with the slot of the other of the VCSEL chip or the surface layer." Han discloses, "Wherein the carrier comprises a surface layer and a base layer" (p. [0048], [0049], and Fig. 1B, pts. 110 and 112). "Wherein the dummy pillar extends from one of the VCSEL chip or the surface layer and mates with the slot of the other of the VCSEL chip or the surface layer" (p. [0049], [0059], and Fig. 1B, pts. 112, 118, 119, and 140c). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Han for the reasons provided above regarding claim 1.
Regarding claim 13, Ishida discloses, "Wherein the plurality of conductive pillars extend from the VCSEL chip to the carrier" (p. [0066] and Figs. 4 and 11G, pts. 120, 155, and 157). Ishida does not explicitly disclose, "Wherein the dummy pillar extends from the VCSEL chip." Han discloses, "Wherein the dummy pillar extends from the VCSEL chip" (p. [0059] and Figs 1A and 1B, pts. 130, 136, and 140c). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Han for the reasons provided above regarding claim 1.
Regarding claim 17, The combination of Ishida, Han, and Tsuji does not explicitly disclose, "Wherein a spacing of the plurality of first electrical contacts defines a pitch that is less than 45 micrometers." It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to dimension the spacing between the contacts to within the noted range so as to balance minimizing the overall footprint of the device against minimum practical pitch between the contacts, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 18, Ishida discloses, "Assembling a vertical cavity surface emitting laser (VCSEL) chip in a flip chip configuration with a carrier to produce an emitter assembly" (p. [0066] and Fig. 4, pts. 120 and 140). "Wherein a plurality of conductive pillars electrically connect the VCSEL chip and the carrier" (p. [0066] and Fig. 4, pts. 121, 122, 123, 155, and 157). Ishida does not explicitly disclose, "Wherein one of the VCSEL chip or the carrier comprises a dummy pillar." "The other of the VCSEL chip or the carrier comprises a slot for the dummy pillar." "Performing a solder reflow procedure on the emitter assembly." Han discloses, "Wherein one of the VCSEL chip or the carrier comprises a dummy pillar" (p. [0059] and Figs 1A and 1B, pts. 136 and 140c). "The other of the VCSEL chip or the carrier comprises a slot for the dummy pillar" (p. [0059] and Figs 1A and 1B, pts. 119, 136, and 140c). "Performing a solder reflow procedure on the emitter assembly" (p. [0059] and Figs 1A and 1B, pt. 140c, where this melting of solder 140c is a solder reflow process). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Han for the reasons provided above regarding claim 1.
The combination of Ishida and Han does not explicitly disclose, "[The dummy pillar] electrically isolated from the VCSEL chip and the carrier." Tsuji discloses, "[The dummy pillar] electrically isolated from the VCSEL chip and the carrier" (p. [0040] and Fig. 1A, pt. 50). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida and Han with the teachings of Tsuji for the reasons provided above regarding claim 1.
Regarding claim 19, Ishida does not explicitly disclose, "Wherein assembling the VCSEL chip in the flip chip configuration with the carrier comprises assembling the VCSEL chip in the flip chip configuration with the carrier such that the dummy pillar mates with the slot." Han discloses, "Wherein assembling the VCSEL chip in the flip chip configuration with the carrier comprises assembling the VCSEL chip in the flip chip configuration with the carrier such that the dummy pillar mates with the slot" (p. [0059] and Figs 1A and 1B, pts. 119, 136, and 140c). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Han for the reasons provided above regarding claim 1.
Regarding claim 20, Ishida does not explicitly disclose, "Applying solder flux on the carrier prior to assembling the VCSEL chip in the flip chip configuration with the carrier." Han discloses, "Applying solder flux on the carrier prior to assembling the VCSEL chip in the flip chip configuration with the carrier" (p. [0073], [0074], and Fig. 2E, pts. 130, 140b, and 140c). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Han for the reasons provided above regarding claim 1.
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ishida, in view of Han, in view of Tsuji, and further in view of Barwicz et al. (Barwicz, US Pub. 2018/0358778).
Regarding claim 2, The combination of Ishida, Han, and Tsuji does not explicitly disclose, "Wherein the slot comprises a hollow extension from the VCSEL chip." Barwicz discloses, "Wherein the slot comprises a hollow extension from the VCSEL chip" (p. [0017] and Fig. 1, pts. 50b, 50c, and 201). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida, Han, and Tsuji with the teachings of Barwicz. In view of the teachings of Ishida regarding a VCSEL array including multiple connection pillars and the teachings of Han regarding the use of alignment pillars to assist with alignment, the alternate configuration of the alignment pillar to extend from the carrier to a slot in on the emitter chip as taught by Barwicz would enhance the teachings of Ishida, Han, and Tsuji by indicating a suitably alternate arrangement for the alignment pillar.
Regarding claim 14, Ishida discloses, "Wherein the plurality of conductive pillars extend from the VCSEL chip to the carrier" (p. [0066] and Figs. 4 and 11G, pts. 120, 155, and 157).
The combination of Ishida, Han, and Tsuji does not explicitly disclose, "Wherein the dummy pillar extends from the carrier." Barwicz discloses, "Wherein the dummy pillar extends from the carrier" (p. [0017] and Fig. 1, pts. 200 and 201). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida, Han, and Tsuji with the teachings of Barwicz for the reasons provided above regarding claim 2.
Claims 5, 6, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ishida, in view of Han, in view of Tsuji, and further in view of Tabuchi (US Patent 5,909,524).
Regarding claim 5, The combination of Ishida, Han, and Tsuji does not explicitly disclose, "Wherein the slot comprises a recess in a surface layer of the carrier." Tabuchi discloses, "Wherein the slot comprises a recess in a surface layer of the carrier" (col. 4, lines 21-46 and Fig. 6B, pts. 2, 10, and 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida, Han, and Tsuji with the teachings of Tabuchi. In view of the teachings of Ishida regarding a VCSEL array including multiple connection pillars and the teachings of Han regarding the use of alignment pillars to assist with alignment, the alternate configuration of the alignment slot to be recessed into the carrier substrate and the alternate configuration of the conductive connection pillar to the laser to extend from the carrier substrate to the laser as taught by Tabuchi would enhance the teachings of Ishida, Han, and Tsuji by indicating suitably alternate arrangements for the alignment pillar and the conductive connection pillar.
Regarding claim 6, The combination of Ishida, Han, and Tsuji does not explicitly disclose, "Wherein the slot comprises a recess extending through a surface layer of the carrier into a base layer of the carrier." Tabuchi discloses, "Wherein the slot comprises a recess extending through a surface layer of the carrier into a base layer of the carrier" (col. 4, lines 21-46 and Fig. 6B, pts. 2, 10, and 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida, Han, and Tsuji with the teachings of Tabuchi for the reasons provided above regarding claim 5.
Regarding claim 16, Ishida does not explicitly disclose, "Wherein the dummy pillar extends from the VCSEL chip." Han discloses, "Wherein the dummy pillar extends from the VCSEL chip" (p. [0059] and Figs 1A and 1B, pts. 130, 136, and 140c). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Ishida with the teachings of Han for the reasons provided above regarding claim 1.
The combination of Ishida, Han, and Tsuji does not explicitly disclose, "Wherein the plurality of conductive pillars extend from the carrier to the VCSEL chip." Tabuchi discloses, "Wherein the plurality of conductive pillars extend from the carrier to the VCSEL chip" (col. 4, lines 32-39 and Fig. 6B, pts. 15c and 16). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida, Han, and Tsuji with the teachings of Tabuchi for the reasons provided above regarding claim 5.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ishida, in view of Han, in view of Tsuji, and further in view of Mathai et al. (Mathai, US Patent 9,798,087).
Regarding claim 12, The combination of Ishida, Han, and Tsuji does not explicitly disclose, "Wherein the surface layer comprises a redistribution layer." Mathai discloses, "Wherein the surface layer comprises a redistribution layer" (col. 4-5, lines 60-3 and Fig. 2, pts. 220 and 222). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida, Han, and Tsuji with the teachings of Mathai. In view of the teachings of Ishida regarding a VCSEL array including multiple connection pillars, the additional inclusion of an RDL layer on the carrier to which the lasers are mounted as taught by Mathai would enhance the teachings of Ishida, Han, and Tsuji by allowing signals to be routed from the connection points to elsewhere in the carrier chip to facilitate further connections.
The combination of Ishida, Han, Tsuji, and Mathai does not explicitly disclose, "[The redistribution layer] configured to decrease a pitch of the plurality of second electrical contacts." Mathai teaches that an RDL layer may be used for routing electrical signals to or from an optoelectronic device mounted thereon (col. 4, lines 61-67). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the pitch of the traces within the RDL layer such that the traces provide a reduction in pitch at for the second electrodes so as to facilitate external connections by exhibiting a larger pitch between external connections than between the second electrodes, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ishida, in view of Han, in view of Tsuji, in view of Barwicz, and further in view of Tabuchi.
Regarding claim 15, The combination of Ishida, Han, and Tsuji does not explicitly disclose, "Wherein the dummy pillar extends from the carrier." Barwicz discloses, "Wherein the dummy pillar extends from the carrier" (p. [0017] and Fig. 1, pts. 200 and 201). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida, Han, and Tsuji with the teachings of Barwicz for the reasons provided above regarding claim 2.
The combination of Ishida, Han, Tsuji, and Barwicz does not explicitly disclose, "Wherein the plurality of conductive pillars extend from the carrier to the VCSEL chip." Tabuchi discloses, "Wherein the plurality of conductive pillars extend from the carrier to the VCSEL chip" (col. 4, lines 32-39 and Fig. 6B, pts. 15c and 16). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of Ishida, Han, Tsuji, and Barwicz with the teachings of Tabuchi. In view of the teachings of Ishida regarding a VCSEL array including multiple connection pillars and the teachings of Han regarding the use of alignment pillars to assist with alignment, the alternate configuration of the conductive connection pillar to the laser to extend from the carrier substrate to the laser as taught by Tabuchi would enhance the teachings of Ishida, Han, Tsuji, and Barwicz by indicating a suitably alternate arrangement for the conductive connection pillar.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Buchmann et al. (Buchmann, US Patent 5,319,725) is cited for teaching various techniques for employing alignment pillars and matching slots.
Mori et al. (Mori, US Pub. 2020/0412089) is cited for teaching the additional use of alignment pillars as physical supports when mounting a laser device.
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/SEAN P HAGAN/Examiner, Art Unit 2828
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