DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 1a in the reply filed on 04/06/2026 is acknowledged.
Claims 5,12 and 18-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group and Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on04/06/2026.
Priority
Examiner acknowledges priority to provisional application 63/386,527 filed on 12/08/2022.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/04/2025 and 04/06/2026 were filed after the filing date of the claimed application on 03/31/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “first quantity of the multiple pins corresponds to a second quantity of the plurality of VCSELs” as recited in claim 7 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 7 and 8, the claims require “a second quantity of the plurality of VCSELs”. When using ordinal designations, it is necessary to start with an initial ordinal designation such as "first" and introduce further elements in numerical order from that point. Failure to adhere to such an ordering creates the implication of additional elements without strictly indicating the presence thereof. Due to this implication, it is unclear whether or not the claim actually requires the presence of the implied features. As such, this claim is deemed indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. For the remainder of this action, this claim will be interpreted as requiring no elements other than those explicitly stated.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4,6,7,9-11,13-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (hereinafter Yu) (US 20200014169 A1) in view of Tan (US 20130285261 A1).
Regarding claim 1, Yu discloses in Fig. 21
An emitter assembly [300] (Para. [0032]), comprising:
a vertical cavity surface emitting laser (VCSEL) chip [100] (Para. [0010] comprising a plurality of VCSELs [104] (Para. [0010]);
a plurality of conductive pillars [208] (Para. [0030]) electrically connected to the VCSEL chip [100] (Paras. [0031,0032]),
wherein a conductive pillar [208] (Para. [0030]), of the plurality of conductive pillars [208] (Para. [0031]), has a solder cap [210] (Para. [0031]) at an end of the conductive pillar [210 on top of 208] (Para. [0031]); and
Yu fails to disclose,
a pin extending into the solder cap
Tan discloses in Fig. 1A,
a pin [115] (Para. [0010]) extending from a VCSEL chip [110] (Para. [0009]) into a solder cap [120] (Para. [0010])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement pins from the VCSEL chip extending into the solder caps of Yu as shown in Tan for the purpose of further electrically connecting the two chips. (Tan Para. [0010])
Regarding claim 2, Yu in view of Tan disclose the device outlined in the rejection of claim 1 above and further discloses,
wherein the pin [Tan 115 Fig. 1A] (Tan Para. [0010]) extends from the VCSEL chip [Yu 100 Fig. 21] (Yu Para. [0010]) into the solder cap [Yu 210 Fig. 21] (Para. [0031]).
Regarding claim 3, Yu in view of Tan disclose the device outlined in the rejection of claim 1 above and further discloses,
wherein the pin [Tan 115 Fig. 1A] (Tan Para. [0010]) is electrically connected to an electrical contact [Yu 114 Fig. 21] (Yu Para. [0017]) associated with a VCSEL [104] of the plurality of VCSELs [104] (Yu Para. [0010]).
Tan discloses pin [115] to be formed of metallic conducting material in Para. [0010])
Regarding claim 4, Yu in view of Tan disclose the device outlined in the rejection of claim 1 above and further discloses in Yu Fig. 21,
a carrier [200] (Para. [0029]),
wherein the plurality of conductive pillars [208] electrically connect the VCSEL chip [100] and the carrier [200] (Para. [0030,0034]).
Regarding claim 6, Yu in view of Tan disclose the device outlined in the rejection of claim 1 above and further discloses
wherein the pin [Tan 115 Fig. 1A] is electrically connected to the conductive pillar and to the VCSEL chip.
Tan discloses pin [115] to be formed of metallic conducting material in Para. [0010])
Regarding claim 7, Yu in view of Tan disclose the device outlined in the rejection of claim 1 above and further discloses
wherein the pin [Tan 115 Fig. 1A] (Tan Para. [0010]) is one of multiple pins [Tan 115 Fig. 1A] (Tan Para. [0010]), and
wherein a first quantity of the multiple pins [Tan 115 Fig. 1A] (Tan Para. [0010]) corresponds to a second quantity of the plurality of VCSELs [Yu 104 Fig. 21] (Yu Para. [0010]).
Tan shows one pin [115] for each solder bump [120] in Fig. 1A (Para. [0010])
Regarding claim 9, Yu in view of Tan disclose the device outlined in the rejection of claim 1 above and further discloses in Yu Fig. 21,
wherein each of the plurality of conductive pillars [208] (Para. [0030]) has a maximum diameter less than 25 micrometers (Para. [0022]).
Fig. 4 of Yu shows a width [WL] of the VCSEL [104 Fig. 21] and discloses [WL] to be 14µm in Para. [0022]. Fig. 21 shows the pillars [208] to have a smaller width value than the width of the VCSEL [104] and therefore the width of the pillars must be at least less than 14µm.
Regarding claim 10, Yu discloses in Fig. 21
An emitter assembly [300] (Para. [0032]), comprising:
a vertical cavity surface emitting laser (VCSEL) chip [100] (Para. [0010]) comprising a plurality of VCSELs [104] (Para. [0010]) in a bottom-emitting configuration (Para. [0014]),
wherein the plurality of VCSELs [104] (Para. [0010]) are respectively associated with a plurality of first electrical contacts [114] (Para. [0017]);
a carrier [200] (Para. [0029]) having a plurality of second electrical contacts [204A] (Para. [0030]),
wherein the VCSEL chip [100] is in a flip chip configuration with the carrier [200] (Paras. [0033,0034]) (see Figs. 7-9);
a plurality of conductive pillars [208] (Para. [0030]) that electrically connect the plurality of first electrical contacts [114] and the plurality of second electrical contacts [204A] (Paras. [0029,0049]),
wherein a conductive pillar [208], of the plurality of conductive pillars [208], has a solder cap [210] (Para. [0031]) at an end of the conductive pillar [208] (Para. [0031]);
Yu fails to disclose,
a pin extending from one of the VCSEL chip or the carrier into the solder cap.
Tan discloses in Fig. 1A,
a pin [115] (Para. [0010]) extending from a VCSEL chip [110] (Para. [0009]) into a solder cap [120] (Para. [0010])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement pins from the VCSEL chip extending into the solder caps of Yu as shown in Tan for the purpose of further electrically connecting the two chips. (Tan Para. [0010])
Examiner notes the interpretation of claim 10 is understood to be “… a pin extending from the VCSEL chip”
Regarding claim 11, Yu in view of Tan discloses the device outlined in the rejection of claim 10 above and further discloses in Yu Fig. 21,
wherein the carrier [200] comprises an integrated circuit chip (Para. [0029]) or a substrate.
Examiner notes the interpretation of claim 11 is understood to be “wherein the carrier comprises an integrated circuit chip”
Regarding claim 13, Yu in view of Tan discloses the device outlined in the rejection of claim 10 above and further discloses,
wherein the plurality of conductive pillars [Yu 208 Fig. 21] (Yu Para. [0030]) extend from the carrier [Yu 200 Fig. 21] to the VCSEL chip [Yu 100 Fig. 21] (Yu Para. [0030] (See Yu Fig. 8), and
wherein the pin [Tan 115 Fig. 1A] (Tan Para. [0010]) extends from the VCSEL chip [Yu 100 Fig. 21].
Regarding claim 14, Yu in view of Tan discloses the device outlined in the rejection of claim 10 above and further discloses,
wherein the pin [Tan 115 Fig. 1A] is electrically connected to an electrical contact [Yu 114 Fig. 21A] (Yu Para. [0017]), of the plurality of first electrical contacts [Yu 114 Fig. 21A] (Yu Para. [0017]), associated with a VCSEL [Yu 104 Fig. 21] (Yu Para. [0010]) of the plurality of VCSELs [Yu 104 Fig. 21] (Yu Para. [0010]).
Tan discloses pin [115] to be formed of metallic conducting material in Para. [0010])
Regarding claim 15, Yu in view of Tan discloses the device outlined in the rejection of claim 10 above and further discloses,
wherein the pin [Tan 115 Fig. 1A] (Tan Para. [0010]) is electrically connected to the conductive pillar [Yu 208 Fig. 21] (Yu Para. [0030]) , to the VCSEL chip [100], and to the carrier [200] (Yu Paras. [0029,0049]).
Tan discloses pin [115] to be formed of metallic conducting material in Para. [0010])
Regarding claim 17, Yu in view of Tan discloses the device outlined in the rejection of claim 10 above and further discloses in Yu Fig. 21,
wherein a spacing of the plurality of first electrical contacts [114] (Para. [0017]) defines a pitch that is less than 45 micrometers (Para. [0022]).
Paragraph [0022] of Yu discloses a width [WL] of a VCSEL structure [104] to be about 14µm and a spacing [D1] between adjacent VCSEL structures [104] to be a potential value of 4µm (see Yu Fig. 4). Therefore, with a width value of 14µm and a spacing distance of 4µm, the pitch between adjacent first electrical contacts is at least less than 45micrometers.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Tan as applied to claim 1 above, and further in view of Ishida et al. (hereinafter Ishida) (US 20210399523 A1).
Regarding claim 8, Yu in view of Tan discloses the device outlined in the rejection of claim 1 above and further discloses in Tan Fig. 1,
wherein the pin [115] is one of multiple pins [115] (Tan Para. [0010])
Yu in view of Tan fails to disclose,
wherein a first quantity of the multiple pins is less than a second quantity of the plurality of VCSELs.
Ishida discloses in Fig. 3,
Wherein a first quantity of bonding portions [123] (Para. [0086]) is less than a second quantity of a plurality of VCSELs [150a] (Para. [0061])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement an amount of bonding portions lower than an amount of VCSELs for the purpose of allowing electrical connection of multiple VCSELs from a single bonding portion. (Ishida Para. [0063])
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Tan as applied to claim 10 above, and further in view of Mathai et al. (hereinafter Mathai) (US 20210141171 A1).
Regarding claim 16, Yu in view of Tan discloses the device outlined in the rejection of claim 10 above and further discloses in Yu Fig. 21,
wherein the carrier comprises a surface layer [204] and a base layer [202], and
Yu in view of Tan fails to disclose,
wherein the surface layer comprises a redistribution layer configured to decrease a pitch of the plurality of second electrical contacts.
Mathai discloses in Fig. 4,
a surface layer [452] (Para. [0059]) comprising a redistribution layer allowing improved accessibility for electrical contact (Para. [0059])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the redistribution layer disclosed in Mathai into the surface layer of Yu in view of Tan for the purpose of allowing offset of the electrical connections for improved accessibility. (Mathai Para. [0059])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(US 20200191828 A1) discloses pins with a plurality of pin shapes placed into a solder portion. (see PTO-892 form)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNTER J NELSON whose telephone number is (571)270-5318. The examiner can normally be reached Mon-Fri. 8:30am-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached at (571) 272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/H.J.N./Examiner, Art Unit 2828 /TOD T VAN ROY/Primary Examiner, Art Unit 2828
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