DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of group I in the reply filed on 2/6/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 11-15 and 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0169065 (Carson).
For claim 1, Carson teaches an emitter assembly (fig. 2-3 and 27-29), comprising:
a vertical cavity surface emitting laser (VCSEL) chip (fig. 2, 100, [0053]; detailed in fig. 3, [0055]; and fig. 27-29, [0084]) comprising a plurality of VCSELs (fig. 27, 103; [0084]) in a bottom-emitting configuration (fig. 3 and [0075], “emit light through the surface of the substrate”),
wherein multiple VCSELs, of the plurality of VCSELs, are grouped in a cluster (fig. 27 shows two clusters of VCSELs 103 separated by gap 175);
a carrier (fig. 2, 200), wherein the VCSEL chip is in a flip chip configuration with the carrier (fig. 2 and [0075]); and
a conductive pillar electrically connected to the multiple VCSELs grouped in the cluster (fig. 29, 132 over cluster region, [0084], contact post, i.e. pillar).
For claim 2, Carson teaches the carrier comprises an integrated circuit chip or a substrate (fig. 2, bottom layer of 200 is a substrate).
For claim 3, Carson teaches the carrier comprises a surface layer and a base layer (fig. 2, bottom layer of 200 is a base layer), and wherein the surface layer comprises a redistribution layer (fig. 2, top layer of 200 under “-“ is a redistribution layer).
For claim 4, Carson teaches the conductive pillar has a solder cap at an end of the conductive pillar (fig. 12 and 29, cap 136 over post 132, [0072]), and wherein the solder cap surrounds the multiple VCSELs (fig. 27 and 29).
For claim 5, Carson teaches the conductive pillar has a solder cap at an end of the conductive pillar fig. 12 and 29, cap 136 over post 132, [0072]), and wherein the solder cap is electrically connected to the multiple VCSELs ([0083]).
For claim 6, Carson teaches the conductive pillar (fig. 29, 132; part of device 100) electrically connects the cluster of the multiple VCSELs (fig. 27, 103; part of device 100) and the carrier (fig. 2, 200).
For claim 7, Carson teaches the conductive pillar extends from the VCSEL chip (fig.12 illustrates the pillar 132 extending from the VCSEL chip below) to the carrier (fig. 2, 200 and [0071]).
For claim 8, Carson teaches the conductive pillar (fig. 29, 132; part of device 100) extends from the carrier (fig. 2, 200) to the VCSEL chip (fig. 27, 103; part of device 100).
For claim 11, Carson teaches a vertical cavity surface emitting laser (VCSEL) chip (fig. 2, 100, [0053]; detailed in fig. 3, [0055]; and fig. 27-29, [0084]), comprising: a plurality of VCSELs (fig. 27, 103; [0084]) in a bottom-emitting configuration (fig. 3 and [0075], “emit light through the surface of the substrate”),
wherein multiple VCSELs, of the plurality of VCSELs, are grouped in a cluster (fig. 27 shows two clusters of VCSELs 103 separated by gap 175); and
an electrical contact shared by the multiple VCSELs grouped in the cluster (fig. 28, 130a, [0083]-[0084]),
wherein the electrical contact is electrically connected to the multiple VCSELs ([0083]), and wherein the electrical contact is configured to electrically connect to a conductive pillar that provides electrical connection of the VCSEL chip (post 132, [0083]) and a carrier (fig. 2, 200).
For claim 12, Carson teaches the multiple VCSELs grouped in the cluster are arranged in a row (fig. 27, the cluster can be considered to include a single row VCSELs rather than all VCSELs above or below gap 175).
For claim 13, Carson teaches the multiple VCSELs grouped in the cluster are arranged non-linearly (fig. 27, the VCSELs in the cluster above gap 175 are arranged in a triangular lattice rather than a line).
For claim 14, Carson teaches the electrical contact (fig. 28, 130a) is outside of a region occupied by the multiple VCSELs grouped in the cluster (fig. 27, VCSELs 103 in a cluster corresponding to 130a).
For claim 15, Carson teaches the multiple VCSELs are multiple first VCSELs, the cluster is a first cluster (fig. 27, cluster above gap 175), and the electrical contact is a first electrical contact (fig. 28, 130a above gap),
wherein multiple second VCSELs, of the plurality of VCSELs, are grouped in a second cluster (fig. 27, cluster below gap 175), and
wherein the VCSEL chip further comprises: a second electrical contact, electrically isolated from the first electrical contact, shared by the multiple second VCSELs, wherein the second electrical contact is electrically connected to the multiple second VCSELs (fig. 28, 130a below gap, [0085]).
For claim 21, Carson teaches a method, comprising:
emitting a beam with a device (abstract, “multibeam arrays”) comprising:
a plurality of vertical cavity surface emitting lasers (VCSELs) (fig. 27, 103; [0084]) in a bottom-emitting configuration (fig. 3 and [0075], “emit light through the surface of the substrate”),
wherein multiple VCSELs, of the plurality of VCSELs, are grouped in a cluster(fig. 27 shows two clusters of VCSELs 103 separated by gap 175);
a carrier (fig. 2, 200),
wherein the device is in a flip chip configuration with the carrier (fig. 2 and [0075]); and
a conductive pillar electrically connected to the multiple VCSELs grouped in the cluster (fig. 29, 132 over cluster region, [0084], contact post, i.e. pillar).
For claim 22, Carson teaches the conductive pillar has a solder cap at an end of the conductive pillar (fig. 12 and 29, cap 136 over post 132, [0072]), and wherein the solder cap surrounds the multiple VCSELs (fig. 27 and 29).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9-10 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0169065 (Carson) in view of US 9,310,553 (Braunisch).
For claim 9, Carson does not teach underfill between the VCSEL chip and the carrier.
However, Braunisch teaches underfill between an the VCSEL chip and the carrier in order to encapsulate the interconnect structure (fig. 2, 214; col. 6, l. 45-48).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the underfill of Braunisch with the invention of Carson in order to encapsulate the interconnect structure.
For claim 10, Carson does not teach a thermal element aligned with the multiple VCSELs grouped in the cluster, wherein the thermal element is separated from the VCSEL chip by the underfill.
However, Braunisch teaches a thermal element (fig. 2, 210) aligned with a vcsel device (fig. 2, 206), wherein the thermal element is separated from the VCSEL chip by the underfill (fig. 2, 214) in order to perform electro-optic functions and encapsulate the interconnect structure (col. 6, l. 9-10; col. 6, l. 45-48).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the thermal element and underfill of Braunisch with the invention of Carson in order to ) in order to perform electro-optic functions and encapsulate the interconnect structure.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0169065 (Carson).
For claim 16, Carson does not teach a spacing of the plurality of VCSELs defines a pitch that is less than 45 micrometers. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention was made to minimize the pitch less than 45 micrometer in order to make a compact device, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over US 2020/0169065 (Carson) in view of US 2023/0054034 (Chua).
For claim 23, Carson does not teach the device comprises an integrated circuit (IC) driver chip, and wherein the VCSEL in configured with a finer pitch than the IC driver chip. However, Chua teaches emitting a beam with a VCSEL array device the device comprises an integrated circuit (IC) driver chip, and wherein the VCSEL in configured with a finer pitch than the IC driver chip (fig. 17, [0042]) in order to allow a laser device with tighter spacing than typical contact pads on a driver chip which drives the laser ([0088]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the driver and pitches of Chua with the invention of Carson in order to drive a laser with tighter spacing than typical contact pads on a driver chip.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2020/0326425, US 2010/0303113, and US 2021/0320478 all teach clustered elements.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael W Carter whose telephone number is (571)270-1872. The examiner can normally be reached M-F, 9:00-5:30.
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/Michael Carter/ Primary Examiner, Art Unit 2828