Prosecution Insights
Last updated: August 08, 2026
Application No. 18/194,237

METHODS, APPARATUS, AND ARTICLES OF MANUFACTURE TO GROUP DESIGN STAGES IN DESIGN SPACE OPTIMIZATION OF SEMICONDUCTOR DESIGN FOR TOOL AGNOSTIC DESIGN FLOWS

Non-Final OA §102
Filed
Mar 31, 2023
Examiner
NGO, BRIAN
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
868 granted / 987 resolved
+27.9% vs TC avg
Moderate +12% lift
Without
With
+12.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 2m
Avg Prosecution
11 currently pending
Career history
995
Total Applications
across all art units

Statute-Specific Performance

§101
19.5%
-20.5% vs TC avg
§103
36.4%
-3.6% vs TC avg
§102
34.2%
-5.8% vs TC avg
§112
7.2%
-32.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 987 resolved cases

Office Action

§102
CTNF 18/194,237 CTNF 77920 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION This Non-Final office is a response to the papers filed on 03/31/2023. Claims 1-20 are pending. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim s 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sawlani et al. (US 20200226742 A1) . Regarding claims 1 , 8, and 15., Sawlani discloses: An apparatus to group design stages in design space optimization of semiconductor design (see Abstract, analysis system that may be implemented in multiple stages…, , par [0074], multiple classifications for all defects, and/or multiple classifications for different groupings of defects ….), the apparatus comprising: interface circuitry (see Fig. 1A-1B); first instructions (see par [0004], program instructions for executing on the one or more processors, the program instructions including: one or more first stage defect classification engines…, see par [0017-0024]); and processor circuitry to at least one of instantiate or execute the first instructions to (see par [0004-0006], program instructions for executing on the one or more processors, the program instructions including: one or more first stage defect classification engines…, see par [0017-0024]): parse a file to identify a first design stage of a design flow and a second design stage of the design flow, the first design stage and the second design stage corresponding to a class of design stages (see par [0003-0004], The analysis may be conducted in multiple levels or stages. After each analysis level, the defect classification accuracy can be significantly increased….., first stage defect classification engines configured to:…., a second stage defect classification engine configured to: receive the first stage….., [wherein first stage and second stage have been identified], see par [0058-0061]); generate, based on a dictionary file, a group of operations to perform the first design stage and the second design stage, the dictionary file associated with the first design stage and the second design stage, (see par [0004-0005], par [0009], the first stage defect classification engines are configured to receive sensor data including environmental conditions of the fabrication process, changes in the mass of the substrate,……, see par [0058-0061], “second stage defect classification engine” takes as input, and operates on, defect classifications from at least one first stage classification engine. Such inputs may include defect composition….[wherein metrology data is dictionary file], see par [0039-0040]); generate adjusted parameters for experimenting on the class of design stages, the adjusted parameters based on the group of operations , (see par [0008], the second stage defect classification engine is additionally configured to further classify the defects on the substrate and/or provide suggested corrective actions to reduce generation of defects…., see par [0014], using the first stage defect classification and the manufacturing information, further classifying the defect on the substrate and/or providing suggested corrective actions to reduce generation of defects…., [wherein corrective actions to reduce generation of defects which is generate adjusted parameters], see par [0082-0083]); and generate second instructions based on the group of operations and the adjusted parameters (see par [0079-0080], The information in the data store 132 may also include information …. of defects and corrective actions……, the second stage defect classification engine 130 is configured to perform an analysis using information from the data store 132 , including outputs from first stage defect classification engine(s)….). Regarding claims 2 , 9, and 16, Sawlani discloses: wherein the processor circuitry is to determine the dictionary file associated with the first design stage and the second design stage (see par [0004-0005], par [0009], the first stage defect classification engines are configured to receive sensor data including environmental conditions of the fabrication process, changes in the mass of the substrate,……, see par [0039-0040]). Regarding claims 3 , 10, and 17, Sawlani discloses: wherein to determine the dictionary file, the processor circuitry is to identify (a) a first variable of the first design stage on which to experiment and (b) a second variable of the second design stage on which to experiment (see par [0039-0046], metrology data include sensor data such as temperature, environmental conditions within the chamber, change in the mass of the substrate or reactor components, mechanical forces, and the like…., see par [0009-0012], see par [0052-0055]). Regarding claims 4 , 11, and 18., Sawlani discloses: wherein to determine the dictionary file, the processor circuitry is to identify (a) a first operation of the first design stage and (b) a second operation of the second design stage (see Par [0004-0005], one or more first stage defect classification engines configured to: receive metrology data acquired for defects on a substrate…., a second stage defect classification engine configured to: receive the first stage defect classification produced by the one or more first stage defect classification engines…., see par [0009-0011]). Regarding claims 5 , 12, and 19, Sawlani discloses: wherein to generate the group of operations, the processor circuitry is to adjust (a) the first operation of the first design stage and (b) the second operation of the second design stage (see par [0014-0016], providing suggested corrective actions to reduce generation of defects on the substrate and/or reduce occurrences of defects on substrates…, see par [0008-0011], second stage defect classification engine is additionally configured to further classify the defects on the substrate and/or provide suggested corrective actions to reduce generation of defects on the substrate and/or reduce occurrences of defects on substrates …., see par [0082-0084]). Regarding claims 6 , 13, and 20, Sawlani discloses: wherein to determine the dictionary file, the processor circuitry is to identify (a) first parameters for experimenting on the first design stage and (b) second parameters for experimenting on the second design stage (see par [0039-0046], metrology data include sensor data such as temperature, environmental conditions within the chamber, change in the mass of the substrate or reactor components, mechanical forces, and the like….). Regarding claims 7 and 14, Sawlani discloses: wherein to generate the adjusted parameters for experimenting on the class of design stages, the processor circuitry is to adjust (a) the first parameters of the first design stage and (b) the second parameters of the second design stage based on the group of operations (see par [0014], providing suggested corrective actions to reduce generation of defects on the substrate and/or reduce occurrences of defects on substrates…, see par [0008], second stage defect classification engine is additionally configured to further classify the defects on the substrate and/or provide suggested corrective actions to reduce generation of defects on the substrate and/or reduce occurrences of defects on substrates ….). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN NGO whose telephone number is (571)270-7011. The examiner can normally be reached M-F 7AM-4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 5712727483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRIAN NGO/ Primary Examiner, Art Unit 2851 Application/Control Number: 18/194,237 Page 2 Art Unit: 2851 Application/Control Number: 18/194,237 Page 3 Art Unit: 2851 Application/Control Number: 18/194,237 Page 4 Art Unit: 2851 Application/Control Number: 18/194,237 Page 5 Art Unit: 2851 Application/Control Number: 18/194,237 Page 6 Art Unit: 2851 Application/Control Number: 18/194,237 Page 7 Art Unit: 2851 Application/Control Number: 18/194,237 Page 8 Art Unit: 2851
Read full office action

Prosecution Timeline

Mar 31, 2023
Application Filed
Sep 07, 2023
Response after Non-Final Action
May 14, 2026
Non-Final Rejection mailed — §102
Jul 27, 2026
Examiner Interview Summary
Jul 27, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
99%
With Interview (+12.4%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 987 resolved cases by this examiner. Grant probability derived from career allowance rate.

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