Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of the Information Disclosure Statement dated 04/03/2023. All of the cited references have been considered.
Drawings
The drawings have been received on 04/03/2023. These drawings are accepted.
CRM
Examiner is interpreting computer readable medium as non-transitory in view of paragraph 0113 of the Specification.
Claim Objections
Claim 9 is objected to because of the following informalities:
In claim 9, “wherein a COBYLA optimization algorithm or a SPSA optimization algorithm is used the determination of parameters of the simplified pulse schedule.” Should read “wherein a COBYLA optimization algorithm or a SPSA optimization algorithm is used for the determination of parameters of the simplified pulse schedule.”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Such claim limitation(s) is/are:
“a digital processor” in claims 10 and 11.
“an evaluating unit” in claim 11.
“a selection module” in claim 11.
“a generator” in claim 11.
“a determination unit” in claim 11.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
The term “best” in claims 1, 11 and 20 is a relative term which renders the claim indefinite. The term “best” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
The term “efficient” in claims 1, 11 and 20 is a relative term which renders the claim indefinite. The term “efficient” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
The term “more complex” in claims 4 and 14 is a relative term which renders the claim indefinite. The term “more complex” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Dependent claims 2-10 and 12-19 do not resolve the issue and are rejected with the same rationale.
Claims 10 and 11 recite “a digital processor”; However, the digital processor performs these functions because it comprises of these other digital processors. The digital processor does not have sufficient structure. For the purposes of examination, Examiner will interpret digital processor as generic computing components.
Claim 11 recites “an evaluating unit”; However, the evaluating unit performs these functions because it comprises of these other digital processors. The evaluating unit does not have sufficient structure because the other digital processors do not have sufficient structure. For the purposes of examination, Examiner will interpret evaluating unit as generic computing components.
Claim 11 recites “a selection module”. However, the selection module performs these functions because it comprises of these other digital processors. The selection module does not have sufficient structure because the other digital processors do not have sufficient structure. For the purposes of examination, Examiner will interpret evaluating unit as generic computing components.
Claim 11 recites “a generator”. However, the generator performs these functions because it comprises of these other digital processors. The generator does not have sufficient structure because the other digital processors do not have sufficient structure. For the purposes of examination, Examiner will interpret evaluating unit as generic computing components.
Claim 11 recites “a determination unit”. However, the determination unit performs these functions because it comprises of these other digital processors. The determination unit does not have sufficient structure because the other digital processors do not have sufficient structure. For the purposes of examination, Examiner will interpret evaluating unit as generic computing components.
Dependent claims 12-19 do not resolve the issue and are rejected with the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 6, 8, 11, 12, 15, 16, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Asthana et al. (Minimizing state preparation times in pulse-level variational molecular simulations); hereinafter Asthana in view of Hwang et al. (US20220374579A1); hereinafter Hwang in further view of Jin et al. (US20220027774A1); hereinafter Jin
Claim 1 is rejected over Asthana, Hwang and Jin.
Regarding claim 1, Asthana teaches a computer-implemented method for a resource-efficient pulse-based variational quantum circuit running on a selected quantum hardware to solve a given predefined problem, the method comprising: (Asthana [Section I. Introduction]: “better understood and significantly improved by establishing connections with quantum optimal control theory (QOC) [43–47]. VQAs involve the optimization of parameters in discrete quantum circuit logic elements, whereas QOC functions more broadly to optimize a time dependent drive Hamiltonian, typically by determining optimal pulse shapes of applied fields.”)
determining a simplified pulse schedule of the pulse sequence, thereby producing an efficient pulse-based schedule that acts as a pulse-based variational form for the best performing quantum circuit. (Asthana [Section B. Minimum evolution time and time-optimal controls]: “In the present study, we numerically find T∗ and the associated time-optimal controls by starting at a large enough pulse duration and reducing the pulse duration until we find the shortest pulse at which the system can reach the target state to the desired accuracy. The pulse is divided into many step-wise constant segments with practical bounds on amplitudes and frequencies. Dividing the pulse into many adjustable segments provides a large amount of freedom in shaping the pulse, essentially allowing the ctrl-VQE algorithm to choose any possible optimal pulse shape in the optimization process.”)
Asthana does not appear to explicitly teach controlling an execution of a plurality of different quantum circuits using a selected quantum hardware for a given predefined problem to be solved;
evaluating a performance of each of the plurality of different quantum circuits;
selecting a best performing one of the plurality of quantum circuits;
However, Hwang teaches controlling an execution of a plurality of different quantum circuits using a selected quantum hardware for a given predefined problem to be solved; (Hwang [0020]: “The measuring of the performances of the candidate quantum circuits includes measuring a performance of a first candidate quantum circuit. The measuring of the performance of the first candidate quantum circuit includes measuring attenuations of fidelity between inputs and outputs of the first candidate quantum circuit and selecting the greatest attenuation of the fidelity as a performance of the first candidate quantum circuit.”; and [0021]: “In an embodiment, the measuring of the performances of the candidate quantum circuits includes measuring a performance of a first candidate quantum circuit. The measuring of the performance of the first candidate quantum circuit includes measuring passages of time between inputs and outputs of the first candidate quantum circuit and selecting the longest passage of the time as a performance of the first candidate quantum circuit.”)
evaluating a performance of each of the plurality of different quantum circuits; (Hwang [0019]: “the operating method of a computing device further includes measuring performances of the candidate quantum circuits and determining a candidate quantum circuit, which has the highest performance, from among the candidate quantum circuits as a quantum circuit.”)
selecting a best performing one of the plurality of quantum circuits; (Hwang [0019]: “the operating method of a computing device further includes measuring performances of the candidate quantum circuits and determining a candidate quantum circuit, which has the highest performance, from among the candidate quantum circuits as a quantum circuit.”)
It would have been obvious before the effective filing date to combine the optimal pulses of Asthana with the candidate selection of quantum circuits of Hwang for high and uniform performance (Hwang [0005]). Asthana and Hwang are analogous art because they both concern quantum computing.
Asthana does not appear to explicitly teach generating a pulse sequence having a pulse schedule tailored to the selected quantum hardware and the given problem for the best performing one of the [plurality of different quantum circuits; and]
However, Jin teaches generating a pulse sequence having a pulse schedule tailored to the selected quantum hardware and the given problem for the best performing one of the [plurality of different quantum circuits; and] (Jin [0039]: “an optimal pulse database of multiple quantum hardware structures is established in advance, and after the target quantum hardware structure is determined, the optimal control pulse set matching the relevant physical parameters of the target quantum hardware structure may be selected from the preset mapping information”)
It would have been obvious before the effective filing date to combine the optimal pulses of Asthana with the optimal pulse control of Jin to improve the fidelity of a target control pulse sequence (Jin, [0040]). Asthana and Jin are analogous art because they both concern pulses in quantum computing.
Claim 2 is rejected over Asthana, Hwang and Jin with the incorporation of claim 1.
Regarding claim 2, Asthana teaches simplifying the given predefined problem. (Asthana [Abstract]: “Here, we find the shortest possible pulses for ctrl-VQE to prepare target molecular wavefunctions for a given device Hamiltonian describing coupled transmon qubits.”; Note: The Hamiltonian is the given predefined problem.)
Claim 5 is rejected over Asthana, Hwang and Jin with the incorporation of claim 1.
Regarding claim 5, Asthana teaches reducing an active time for a scheduled pulse. (Asthana [Figure 2]: “(a) How the optimized pulse shape changes for a two-qubit system as the pulse duration is reduced from 20.00 ns to 15.00 ns.”)
Claim 6 is rejected over Asthana, Hwang and Jin with the incorporation of claim 1.
Regarding claim 6, Asthana teaches wherein the selected quantum hardware comprises a physical two-qubit gate. (Asthana [Figure 2]: “(a) How the optimized pulse shape changes for a two-qubit system as the pulse duration is reduced from 20.00 ns to 15.00 ns.”)
Claim 8 is rejected over Asthana, Hwang and Jin with the incorporation of claim 1.
Regarding claim 8, Asthana teaches wherein the quantum circuit is used for a simplified and optimized physical two-qubit gate and (Asthana [Figure 2]: “(a) How the optimized pulse shape changes for a two-qubit system as the pulse duration is reduced from 20.00 ns to 15.00 ns.”)
a determination of a molecular energy level of a molecule. (Asthana [Section III. Computational Details]: “As a test system for our simulations, we have chosen the problem of finding the ground state energy of the H2 molecule at a bond distance of 1.5
A
˙
, which has relatively strong correlations. Molecular integrals are generated using PySCF [56] and STO-3G basis set is used in this work.”)
Claim 11 is rejected over Asthana, Hwang and Jin.
Regarding claim 11, Asthana teaches a quantum information processing system for executing a resource-efficient pulse-based variational quantum circuit running on a selected quantum hardware to solve a given predefined problem, the system comprising:
a digital processor operationally coupled to a digital memory which stores instructions, which when executed, controls the following components: (Asthana [Section V. Summary]: “In this paper, we presented time-optimal control fields that prepare target molecular ground states on trans-mon quantum processors. These optimal controls were obtained using the pulse-level VQE algorithm known as ctrl-VQE.”)
The remainder of claim 11 is claim 1 in the form of a processing system and is rejected for the same reasons as claim 1 stated above.
Dependent claim 12 is claim 2 in the form of a processing system and is rejected for the same reasons as claim 2 stated above. For the rejection of the limitations specifically pertaining to the processing system of claim 11, see the rejection of claim 11 above.
Dependent claim 15 is claim 5 in the form of a processing system and is rejected for the same reasons as claim 5 stated above. For the rejection of the limitations specifically pertaining to the processing system of claim 11, see the rejection of claim 11 above.
Dependent claim 16 is claim 6 in the form of a processing system and is rejected for the same reasons as claim 6 stated above. For the rejection of the limitations specifically pertaining to the processing system of claim 11, see the rejection of claim 11 above.
Dependent claim 18 is claim 8 in the form of a processing system and is rejected for the same reasons as claim 8 stated above. For the rejection of the limitations specifically pertaining to the processing system of claim 11, see the rejection of claim 11 above.
Claim 20 is rejected over Asthana, Hwang and Jin.
Regarding claim 20, Asthana teaches a computer program product for a resource-efficient pulse-based variational quantum circuit running on a selected quantum hardware to solve a given predefined problem, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions being executable by one or more computing systems or controllers to cause the one or more computing systems to perform a method comprising: (Asthana [Section I. Introduction]: “better understood and significantly improved by establishing connections with quantum optimal control theory (QOC) [43–47]. VQAs involve the optimization of parameters in discrete quantum circuit logic elements, whereas QOC functions more broadly to optimize a time dependent drive Hamiltonian, typically by determining optimal pulse shapes of applied fields.”)
The remainder of claim 20 is claim 1 in the form of a computer program product and is rejected for the same reasons as claim 1 stated above.
Claims 3, 7, 13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Asthana, Hwang and Jin and in further view of Coury et al. (US20030169041A1); hereinafter Coury
Claim 3 is rejected over Asthana, Hwang, Jin and Coury with the incorporation of claim 1.
Regarding claim 3, Asthana teaches wherein the determination of the simplified pulse schedule comprises:
at least one selected out of a group comprising:
changing a shape of the pulse. (Asthana [Section B. Minimum evolution time and time-optimal controls]: “The pulse is divided into many step-wise constant segments with practical bounds on amplitudes and frequencies. Dividing the pulse into many adjustable segments provides a large amount of freedom in shaping the pulse, essentially allowing the ctrl-VQE algorithm to choose any possible optimal pulse shape in the optimization process.”)
Asthana does not appear to explicitly teach at least one selected out of a group comprising:
removing at least a pulse from the pulse schedule;
adding pulses to the pulse schedule; and
However, Coury teaches at least one selected out of a group comprising:
removing at least a pulse from the pulse schedule; (Coury [0070]: “In some embodiments of the invention, these rules include commutation of fundamental operators, removal of empty time units, and removal of redundant pulse sequences or replacement of such pulse sequences by simplified pulse sequences.”)
adding pulses to the pulse schedule; and (Coury [0070]: “In some embodiments of the invention, these rules include commutation of fundamental operators, removal of empty time units, and removal of redundant pulse sequences or replacement of such pulse sequences by simplified pulse sequences.”; Note: Replacement of pulse sequences is also adding.)
It would have been obvious before the effective filing date to combine the optimal pulses of Asthana with the removal of redundant pulse sequences of Coury to optimize the sequence of fundamental operations (Coury, [0070]). Asthana and Coury are analogous art because they both concern pulses in quantum computing.
Claim 7 is rejected over Asthana, Hwang, Jin and Coury with the incorporation of claim 1.
Regarding claim 7, Asthana does not appear to explicitly teach wherein the selected quantum hardware uses error correction and/or error mitigation.
However, Coury teaches wherein the selected quantum hardware uses error correction and/or error mitigation. (Coury [0072]: “wherein a plurality of physical qubits can be used to encode a single qubit state, such that the state is protected from errors during the computation. Such algorithms can include aspects similar to classical error correction algorithms”)
It would have been obvious before the effective filing date to combine the optimal pulses of Asthana with the removal of redundant pulse sequences of Coury to optimize the sequence of fundamental operations (Coury, [0070]). Asthana and Coury are analogous art because they both concern pulses in quantum computing.
Dependent claim 13 is claim 3 in the form of a processing system and is rejected for the same reasons as claim 3 stated above. For the rejection of the limitations specifically pertaining to the processing system of claim 11, see the rejection of claim 11 above.
Dependent claim 17 is claim 7 in the form of a processing system and is rejected for the same reasons as claim 7 stated above. For the rejection of the limitations specifically pertaining to the processing system of claim 11, see the rejection of claim 11 above.
Claims 4 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Asthana, Hwang and Jin and in further view of Meng et al. (US20230087100A1); hereinafter Meng
Claim 4 is rejected over Asthana, Hwang, Jin and Meng with the incorporation of claim 1.
Regarding claim 4, Asthana does not appear to explicitly teach using a single Gaussian pulse as a replacement for more complex pulse shapes.
However, Meng teaches using a single Gaussian pulse as a replacement for more complex pulse shapes. (Meng [0049]: “Therefore, it can be seen that C.sub.1 decides the relationship between the single pulse duration and the pulse amplitude, and also fixes the shape of the pulses to a certain extent. If a proper C.sub.1 is selected, it can be ensured that the shape of the Gaussian pulses is relatively regular, and thus it is easier to realize in experiments. In the method according to the present disclosure, the impact of the single pulse duration T.sub.k(l) is considered, and thus a total pulse duration may be dynamically adjusted through parameter optimization to be as short as possible.”)
It would have been obvious before the effective filing date to combine the optimal pulses of Asthana with the gaussian pulse of Meng for effective parameter optimization for pulse duration (Meng [0049]). Asthana and Meng are analogous art because they both concern pulse and quantum computing.
Dependent claim 14 is claim 4 in the form of a processing system and is rejected for the same reasons as claim 4 stated above. For the rejection of the limitations specifically pertaining to the processing system of claim 11, see the rejection of claim 11 above.
Claims 9, 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Asthana, Hwang and Jin and in further view of Antonio et al. (US20190095811A1); hereinafter Antonio
Claim 9 is rejected over Asthana, Hwang, Jin and Antonio with the incorporation of claim 1.
Regarding claim 9, Asthana does not appear to explicitly teach wherein a COBYLA optimization algorithm or a SPSA optimization algorithm is used the determination of parameters of the simplified pulse schedule.
However, Antonio teaches wherein a COBYLA optimization algorithm or a SPSA optimization algorithm is used the determination of parameters of the simplified pulse schedule. (Antonio [0058]: “The energy estimates are then used, in one or more examples, by a gradient descent algorithm that relies on a simultaneous perturbation stochastic approximation (SPSA) to update the control parameters. The SPSA algorithm approximates the gradient using only two energy measurements, regardless of the dimensions of the parameter space p, achieving a level of accuracy comparable to standard gradient descent methods, in the presence of stochastic fluctuations. The technical solutions thus facilitate optimizing over multiple qubits and long depths for trial state preparation, thus facilitating optimizations over a number of parameters, for example p=30.”)
It would have been obvious before the effective filing date to combine the optimal pulses of Asthana with the simultaneous perturbation stochastic approximation (SPSA) of Antonio for accurate optimization (Antonio [0076]). Asthana and Antonio are analogous art because they both concern pulses in quantum computing.
Claim 10 is rejected over Asthana, Hwang, Jin and Antonio with the incorporation of claim 1.
Regarding claim 10, Asthana does not each wherein the COBYLA optimization algorithm or the SPSA optimization algorithm is each performed by a digital processor.
However, Antonio teaches wherein the COBYLA optimization algorithm or the SPSA optimization algorithm is each performed by a digital processor. (Antonio [0026]: “FIG. 2 is an example of a quantum computer 200 (quantum hardware) that can process the output from the computer 100 according to embodiments of the present invention. A quantum processor is a computing device that can harness quantum physical phenomena (such as superposition, entanglement, and quantum tunneling) unavailable to non-quantum devices. A quantum processor may take the form of a superconducting quantum processor. A superconducting quantum processor may include a number of qubits and associated local bias devices, for instance two or more superconducting qubits. An example of a qubit is a flux qubit. A superconducting quantum processor may also employ coupling devices (i.e., “couplers”) providing communicative coupling between qubits.”; and [0029]: “Now turning back to FIG. 1, an example illustrates a computer 100, e.g., any type of computer system configured to execute algorithm(s) (including various mathematical computation as understood by one skilled in the art) for encoding quantum Hamiltonians on a set of qubits, as discussed herein, such that the result can be input to the quantum computer 200. The computer 100 can be a distributed computer system over more than one computer. Various methods, procedures, modules, flow diagrams, tools, applications, circuits, elements, and techniques discussed herein can also incorporate and/or utilize the capabilities of the computer 100. Indeed, capabilities of the computer 100 can be utilized to implement elements of exemplary embodiments discussed herein.)
It would have been obvious before the effective filing date to combine the optimal pulses of Asthana with the simultaneous perturbation stochastic approximation (SPSA) of Antonio for accurate optimization (Antonio [0076]). Asthana and Antonio are analogous art because they both concern pulses in quantum computing.
Conclusion
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/DAVID H TRAN/Examiner, Art Unit 2147
/VIKER A LAMARDO/Supervisory Patent Examiner, Art Unit 2147