DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The present application, 18194894, filed 04/03/2023 claims foreign priority to IN202341017683, filed 03/16/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/03/2023, 02/29/2024 and 11/05/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification is objected to under 37 C.F.R. 1.74, which requires the detailed description to refer to the different parts of the figures by use of reference letters or reference numerals. Implicit in this rule is that the detailed description correctly reference the figures. In this application the figures and detailed description are inconsistent as explained below.
A. In paragraph [0044] line 2, “206” should read “406” instead.
Claim Objections
Claim 11 is objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 11 line 1, “MOS” should read “metal-oxide semiconductor (MOS)” instead to define how the acronym is to be interpreted.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-5 and 8-9 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Hwang et al. (US 20220236950 A1), hereinafter Hwang. Hwang is cited in the IDS submitted on 04/03/2023.
Regarding claim 1, Hwang teaches a Full Adder (FA) circuit, comprising:
a sum generation circuit configured to generate a sum output (S) (Hwang Fig. 3 and paragraphs [0035-0036] sum generation circuit – 10 and 20; sum output – sum); and
a carry output generation circuit configured to generate a carry output (CO) (Hwang Fig. 3 and paragraphs [0035, 0037] carry output generation circuit – 10 and 30; carry output – carry),
wherein each of the sum generation circuit and the carry output generation circuit is configured to receive a first operand input (A), a second operand input (B), and a carry input (CI) (Hwang Fig. 3 and paragraphs [0035-0037] first operand input – input_A; a second operand input – input_B; carry input – input_C),
wherein the sum generation circuit comprises a first exclusive-NOR gate and a second exclusive-NOR gate, wherein the second exclusive-NOR gate is configured to receive an output of the first exclusive-NOR gate to produce the sum output (S) (Hwang Fig. 3 and paragraphs [0035-0036, 0040]; first exclusive-NOR gate – 10; second exclusive-NOR gate – 20/21; an output of the first exclusive-NOR gate – sig_B), and
wherein the carry output generation circuit comprises a first or-and-invert (OAI) gate, a second or-and-invert (OAI) gate, and a NAND gate (Hwang Fig. 3 and paragraphs [0035, 0037] first or-and-invert (OAI) gate – 12; second or-and-invert (OAI) gate – 32; NAND gate – 11),
wherein the first OAI gate is configured to receive an output of the NAND gate to generate one of an exclusive-NOR output or a NOR output of the first operand (A) and the second operand (B) (Hwang Fig. 3 and paragraphs [0035, 0040] “The first OAI gate 12 may perform an XNOR operation on the first input signal INPUT_A and the second input signal INPUT_B based on the first internal signal SIG_A, the first input signal INPUT_ A, and the second input signal INPUT_B … The first OAI gate 12 of the first logic gate group 10 may perform a logic operation on the first input signal INPUT_A, the second input signal INPUT_B, and the first internal signal SIG_A. Thus the first OAI gate 12 may generate the second internal signal SIG_B as a result of performing an XNOR operation on the first input signal INPUT_A and the second input signal INPUT_B”; output of the NAND gate – sig_A; exclusive-NOR output - sig_B), and
wherein the second OAI gate is configured to receive the output of the NAND gate, an inverse of the carry input, and the generated one of the exclusive-NOR output or the NOR output to produce the carry output (CO) (Hwang Fig. 3 and paragraph [0037] inverse of the carry input - inverted signal of the third input signal INPUT_C).
Regarding claim 2, Hwang teaches all the limitations of claim 1 as stated above. Further, Hwang teaches comprising: a maximum of 4 metal-oxide semiconductor (MOS) transistors configured to receive the first operand input (A); and a maximum of 5 MOS transistors configured to receive the second operand input (B) (Hwang Figs. 5-6 and paragraphs [0038, 0045-0047] “only the first logic gate group 10 receives the first input signal INPUT_A and the second input signal INPUT_B”; the first logic gate group 10 include 4 transistors for receiving input_A and 4 transistors for receiving input_B).
Regarding claim 4, Hwang teaches all the limitations of claim 1 as stated above. Further, Hwang teaches wherein when the first OAI gate is configured to generate the exclusive-NOR output, the first OAI gate comprises six MOS transistors (Hwang Fig. 6 and paragraph [0047] “the first OAI gate 12 according to an embodiment may include a combination of six transistors”).
Regarding claim 5, Hwang teaches all the limitations of claim 4 as stated above. Further, Hwang teaches wherein the six MOS transistors comprise two MOS transistors configured to receive the first operand input (A) and two other MOS transistors configured to receive the second operand input (B) (Hwang Fig. 6 and paragraph [0047]).
Regarding claim 8, Hwang teaches all the limitations of claim 1 as stated above. Further, Hwang teaches wherein the second OAI gate comprises six MOS transistors (Hwang Fig. 6 and paragraph [0047] “the second OAI gate 32 in the third logic gate group 30 may also be configured as the circuit diagram of FIG. 6”).
Regarding claim 9, Hwang teaches all the limitations of claim 8 as stated above. Further, Hwang teaches wherein the six MOS transistors of the second OAI gate comprises two MOS transistors configured to receive the output of the NAND gate, two other MOS transistors configured to receive the inverse of the carry input, and two remaining MOS transistors configured to receive the generated one of the exclusive-NOR output or the NOR output (Hwang Figs. 3, 6 and paragraph [0047]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-11, 13-14 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Hwang in view of Trommer et al. (NPL – “Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors”), hereinafter Trommer.
Regarding claim 10, Hwang teaches a Full Adder (FA) circuit, comprising:
a sum generation circuit configured to generate a sum output (Hwang Fig. 3 and paragraphs [0035-0036] sum generation circuit – 10 and 20; sum output – sum); and
a carry output generation circuit configured to generate a carry output (Hwang Fig. 3 and paragraphs [0035, 0037] carry output generation circuit – 10 and 30; carry output – carry),
wherein each of the sum generation circuit and the carry output generation circuit is configured to receive a first operand input, a second operand input, and a carry input (Hwang Fig. 3 and paragraphs [0035-0037] first operand input – input_A; a second operand input – input_B; carry input – input_C),
wherein the sum generation circuit comprises a first exclusive-NOR gate and a second exclusive-NOR gate, wherein the second exclusive-NOR gate is configured to receive an output of the first exclusive-NOR gate to produce the sum output (Hwang Fig. 3 and paragraphs [0035-0036, 0040]; first exclusive-NOR gate – 10; second exclusive-NOR gate – 20/21; an output of the first exclusive-NOR gate – sig_B), and
wherein the carry output generation circuit comprises a first OAI gate, a second OAI gate, and a NAND gate (Hwang Fig. 3 and paragraphs [0035, 0037] first or-and-invert (OAI) gate – 12; second or-and-invert (OAI) gate – 32; NAND gate – 11),
wherein the carry output generation circuit is configured such that one of:
the first OAI gate is configured to receive an output of the NAND gate to generate one of an exclusive-NOR output or a NOR output of the first operand and the second operand (Hwang Fig. 3 and paragraphs [0035, 0040] “The first OAI gate 12 may perform an XNOR operation on the first input signal INPUT_A and the second input signal INPUT_B based on the first internal signal SIG_A, the first input signal INPUT_ A, and the second input signal INPUT_B … The first OAI gate 12 of the first logic gate group 10 may perform a logic operation on the first input signal INPUT_A, the second input signal INPUT_B, and the first internal signal SIG_A. Thus the first OAI gate 12 may generate the second internal signal SIG_B as a result of performing an XNOR operation on the first input signal INPUT_A and the second input signal INPUT_B”; output of the NAND gate – sig_A; exclusive-NOR output - sig_B), and
the second OAI gate is configured to receive the output of the NAND gate, an inverse of the carry input, and the generated one of the exclusive-NOR output or the NOR output to produce the carry output (Hwang Fig. 3 and paragraph [0037] inverse of the carry input - inverted signal of the third input signal INPUT_C).
Hwang does not explicitly teach wherein the sum generation circuit comprises a first exclusive-OR gate and a second exclusive-OR gate, wherein the second exclusive-OR gate is configured to receive an output of the first exclusive-OR gate to produce the sum, and wherein the carry output generation circuit comprises a first and-or-invert (AOI) gate, a second and-or-invert (AOI) gate, and a NOR gate, wherein the carry output generation circuit is configured such that one of: the first AOI gate is configured to receive an output of the NOR gate to generate one of an exclusive-OR output or a NAND output of the first operand and the second operand, and the second AOI gate is configured to receive the output of the NOR gate, an inverse of the carry input, and the generated one of the exclusive-OR output or the NAND output to produce the carry output.
However, on the same field of endeavor, Trommer discloses a full-adder implementation using AOI based XOR gates wherein the XOR gate comprises a NOR gate followed by an AOI gate. Furthermore, the AOI based XOR gates is equivalent to an OAI based XNOR gate comprising a NAND gate followed by an OAI gate (Trommer Figs. 8-9 and section V and VI; XOR gate – NOR and AOI gate; AOI gate – AND gate and NOR gate).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Hwang using Trommer and configure the logic first group 10 to include a first exclusive-OR gate comprising of a NOR gate instead of the NAND gate 11 and a first AOI gate instead of the first OAI gate 12; the second logic group 20 to include a second exclusive-OR gate to receive an output of the first exclusive-OR gate and to produce the sum; and the third logic group to include a second and-or-invert (AOI) gate, wherein the carry output generation circuit is configured such that one of: the first AOI gate is configured to receive an output of the NOR gate to generate one of an exclusive-OR output of the first operand and the second operand, and the second AOI gate is configured to receive the output of the NOR gate, an inverse of the carry input, and the exclusive-
Therefore, the combination of Hwang as modified in view of Trommer teaches wherein the sum generation circuit comprises a first exclusive-OR gate and a second exclusive-OR gate, wherein the second exclusive-OR gate is configured to receive an output of the first exclusive-OR gate to produce the sum, and wherein the carry output generation circuit comprises a first and-or-invert (AOI) gate, a second and-or-invert (AOI) gate, and a NOR gate, wherein the carry output generation circuit is configured such that one of: the first AOI gate is configured to receive an output of the NOR gate to generate one of an exclusive-OR output or a NAND output of the first operand and the second operand, and the second AOI gate is configured to receive the output of the NOR gate, an inverse of the carry input, and the generated one of the exclusive- OR output or the NAND output to produce the carry output.
Regarding claim 11, Hwang as modified in view of Trommer teaches all the limitations of claim 10 as stated above. Further, Hwang as modified in view of Trommer teaches comprising a maximum of 4 MOS transistors configured to receive the first operand input, and a maximum of 5 MOS transistors configured to receive the second operand input (Hwang Figs. 5-6 and paragraphs [0038, 0045-0047] “only the first logic gate group 10 receives the first input signal INPUT_A and the second input signal INPUT_B”; the first logic gate group 10 include 4 transistors for receiving input_A and 4 transistors for receiving input_B).
Regarding claim 13, Hwang as modified in view of Trommer teaches all the limitations of claim 10 as stated above. Further, Hwang as modified in view of Trommer teaches wherein when the first AOI gate is configured to generate the exclusive-OR output, the first AOI gate comprises six MOS transistors (Hwang Fig. 6 and paragraph [0047] “the first OAI gate 12 according to an embodiment may include a combination of six transistors”). The motivation to combine is the same as claim 10.
Regarding claim 14, Hwang as modified in view of Trommer teaches all the limitations of claim 13 as stated above. Further, Hwang as modified in view of Trommer teaches wherein the six MOS transistors comprise two MOS transistors configured to receive the first operand input and two other MOS transistors configured to receive the second operand input (Hwang Fig. 6 and paragraph [0047]). The motivation to combine is the same as claim 10.
Regarding claim 17, Hwang as modified in view of Trommer teaches all the limitations of claim 10 as stated above. Further, Hwang as modified in view of Trommer teaches wherein the second AOI gate comprises six MOS transistors (Hwang Fig. 6 and paragraph [0047] “the second OAI gate 32 in the third logic gate group 30 may also be configured as the circuit diagram of FIG. 6”).
Regarding claim 18, Hwang as modified in view of Trommer teaches all the limitations of claim 17 as stated above. Further, Hwang as modified in view of Trommer teaches wherein the six MOS transistors of the second AOI gate comprises two MOS transistors configured to receive the output of the NOR gate, two other MOS transistors configured to receive the inverse of the carry input, and two remaining MOS transistors configured to receive the generated one of the exclusive-OR output or the NAND output (Hwang Figs. 3, 6 and paragraph [0047]).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang as applied to claim 1 above, and further in view of Elkin et al. (US 20210124558 A1), hereinafter Elkin. Elkin is cited in the IDS submitted on 02/29/2024.
Regarding claim 3, Hwang teaches all the limitations of claim 1 as stated above. Further, Hwang teaches comprising (Hwang Figs. 4-11 and paragraphs [0045, 0047 and 0049]). Further, Hwang teaches the circuit comprising 22 transistors not including the inverter (Hwang Figs. 4-11 and paragraphs [0045, 0047 and 0049]; 4 transistors for gate 11; 6 transistors for 12; 6 transistors for 32; and 6 transistors for 21 as shown in at least Figs. 5-7) .
Hwang does not explicitly teach comprising a maximum of 25 MOS transistors.
However, on the same field of endeavor, Elkin discloses an inverter implemented as two transistors (Elkin paragraph [0044] “An inverter in one embodiment may be built using two transistors”).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Hwang using Elkin to implement the inverter 31 in the third logic gate group 30 as two transistors such that the full adder circuit is built using 24 transistors in order to reduce the number of transistors compared to traditional full adder circuits [Elkin paragraph [0044]). Furthermore, inverter implementation using two transistors is well-known.
Therefore, the combination of Hwang as modified in view of Elkin teaches comprising a maximum of 25 MOS transistors.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Hwang in view of Trommer as applied to claim 10 above, and further in view of Elkin.
Regarding claim 12, Hwang as modified in view of Trommer teaches all the limitations of claim 10 as stated above. Further, Hwang as modified in view of Trommer teaches comprising (Hwang Figs. 4-11 and paragraphs [0045, 0047 and 0049]). Further, Hwang teaches the circuit comprising 22 transistors not including the inverter (Hwang Figs. 4-11 and paragraphs [0045, 0047 and 0049]; 4 transistors for gate 11; 6 transistors for 12; 6 transistors for 32; and 6 transistors for 21 as shown in at least Figs. 5-7) .
Hwang does not explicitly teach comprising a maximum of 25 MOS transistors.
However, on the same field of endeavor, Elkin discloses an inverter implemented as two transistors (Elkin paragraph [0044] “An inverter in one embodiment may be built using two transistors”).
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Hwang using Elkin to implement the inverter 31 in the third logic gate group 30 as two transistors such that the full adder circuit is built using 24 transistors in order to reduce the number of transistors compared to traditional full adder circuits (Elkin paragraph [0044]). Furthermore, inverter implementation using two transistors is well-known.
Therefore, the combination of Hwang as modified in view of Trommer and Elkin teaches comprising a maximum of 25 MOS transistors.
Allowable Subject Matter
Claims 6-7 and 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art discloses the configuration of a full adder comprising a carry output generation circuit comprising a first OAI gate wherein the first OAI gate is configured to receive an output of the NAND gate to generate an exclusive-NOR output of the first operand (A) and the second operand (B); and a full adder comprising a carry output generation circuit comprising a first and-or-invert (AOI) gate, wherein the carry output generation circuit is configured such that the first AOI gate is configured to receive an output of the NOR gate to generate an exclusive-OR output of the first operand and the second operand. However, none of the prior art references cited explicitly teach or suggest, in combination with other limitations of the claims, the features of a full adder comprising a carry output generation circuit comprising a first OAI gate wherein the first OAI gate is configured to receive an output of the NAND gate to generate one of an exclusive-NOR output or a NOR output of the first operand (A) and the second operand (B), “wherein when the first OAI gate is configured to generate the NOR output, the first OAI gate comprises seven MOS transistors” as recited in claim 6; a full adder comprising a carry output generation circuit comprising a first and-or-invert (AOI) gate, wherein the carry output generation circuit is configured such that one of: the first AOI gate is configured to receive an output of the NOR gate to generate one of an exclusive-OR output or a NAND output of the first operand and the second operand, “wherein when the first AOI gate is configured to generate the NAND output, the first AOI gate comprises six MOS transistors” as recited in claim 15.
Conclusion
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/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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