Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 5, 9-12, 14-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ye et al.(cited by applicant), hereafter referred to as “Ye”.
Regarding claims 1 and 14, in the embodiments of Figs. 5, 7, 10, and 17, Ye discloses:
A multi-chip module (paragraph [0071]) with a multi-mode power amplifier system (multi-mode power amplifier system 500 in Fig. 5, per claim 14), the multi-chip module comprising:
a power amplifier (Figs. 5, 7, 10, 17, variable gain amplifier 542, 700, 1502) on a compound semiconductor die (amplifier implemented on Si-Ge or GaAs ED-pHEMT die, a digital switched attenuator (DSA) implemented on an SOI die, paragraphs [0070]-[0071]), the power amplifier including a first power amplifier transistor (Fig. 7, one of the three groups of unit cells 702, 704, 706) and a second power amplifier transistor (Fig. 7, one of the three groups of unit cells 702, 704, 706), the power amplifier configured to amplify a radio frequency signal (signal input 720, per claim 1);
a bias circuit (1702 as exemplarily shown in Fig. 17) on the compound semiconductor die (bias circuit 1702 is part of variable gain amplifier circuit 1500 therefore 1702 is also implemented on Si-Ge or GaAs ED-pHEMT die, paragraphs [0070]-[0071], per claim 14), the bias circuit configured to bias the power amplifier (1502, the bias circuit exemplarily applicable for one of the amplifier sets 1502 of the amplifier system 700 of three different amplifier sets of Fig. 7 as per paragraph 0111) such that (i) the first power amplifier transistor and the second power amplifier transistor are on in a first mode (of the three different modes of the amplifier system of Fig. 7) and (ii) the first power amplifier transistor is on and the second power amplifier transistor is off in the second mode (Fig.7, paragraph [0084], the controller may select a mode by activate one of the unit cells 702, 704, 706); and
an output matching network (inductor 1048, capacitor 0144 and output balun transformer 1046 as exemplarily shown in Fig. 10 are all part of an output matching network) implemented at least partly on a semiconductor-on-insulator die (paragraph [0094], per claim 14), the output matching network configured to adjust an output matching impedance (an output matching network is known in the art to adjust output impedance for matching) for the power amplifier for the second mode relative to the first mode (paragraph [0095], input and output resistors 1030 and 1032 are used to adjust impedance to avoid input output losses during amplify modes), and
the compound semiconductor die and the semiconductor-on-insulator die being on a common substrate and packaged together with each other (paragraph [0070]-[0071], per claim 14).
Regarding claims 4 and 16, in the embodiments of Figs.10-14, Ye discloses:
the output matching network includes a switch (as shown in embodiments of Figs. 10-14 of Ye) configured to adjust the output matching impedance for the power amplifier for the second mode relative to the first mode (paragraph [0095], input and output resistors 1030 and 1032 are used to adjust impedance to avoid input output losses during amplify modes).
Regarding claims 5 and 17, in the embodiments of Figs.10-14, Ye discloses:
the switch is configured to include a capacitor (1044) in the output matching impedance (as shown in embodiments of Figs. 10-14) in the first mode and to not include the capacitor in the output matching impedance in the second mode (paragraph 0093).
Regarding claims 9 and 15, in the embodiments of Figs. 5, 7, 10, 17, Ye discloses:
the power amplifier is on a silicon germanium die and the switch is on a silicon-on-insulator die (paragraph [0070]).
Regarding claim 10, in the embodiments of Figs. 5 and 7, Ye discloses:
the power amplifier (700 in Fig. 7 which is a variable gain output stage (540) of amplifier 500 of FIG. 5) includes a gain stage (520, containing gain amplifier 522) and an output stage (540), the output stage including the first power amplifier transistor (one of the three groups of unit cells 702, 704, 706) and the second power amplifier transistor (one of the three groups of unit cells 702, 704, 706).
Regarding claim 11, in the embodiments of Figs. 5 and 7, Ye discloses:
the gain stage (520), (although shown as comprising a single amplification path, it is well within the scope of the Ye amplifier that a multiple path of variable gain associated with multiple modes of operation could be implemented for the gain stage 520 as well, such that a fourth power amplifier transistor) includes a third power amplifier transistor (one of the three groups of unit cells 702, 704, 706) and a fourth power amplifier transistor (one of the three groups of unit cells 702, 704, 706), and
the bias circuit (similar to the multimode bias circuit 1704) is configured to bias the gain stage such that (i) the third power amplifier transistor and the fourth power amplifier transistor are on in the first mode and (ii) the third power amplifier transistor is on and the fourth power amplifier transistor is off in the second mode.
Regarding claim 12, in the embodiments of Figs. 5, 7, and 17, Ye discloses:
the bias circuit (1702 in Fig. 17) is configured to provide a reference current (Iref) to the first power amplifier transistor (one of the three groups of unit cells 702, 704, 706), the reference current being different in the first mode than in the second mode (paragraphs [0109]-[0111]).
Regarding claim 20, in the embodiments of Figs. 5 and 7, Ye discloses:
A method of operating a multi-mode power amplifier system (such as 500 of Fig. 5), the method comprising:
amplifying a radio frequency signal (720, as shown in Fig. 7) in a first mode with a first power amplifier transistor (one of the three groups of unit cells 702, 704, 706) of a power amplifier and a second power amplifier transistor of the power amplifier (one of the three groups of unit cells 702, 704, 706);
adjusting a power amplifier signal path by deactivating the second power amplifier transistor and adjusting an output matching impedance for the power amplifier (Fig.7, paragraph 0084, the controller may select a mode by activate one of the unit cells 702, 704, 706 and deactivating the others); and
after said adjusting, amplifying the radio frequency signal in a second mode with the first power amplifier transistor while the second power amplifier transistor is deactivated, the output matching impedance being different for the second mode than for the first mode (paragraph [0095], input and output resistors 1030 and 1032 are used to adjust impedance to avoid input output losses during amplify modes).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ye et al. in view of Babcock et al. (both cited by the applicant), hereafter referred to as “Ye” and “Babcock”, respectively.
Regarding claims 2 and 3:
Although Ye doesn’t teach explicitly about wireless local area network (WLAN) and wireless personal area network (WPAN) modes for two of the three different modes, in a similar field of the endeavor by the same inventive entity Babcock et al. teaches in Figs. 38-41 multimode transceivers along with managing multimode cascode amplifiers (1350 in Fig. 54A) through multimode bias circuits (1355, Fig. 54A) to switch between WPAN system, (such as signals associated with one or more of Bluetooth, ZigBee, Z-Wave, Wireless USB, INSTEON, IrDA, or Body Area Network) or WLAN system (paragraphs, [0627], [0636], [0639], [0936]).
Therefore, per claim 2, a person of ordinary skill in the art would find it obvious to implement a multimode variable gain power amplifier system, such as, Ye’s to switch between WLAN and WPAN system, as the first and the second mode of operations to cover same device (transceiver) for multiple purposes, wherein per claim 3, the first mode is a Wi-Fi mode (WLAN) and the second mode is a Bluetooth mode (WPAN) (Babcock, paragraph [0639]).
Regarding claim 18, Ye discloses:
a multi-mode power amplifier system (multi-mode power amplifier system 500 in Fig. 5) including a power amplifier (Figs. 5, 7, 10, 17, variable gain amplifier 542, 700, 1502) with a first power amplifier (Fig. 7, one of the three groups of unit cells 702, 704, 706) transistor and a second power amplifier transistor (one of the three groups of unit cells 702, 704, 706), the power amplifier configured to amplify a radio frequency signal,
a bias circuit (1702 as exemplarily shown in Fig. 17) configured to bias the power amplifier (1502, the bias circuit exemplarily applicable for one of the amplifier sets 1502 of the amplifier system 700 of three different amplifier sets of Fig. 7 as per paragraph 0111) such that (i) the first power amplifier transistor and the second power amplifier transistor are on in a first mode (of the three different modes of the amplifier system of Fig. 7) and (ii) the first power amplifier transistor is on and the second power amplifier transistor is off in a second mode (Fig.7, paragraph 0084, the controller may select a mode by activate one of the unit cells 702, 704, 706), and
an output matching network (inductor 1048, capacitor 0144 and output balun transformer 1046 as exemplarily shown in Fig. 10 are all part of an output matching network) coupled to an output of the power amplifier (as can be seen in any of the amplifier systems of Figs. 10-14), the output matching network configured to adjust an output matching impedance (an output matching network is known in the art to adjust output impedance for matching) for the power amplifier for the second mode relative to the first mode (paragraph [0095], input and output resistors 1030 and 1032 are used to adjust impedance to avoid input output losses during amplify modes).
However, Ye is silent in teaching a wireless communication device with a multi-mode power amplifier system (such as multi-mode power amplifier system 500 in Fig. 5 in Ye) comprising an antenna.
Babcock teaches:
A wireless communication device (wireless communication device 800 of Fig. 39C) comprising an antenna (antennas 804).
A person of ordinary skill in the art would find it obvious to implement the multi-mode power amplifier system taught in Ye (500 in Fig. 5) in a wireless communication device and include an antenna as taught by Babcock (Fig. 39C) to be used in a wide variety of communications (paragraphs [0639], [0645]). Thereby suggesting such an obviousness of such a modification.
Regarding claim 19, Ye discloses:
the multi-mode power amplifier system, however, Ye is silent in teaching that the multi- mode power amplifier system includes a baseband processor configured to provide a mode select signal to the bias circuit.
Babcock teaches:
the multi- mode power amplifier system (as applied in the wireless communication device 800 of Fig. 39) includes a baseband processor (Fig. 39C, device 800, baseband system 801) configured to provide a mode select (corresponding to WLAN or WPAN) signal to the bias circuit (of the multimode power amplifier system to operate in WLAN or WPAN modes).
A person of ordinary skill in the art would find it obvious to implement a multimode variable gain power amplifier system, such as, Ye’s to switch between WLAN and WPAN system, as the first and the second mode of operations to cover same device (transceiver) for multiple purposes, wherein the first mode is a Wi-Fi mode (WLAN) and the second mode is a Bluetooth mode (WPAN) (Babcock, paragraph [0639]).
Claim(s) 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ye et al. and Babcock et al. and in further view of Shirvani and/or Arell (each cited by the applicant), hereafter referred to as “Ye and Babcock”, “Shirvani”, and “Arell”, respectively.
Regarding claim 6, Ye and Babcock teaches:
The combination of Ye and Babcock (clearly shows as part of output matching network a shunt inductor and a switch with a series capacitor, see Figs.10-14) is not explicit about a shunt capacitor and a series inductor constituting the output matching network.
In a similar field of endeavor Shirvani indicates shunt capacitor (70) with series inductor (66) as matching circuit (24) for a multimode amplifier (paragraph [0046]) like the combination of Ye and Babcock. Also, Arell teaches in Figs. 8 and 4, in respective power modes, the bias network and mode control 850 using respective switches and amplifiers paths with series inductor and shunt capacitor matching networks providing desired impedance match to optimize the power transfer from the output of the power amplifier 800 (paragraph [0048]).
Therefore, it would have been obvious to a person of ordinary skill in the art to replace the switchable output matching network of the resultant combination of Ye and Babcock with an art equivalent substitute of output matching network with a switchable shunt capacitor and a series inductor network similar to that taught by Shirvani and/or Arell and perform the equivalent optimization of output impedance matching performance with respective modes of the multimode amplifier of the combination. Wherein per claim 7, Babcock teaches surface mount passive devices, such as inductors and capacitors for matching and filtering purposes with the multimode amplifier (Babcock, paragraph [0580]). Wherein per claim 8, Arell teaches the output matching network includes a first section (440 of shunt capacitor 442, series inductor 441, Fig. 4) and a second section (430 of series inductor 431 and shunt capacitor 432, Fig. 4) coupled to the output of the power amplifier (410-420) by way of the first section (440), the second section (430) including the switch (745 in Fig. 7 and 827 in Fig. 8), the series inductor (440), and the shunt capacitor (442).
Allowable Subject Matter
Claim 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Baltzell can be reached at (571) 272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MALANE LIENG/ Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843