DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
On March 11, 2026, a Notice of Allowance was mailed for the present application. Subsequently, on June 10, 2026, the applicant filed a Request for Continued Examination (RCE) accompanied by an Information Disclosure Statement (IDS).
Upon reviewing the newly cited references provided in the June 10, 2026 IDS, the examiner identified the prior art reference Ota (US 2013/0265111 A1). It has been determined that Ota teaches or suggests the limitations of the independent claims that were previously deemed allowable. Therefore, a new rejection under 35 U.S.C. § 103 for obviousness is necessitated, and a new Non-Final Office Action is issued below.
§13.04 Reopen Prosecution — After Notice of Allowance Prosecution on the merits of this application is reopened in view of the Request for Continued Examination (RCE) and Information Disclosure Statement (IDS) filed on June 10, 2026.
§13.05 Reopen Prosecution — After Notice of Allowance, New Reference Prosecution on the merits of this application is reopened in view of the newly discovered prior art reference to Ota.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ota et al. (US 2013/0265111 A1) in view of Babcock et al. (US 2018/0226367 A1) and Ye et al. (US 2018/0131339 A1).
Regarding Claims 1, 14, 18, and 20
Ota teaches a multi-mode power amplifier system comprising:
At least one power amplifier (e.g., first amplifier 1 and second amplifier 2) configured to amplify a radio frequency signal in at least a first mode (high power state) and a second mode (low power state). A
An output matching network having a first stage (first output matching circuit 3) coupled to an output of the power amplifier, where the first stage tunes an output matching impedance for the first mode.
An output matching network having a second stage (second output matching circuit 4) with an inductor (L1) coupled in series with the first stage, wherein the second stage further includes a shunt capacitor (C1, C2) coupled to the inductor and a switch (SW1, SW2) coupled to the shunt capacitor.
The second stage tunes the output matching impedance for the second mode in response to the switch.
An antenna coupled to the output matching network, as well as methods of operating this multi-mode power amplifier system.
While Ota teaches the core RF amplification and matching network switching architecture, Ota does not explicitly disclose:
A bias circuit configured to provide a reference current with a first reference current level in the first mode and a second reference current level in the second mode, wherein the bias circuit includes registers that store settings for the reference current levels to account for a temperature profile of the power amplifier (Claims 1, 18, and 20).
The at least one power amplifier being on a compound semiconductor die (e.g., silicon germanium), the switch being on a semiconductor-on-insulator (SOI) die, and both being packaged together on a common substrate (Claim 14).
Babcock, which is in the same field of endeavor (radio frequency front-end modules and power amplification), teaches the missing limitations:
Babcock teaches multi-mode power amplifiers that utilize a bias circuit configured to control the bias of the amplifier stages depending on the mode of operation. Babcock further teaches that operating levels can be controlled based on operating conditions, explicitly including temperature. Furthermore, Babcock discloses using an integrated circuit equipped with registers to store settings and control the states of various signals (e.g., enable signals).
Babcock teaches integrating power amplifiers and RF switches in a multi-chip module. Specifically, Babcock discloses that power amplifiers can be implemented on a separate compound semiconductor die (such as a GaAs, GaN, or SiGe die) to provide higher efficiency and higher breakdown voltages. Babcock simultaneously teaches implementing RF switches on a silicon-on-insulator (SOI) die because SOI processes exhibit superior performance for RF switching compared to other technologies.
It would have been obvious to a Person Having Ordinary Skill in the Art (POSITA) at the time of the invention to rationally modify the multi-mode power amplifier system of Ota to incorporate the register-based, temperature-compensating bias circuit and the heterogeneous die integration (compound semiconductor PA and SOI switch on a common substrate) as taught by Ye and/or Babcock.
A POSITA would have been motivated to combine the teachings of Ota with Ye and/or Babcock for the following reasons:
A POSITA would be motivated to use registers to store bias settings that account for temperature profiles to ensure stable, reliable performance of the power amplifier across fluctuating thermal conditions, preventing degradation of power added efficiency (PAE) and linearity as operating temperatures change.
A POSITA would be explicitly motivated to use a compound semiconductor die (e.g., SiGe) for the power amplifier and an SOI die for the switch to optimize the overall RF system's efficiency, cost, and performance. As noted in the secondary art, utilizing a compound semiconductor provides the high impedance load line necessary for high voltage swing and low current consumption in amplification, while integrating the switch on an SOI die yields superior RF switching performance. Packaging them on a common substrate reduces overall cost and footprint while maximizing the respective strengths of each semiconductor material.
Regarding Claims 2-13, 15-17, and 19
Ota teaches a multi-mode power amplifier system and method of operation that includes several of the dependent claim limitations:
Adjusting the PA signal path and OMN impedance (Claims 6, 7, 16): Ota teaches adjusting the signal path by selectively switching between a main amplifier (HPM) and a sub amplifier (LPM) based on mode. Ota further teaches adjusting the output matching impedance of the network based on the operating mode and frequency.
Switching a shunt capacitor (Claims 8, 9, 17): Ota teaches an output matching network comprising a switch (SW2) configured to include a shunt capacitor (C2) in the matching impedance in a first state, and to disconnect/exclude it in a second state.
While Ota teaches the core multi-mode RF amplification and dynamic matching architecture, it does not explicitly disclose:
The first and second modes being WLAN (Wi-Fi) and WPAN (Bluetooth) modes (Claims 2, 3, 11).
The bias circuit deactivating specific auxiliary PA transistors in the gain and output stages for the second mode (Claims 4, 5).
The series-inductor being a surface mount inductor (Claim 10).
Heterogeneous die integration, specifically the PA being on a compound semiconductor die (e.g., SiGe) and the switch/LNA being on a semiconductor-on-insulator (SOI) die (Claims 12, 13, 15).
A baseband processor providing a mode select signal directly to the bias circuit (Claim 19).
Babcock and Ye, which are in the same field of endeavor (radio frequency front-end modules and power amplification), teach the missing limitations:
WLAN/WPAN, Wi-Fi, and Bluetooth Modes (Claims 2, 3, 11): Babcock explicitly teaches front-end systems configured to process signals associated with Wireless Local Area Networks (WLAN) such as Wi-Fi, and Wireless Personal Area Networks (WPAN) such as Bluetooth and ZigBee.
Deactivating Auxiliary Transistors (Claims 4, 5): Babcock teaches a bias circuit configured to dynamically control the bias of stacked transistors based on the mode. Specifically, Babcock teaches biasing a transistor to a linear region of operation in a first mode and biasing it as a switch (effectively deactivating it) in a second lower-power mode to adjust the signal path and improve efficiency.
Surface Mount Inductor (Claim 10): Babcock teaches stacked filter assemblies and matching networks utilizing passive components that are packaged as surface mount devices, explicitly including inductors.
Heterogeneous Die Integration (SiGe PA and SOI Switch/LNA) (Claims 12, 13, 15): Babcock teaches packaging architectures utilizing multiple distinct semiconductor dies. Babcock explicitly discloses implementing power amplifiers on separate compound semiconductor dies (such as SiGe, GaAs, or GaN) to provide higher voltage swing and efficiency, while implementing RF switches and Low Noise Amplifiers (LNAs) on Silicon-On-Insulator (SOI) dies to leverage their superior RF switching performance.
Baseband Processor Mode Selection (Claim 19): Babcock teaches a baseband system/processor that provides control signals, including mode select signals and bias control signals, to the control and biasing circuits of the multi-mode power amplifier.
It would have been obvious to a Person Having Ordinary Skill in the Art (POSITA) at the time of the invention to rationally modify the multi-mode power amplifier system of Ota to incorporate the specific communication protocols (Wi-Fi/Bluetooth), surface mount passive components, baseband processor control, and heterogeneous multi-chip packaging (SiGe and SOI integration) taught by Babcock. Furthermore, it would have been obvious to implement the specific transistor-level bias deactivation (acting as a switch) taught by Babcock to achieve the mode-switching taught broadly by Ota.
A POSITA would have been motivated to combine the teachings of Ota with Babcock and Ye for the following reasons:
Multi-Protocol Support: A POSITA would be motivated to adapt Ota's multi-mode amplifier to support both Wi-Fi (WLAN) and Bluetooth (WPAN) as taught by Babcock to allow the front-end module to be integrated into modern IoT and mobile devices that require simultaneous or switched multi-protocol wireless connectivity.
Efficiency and Space Reduction: A POSITA would be motivated to use surface mount inductors to reduce the physical footprint of the output matching network, and to use baseband-driven transistor deactivation to maximize power-added efficiency (PAE) during low-power (Bluetooth) operations.
Optimized Semiconductor Performance: A POSITA would be strongly motivated to utilize a SiGe (compound) die for the power amplifier to achieve high breakdown voltages and efficient power amplification, while using an SOI die for the switches and LNAs to minimize insertion loss and improve noise figures, packaging them on a common substrate to reduce overall device cost and footprint as explicitly suggested by Babcock.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
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