DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA .
This action is responsive to the application filed 05/09/2023.
Claims 1-20 are presented for examination. Claims 1 and 12 are independent Claims.
Information Disclosure Statement
2. The Applicant’s Information Disclosure Statement (filed 08/23/2023) has been received, entered into the record, and considered.
Drawings
3. The drawings filed 08/23/2023 are acceptable for examination purposes.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-20 of copending application 18/195259.
Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1-20 of copending application 18/195259 contain every element of claims 1-20 of the instant application and thus anticipate the claims of the instant application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting.
Current Application
Copending application 18/195259
1. A dual-mode power amplifier simulation system comprising:
a trained machine learning model that is trained with first simulation results associated with a first power amplifier circuit and measured results associated with a physical implementation of the first power amplifier circuit, the trained machine learning model is configured to generate augmented simulation results;
a simulator executing on one or more computer processors that simulates a dual-mode power amplifier circuit and generates dual-mode simulation results; and
a post processor including the trained machine learning model that executes on one or more computing devices with computer-executable instructions that, when executed, causes the post processor to augment the dual-mode simulation results for the dual-mode power amplifier based on the trained machine learning model associated with the first power amplifier circuit.
1. An electronic circuit simulation post-processing system comprising:
a trained machine learning model that is trained with first simulation results associated with a first electronic circuit and measured results obtained from a physical implementation of the first electronic circuit, the trained machine learning model configured to generate augmented simulation results;
a simulator executing on one or more computer processors that simulate a second electronic circuit that is different than the first electronic circuit and generates second simulation results; and
a post processor including the trained machine learning model that executes on one or more computing devices with computer-executable instructions that, when executed, causes the post processor to augment the second simulation results based on the trained machine learning model.
As to the remaining claims 2-20, they are also rejected under obvious type double patenting as stated in claim 1 above.
This is a provisional obviousness-type double patenting rejection because the conflicting claims have not in fact been patented.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-8, 10-12, and 15-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by JOHNSTON et al. (US 20210313841).
It is noted that any citations to specific, pages, columns, paragraphs, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
As to Claim 1:
JOHNSTON teaches a dual-mode power amplifier simulation system (Abstract, [0006-0007], and [0011-0012]) comprising:
a trained machine learning model that is trained with first simulation results associated with a first power amplifier circuit and measured results associated with a physical implementation of the first power amplifier circuit, the trained machine learning model is configured to generate augmented simulation results (Abstract, [0011-0013], and [0141-0151]);
a simulator executing on one or more computer processors that simulates a dual-mode power amplifier circuit and generates dual-mode simulation results ([0006-0009] and [0101-0106]); and
a post processor including the trained machine learning model that executes on one or more computing devices with computer-executable instructions that, when executed, causes the post processor to augment the dual-mode simulation results for the dual-mode power amplifier based on the trained machine learning model associated with the first power amplifier circuit ([0197-0198] and [0233]).
As to Claim 4:
JOHNSTON the first power amplifier circuit and the dual mode power amplifier circuit are multi-chip modules ([0328-0329]).
As to Claim 5:
JOHNSTON the computer-executable instructions, when executed, further causes the one or more computer processors to retrain the trained machine learning model using second measured results obtained from the second electronic circuit ([0328-0329]).
As to Claim 6:
JOHNSTON the trained machine learning model uses a gradient tree boosting, ensemble model ([0141-0151]).
As to Claim 7:
JOHNSTON the trained machine learning model uses at least one of the group consisting of: linear regression, least absolute shrinkage and selection operator (LASSO), support vector regression (SVR), random forest algorithms, or bayesian ridge regression ([0151]).
As to Claim 8:
JOHNSTON the trained machine learning model is trained to augment simulation results associated with at least one of the group consisting of: output power, error vector magnitude, current, and an output matching network ([0157] and [0376]).
As to Claim 10:
JOHNSTON the trained machine learning model reduces errors in the simulation results associated with the dual-mode power amplifier circuit, the errors including at least one of the group consisting of coding errors, thermal modeling errors, surface mount component (SMT) modeling errors, multi-chip module (MCM) modeling errors, mixed-signal integrated circuit errors, process variation errors, and harmonic balance errors ([0134], [0157], and [0376]).
As to Claim 11:
JOHNSTON computer-executable code that generates first simulation results corresponding to the measured results ([0023-0024] and [0038-0041]).
As to Claim 12:
JOHNSTON a computer-implemented method comprising:
storing a trained machine learning model that is trained with first simulation results associated with a first power amplifier circuit and measured results obtained from a physical implementation of the first power amplifier circuit (Abstract, [0011-0013], and [0141-0151]);
generating, with one or more computer processors, second simulation results associated with a dual-mode power amplifier circuit that is different than the first power amplifier circuit results ([0006-0009] and [0101-0106]); and
augmenting the second simulation results with the trained machine learning model that executes on one or more computing devices with computer-executable instructions ([0197-0198] and [0233]).
As to Claim 15:
JOHNSTON teaches the first power amplifier circuit includes a mode switch to adjust an output matching impedance, and the dual-mode power amplifier has an array of mode select switches to adjust an output matching impedance ([0129-0132] and [0195]).
As to Claim 16:
JOHNSTON teaches retraining the trained machine learning model using second measured results obtained from the dual-mode power amplifier circuit; and augmenting third simulation results associated with another dual-mode power amplifier circuit with the retrained machine learning model ([0106-0107] and [0151]).As to Claim 17:
JOHNSTON teaches the trained machine learning model uses a gradient tree boosting, ensemble model ([0141-0151]).
As to Claim 18:
JOHNSTON teaches the trained machine learning model uses at least one of the group consisting of: linear regression, least absolute shrinkage and selection operator (LASSO), support vector regression (SVR), random forest algorithms, or bayesian ridge regression ([0151]).
As to Claim 19:
JOHNSTON teaches the trained machine learning model is trained to augment simulation results associated with at least one of the group consisting of: output power, error vector magnitude, current, and an output matching network ([0157] and [0376]).
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 2, 3, 9, 13, 14, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over JOHNSTON in view of ZHU et al. (US 20220114136).
As to Claim 2:
JOHNSTON does not explicitly teach, ZHU teaches the trained machine learning model is further trained with bill of material information about the first power amplifier circuit ([0065] and [0070]).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify JOHNSTON with ZHU because it would have provided the enhanced capability for operating an electronic device according to its precise bill of materials.
As to Claim 3:
JOHNSTON does not explicitly teach, ZHU teaches the trained machine learning model further receives bill of material information about the dual-mode power amplifier circuit ([0065] and [0070]).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify JOHNSTON with ZHU because it would have provided the enhanced capability for operating an electronic device according to its precise bill of materials.
As to Claim 9:
JOHNSTON does not explicitly teach, ZHU teaches the simulation results associated with the first power amplifier circuit, the measured results, and/or a bill of materials are used to train the trained machine learning model include at least one of the group consisting of: a surface mount component, a power amplifier variable, inductor data, capacitance data, input matching network (IMN) data, IMN inductor data, output matching network (OMN) data, OMN inductor data, OMN capacitor data, resistance data, resistance data, transistor base resistance (RBB), current, voltage, frequency, WiFi enable, multichip data, circuit architectural information, and silicon on insulator data ([0062] [0065], [0070], and [0076]).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify JOHNSTON with ZHU because it would have provided the enhanced capability for operating an electronic device according to its precise bill of materials.
As to Claim 13:
JOHNSTON does not explicitly teach, ZHU teaches the trained machine learning model is further trained with bill of material information about the first power amplifier electronic circuit ([0065] and [0070]).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify JOHNSTON with ZHU because it would have provided the enhanced capability for operating an electronic device according to its precise bill of materials.
As to Claim 14:
JOHNSTON does not explicitly teach, ZHU teaches the trained machine learning model further receives bill of material information about the dual mode power circuit ([0065] and [0070]).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify JOHNSTON with ZHU because it would have provided the enhanced capability for operating an electronic device according to its precise bill of materials.
As to Claim 20:
JOHNSTON does not explicitly teach, ZHU teaches the first simulation results, the measured results, and/or a bill of materials are used to train the trained machine learning model include at least one of the group consisting of: a surface mount component, a power amplifier variable, inductor data, capacitance data, input matching network (IMN) data, IMN inductor data, output matching network (OMN) data, OMN inductor data, OMN capacitor data, resistance data, resistance data, transistor base resistance (RBB), current, voltage, frequency, WiFi enable, multichip data, circuit architectural information, and silicon on insulator data ([0062] [0065], [0070], and [0076]).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify JOHNSTON with ZHU because it would have provided the enhanced capability for operating an electronic device according to its precise bill of materials.
Conclusion
7. The prior art made of record, listed on PTO 892 provided to Applicant is considered to have relevancy to the claimed invention. Applicant should review each identified reference carefully before responding to this office action to properly advance the case in light of the prior art.
Contact information
8. Any inquiry concerning this communication or earlier communications from the
examiner should be directed to MAIKHANH NGUYEN whose telephone number is (571) 272-4093. The examiner can normally be reached on Monday-Friday (8:00 am – 5:30 pm). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TAMARA KYLE can be reached at (571)272-4241.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MAIKHANH NGUYEN/Primary Examiner, Art Unit 2144
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