Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/13/2025 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 1, lines 20-21, regarding “publishing, in the shared memory, state information…”, it is unclear and ambiguous because the claim does not specify what actions constitute “publishing” in this context. It is unclear whether “publishing” refers to writing data into shared memory or making data readable by other chiplets or signaling availability of the state information or enforcing a particular memory ordering. Similar problems exist in claims 10 and 19.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-13 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by DITTY et al. (U.S. Publication No. 2023/0176577 A1), hereafter referred to as DITTY’577.
Referring to claim 1, DITTY’577, as claimed, a computing system (see Figs. 7-9, 20, 26, and 27) comprising a plurality of chiplets (controllers 100 or SOCs 2002(N), see paras. [0121] and [0296] and Fig. 20) executing a plurality of workloads (execution of workloads with a mix of computation and addressing calculations, see para. [0200]), the plurality of chiplets including: a central chiplet including (a) a shared memory (memory such as HBM or HBM2 unified memory technology, see paras. [0201]-[0204], [0218]-[0221]; also note: memory system 2004 shared between SOCs 2002, see paras. [0298] and [0299]) and (b) a cache memory accessible by the plurality of chiplets (SRAM, see paras. [0219]-[0221]; also note: L2, L3 cache, see paras. [0188], [0195], [0196], [0265]); a sensor input chiplet to execute one or more workloads (object identification/detection using data from camera sensors, see para. [0210]) for receiving sensor data from a plurality of sensors (controllers (100(1)-100(3)) is continuously provided signals from an array of sensors, see paras. [0120], [0124], [0264], [0324], and Figs. 4, 24, 26) and store the sensor data in the cache memory (on-chip and off-chip storage including RAM, SRAM, DRAM, VRAM. On-chip storage comprise L2 or L3 caches, see para. [0265]); a machine learning accelerator chiplet to execute multiple workloads for accessing the sensor data in the cache memory (DLA can quickly and efficiently execute neural networks, especially CNNs, on processed or unprocessed data for any variety of functions including , without limitation: (1) a CNN for object identification and detection using data from camera sensors, (2) a CNN for distance estimation using data from camera sensors…(5) a CNN for security and/or safety related events; inference accelerator, see paras. [0207]-[0211]; also note: Programmable Vision Accelerator in paras. [0187], [0212]-[0217]), and for calculating inferences using the sensor data and machine learning (separate controller/supercomputer configured to perform deep learning and artificial intelligence functionality, see paras. [0126], [0171], [0172]; also note: Deep Learning Accelerator (DLA) optimized for inferencing, see paras. [0208]-[0211]); and an autonomous drive chiplet to execute one or more workloads for calculating autonomous driving algorithms (blend of multiple processors to perform the complex functions associated with Level 3-5 autonomous vehicles, see para. [0182]) based at least in part on inferences calculated by the machine learning accelerator chiplet (The DLA runs a neural network for regressing the confidence value. The neural network can take as its input at least some subset of parameters, such as (1) bounding box dimensions, (2) ground plane estimate obtained e.g. from another subsystem (3) inertial measurement unit (IMU) output that correlates with ego-vehicle orientation, (4) distance or 3D location estimates of the object obtained from the neural network and/or other sensors, such as LIDAR or RADAR, see para. [0227]; by providing a CPU complex, GPU complex and hardware acceleration cluster, multiple neural networks to be performed simultaneously or sequentially and for the results to be combined together to enable Level 3-5 autonomous driving functionality, see paras. [0257]-[0260]); wherein each chiplet of the plurality of chiplets communicates with other chiplets of the plurality of chiplets (each Advanced SoC can address the other Advanced SoC’s DRAM and SysRAM, see para. [0286]) by (i) accessing, in the shared memory (communication or interactions with one another or some or all of the memory systems could be shared between the SOCs, see paras. [0298]-[0301]), state information (controls/states are shared and integrated among the components, see paras. [0310], [0314] and multilevel monitoring such as monitoring same or different or other state information of the event processing, see para. [0467]) for each workload that is to be executed by the chiplet, and (ii) publishing, in the shared memory, state information for each workload that is executed by that chiplet (the vector processors included in a particular PVA may be configured to employ data parallelism. For example, the plurality of vector processors execute the same computer vision algorithm but on different regions of an image. In other embodiments, the vector processors may simultaneously execute different computer vision algorithms on the same image or even execute different algorithms on sequential images or portions on an image, see para. [0217]; also note all relevant inputs gathered by sensors are fed into each of the processors. Each of the processors may independently process the sensor data, and independently provides actuation information and/or control signals that may be used to control the vehicle actuators. MCU receives the information and/or signals and evaluates them for consistency, see para. [0287]).
As to claim 2, DITTY’577 also discloses the plurality of chiplets includes one or more general compute chiplets (controllers 100 or SOCs 2002(N), see paras. [0121] and [0296] and Fig. 20; also note: general purpose CPUs, see para. [0185] and Fig. 7).
As to claim 3, DITTY’577 also discloses the plurality of chiplets includes a cache memory chiplet (SRAM, see paras. [0219]-[0221]; also note: on-chip and off-chip storage including RAM, SRAM, DRAM, VRAM. On-chip storage comprise L2 or L3 caches, see paras. [0188], [0195], [0196], [0265]) accessible by the plurality of chiplets.
As to claim 4, DITTY’577 also discloses the autonomous drive chiplet (blend of multiple processors to perform the complex functions associated with Level 3-5 autonomous vehicles, see para. [0182]) is coupled to a dedicated cache memory chiplet (SRAM, see paras. [0219]-[0221]; also note: on-chip and off-chip storage including RAM, SRAM, DRAM, VRAM. On-chip storage comprise L2 or L3 caches, see paras. [0188], [0195], [0196], [0265]; GPU memory separate and independent, see para. [0301]).
As to claim 6, DITTY’577 also discloses the shared memory stores a plurality of programs to execute a plurality of workload pipelines in parallel (parallel workloads/processing, see paras. [0185], [0199], [0200], [0300], [0696]).
As to claim 7, DITTY’577 also discloses the central chiplet (controllers 100 or SOCs 2002(N), see paras. [0121] and [0296] and Fig. 20) includes a transient-resistant CPU core to schedule the plurality of programs (scheduling, see paras. [0200], [0363], [0373], [0384], [0682], [0696]).
As to claim 8, DITTY’577 also discloses each of the plurality of chiplets includes at least one transient-resistant CPU core (cores such as in controllers 100 or SOCs 2002(N), see paras. [0121] and [0296], Figs. 8, 16, and 20).
As to claim 9, DITTY’577 also discloses each of the plurality of chiplets communicate through the shared memory by synchronizing workloads in a reservation table stored in the shared memory (thread scheduling, finer-grain synchronization and cooperation between parallel threads; shared memory, see paras. [0200], [0202]; also note: monitors shared resources and determine whether the two computers are sufficiently aligned, see para. [0330]).
Note claims 10 and 19 recite similar limitations of claim 1. Therefore they are rejected based on the same reason accordingly.
Note claims 11 and 20 recite the corresponding limitations of claim 2. Therefore they are rejected based on the same reason accordingly.
Note claim 12 recites the corresponding limitations of claim 3. Therefore it is rejected based on the same reason accordingly.
Note claim 13 recites the corresponding limitations of claim 4. Therefore it is rejected based on the same reason accordingly.
Note claim 15 recites the corresponding limitations of claim 6. Therefore it is rejected based on the same reason accordingly.
Note claim 16 recites the corresponding limitations of claim 7. Therefore it is rejected based on the same reason accordingly.
Note claim 17 recites the corresponding limitations of claim 8. Therefore it is rejected based on the same reason accordingly.
Note claim 18 recites the corresponding limitations of claim 9. Therefore it is rejected based on the same reason accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over DITTY’577 in view of Applicant’s Admitted Prior Art, hereafter referred to as AAPA.
As to claim 5, DITTY’577 discloses the plurality of chiplets interface through interconnects (Chip-to-Chip communication, NVLINK, PCIe, etc., see paras. [0284]-[0286], [0306], [0313]; I2C bus, see para. [0701]).
However, DITTY’577 does not explicitly teach Universal Chiplet Interconnect Express interconnects.
AAPA discloses Universal Chiplet Interconnect Express interconnects (Universal Chiplet Interconnect Express (UCIe), see para. [0001]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify DITTY’577’s invention to implement Universal Chiplet Interconnect Express interconnects, as taught by AAPA, in order to produce large SoC packages with intermixed components from different silicon manufacturers thereby achieving higher safety integrity levels of electrical components (see para. [0001]) and on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Note claim 14 recites the corresponding limitations of claim 5. Therefore it is rejected based on the same reason accordingly.
Response to Arguments
Applicant's arguments filed 10/30/2025 have been fully considered but they are not persuasive.
At the outset, Applicants are reminded that claims subject to examination will be given their broadest reasonable interpretation consistent with the specification. In re Morris, 127 F.3d 1048, 1054-55 (Fed. Cir. 1997). In fact, the "examiner has the duty of police claim language by giving it the broadest reasonable interpretation." Springs Window Fashions LP v. Novo Industries, L.P., 65 USPQ2d 1862, 1830, (Fed. Cir. 2003). Applicants are also reminded that claimed subject matter not the specification, is the measure of the invention. Disclosure contained in the specification cannot be read into the claims for the purpose of avoiding the prior art. In re Sporck, 55 CCPA 743, 386 F.2d, 155 USPQ 687 (1986).
With this in mind, the discussion will focus on how the terms and relationships thereof in the claims are met by the references. Response to any limitations that are not in the claims or any arguments that are irrelevant and/or do not relate to any specific claim language will not be warranted.
Applicant argued that “DITTY’577 does not teach each chiplet of the plurality of chiplets communicat[ing] with other chiplets of the plurality of chiplets by (i) accessing, in the shared memory, state information for each workload that is to be executed by the chiplet, and (ii) publishing, in the shared memory, state information for each workload that is executed by that chiplet.” (Pages 7-9 of Applicant’s Amendment)
Examiner does not agree with Applicant. As set forth in the art rejection, DITTY’577 discloses each chiplet of the plurality of chiplets communicates with other chiplets of the plurality of chiplets (each Advanced SoC can address the other Advanced SoC’s DRAM and SysRAM, see para. [0286]) by (i) accessing, in the shared memory (communication or interactions with one another or some or all of the memory systems could be shared between the SOCs, see paras. [0298]-[0301]), state information (controls/states are shared and integrated among the components, see paras. [0310], [0314] and multilevel monitoring such as monitoring same or different or other state information of the event processing, see para. [0467]) for each workload that is to be executed by the chiplet, and (ii) publishing, in the shared memory, state information for each workload that is executed by that chiplet (the vector processors included in a particular PVA may be configured to employ data parallelism. For example, the plurality of vector processors execute the same computer vision algorithm but on different regions of an image. In other embodiments, the vector processors may simultaneously execute different computer vision algorithms on the same image or even execute different algorithms on sequential images or portions on an image, see para. [0217]; also note all relevant inputs gathered by sensors are fed into each of the processors. Each of the processors may independently process the sensor data, and independently provides actuation information and/or control signals that may be used to control the vehicle actuators. MCU receives the information and/or signals and evaluates them for consistency, see para. [0287]). The components in DITTY’577 are tightly integrated sharing data with multilevel safety framework providing high levels of resiliency and redundancy while providing processing capabilities to timely and effectively monitor many complicated high-performance real-time drive control (and other) control functions (see paras. [0427]-[0430]). Applicant is suggested to expand on the state information for each workload and the “publishing”.
In summary, DITTY’577 and AAPA teach the claimed limitations as set forth.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Contact Information
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TITUS WONG/Primary Examiner, Art Unit 2181