Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to the listing of claims filed on May 11, 2023. Claims 1-20 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US PGPub No: 2018/0041601) in view of Tomlinson et al (US PGPub No: 2002/0104031), hereafter referred to as Park and Tomlinson, respectively.
With regards to claim 1, Park teaches through Tomlinson, a method for verifying that a region of configurable logic circuits in an integrated circuit has been erased, the method comprising: receiving a first key, first data, and a digital signature at a first control circuit comprising a signature verifier engine (Park teaches the eUICC receiving the Delete Profile OK message; see paragraph 203, Park. The Delete Profile OK message includes a profile ID, random challenge (i.e. first data), public key (i.e. first key) and signature value (i.e. signature); see paragraph 202, Park);
and performing a signature verification of the digital signature with the signature verifier engine using the first data and the first key to generate an output that verifies whether the region of the configurable logic circuits in the integrated circuit has been erased (Park teaches the eUICC transmitting a Deletion OK message to a terminal, the Deletion OK message includes a signature value encrypted with a private key; see paragraph 192, Park. The Deletion OK message indicates to the notification server that a specific profile (i.e. region) has been successfully deleted; see paragraph 192 and element 1825 of Figure 18, Park)
While Park teaches discarding/erasing portions of an eUICC (integrated circuit), Park does not explicitly configurable logic circuits being part of integrated circuits. In the same field of endeavor, Tomlinson also teaches a system that supports integrated circuits supporting erasure; see paragraphs 32 and 43, Tomlinson. In particular, Tomlinson explains how integrated circuits can comprise erasable capture register coupled to programmable logic circuit (configuration logic circuit) to be adapted to capture system status; see claim 10, Tomlinson. By using programmable logic circuits, integrated circuits can be reconfigured to erase/delete data. Therefore it would have been obvious to one skilled in the art, before the effective filing date, to have combined the teachings of Tomlinson with those of Park to use programmable logic circuits with integrated circuits to erase/delete data.
With regard to claims 2 and 10, Park teaches through Tomlinson,the method further comprising: generating a hash value with a hash function using hash circuitry, wherein the first data comprises the hash value (Park teaches the hash being generated based on received information such as the random challenge value; see paragraph 231, Park).
With regard to claims 3, 11, and 18, Park teaches through Tomlinson,the method wherein generating the hash value comprises generating the hash value using a first nonce value from a first user (Park teaches the hash being generated based on received information such as the random challenge (nonce) value; see paragraph 231, Park).
With regard to claims 4 and 12, Park teaches through Tomlinson,the method wherein generating the hash value further comprises generating the hash value using the first nonce value and a second nonce value from a second user (Park teaches the hash being generated based on received information such as the random challenge (first nonce) value and other credentials such as biometrics (second nonce); see paragraph 231, Park).
With regard to claims 5, 13, and 19, Park teaches through Tomlinson,the method wherein generating the hash value further comprises generating the hash value using a first identifier that identifies the region of the configurable logic circuits and a second identifier that identifies the integrated circuit (Park teaches the hash being generated based on received information such as the random challenge (first nonce) value and other credentials such as biometric authentication information (second nonce); see paragraph 231, Park. The biometric authentication information can be value; see paragraph 223, Park).
With regards to claim 6, Park teaches through Tomlinson,the method further comprising: generating the digital signature using a signing engine in a second control circuit based on a second key and the first data, wherein the first key and the second key are part of a key pair (The Delete Profile message can include a signature, a third delivery server public key and a second delivery server public key; see paragraphs 202 and 214, Park).
With regard to claims 7, 15, and 20, Park teaches through Tomlinson,the method further comprising: erasing second data stored in memory in the region of the configurable logic circuits in response to receiving a nonce value from a user using a security controller circuit in the integrated circuit (Park supports a factory reset on the eUICC (delete second data in memory of logical circuit) with the request including a random challenge value; see paragraph 238, Park).
With regards to claim 8, Park teaches through Tomlinson,the method further comprising: allowing configuration of the region of the configurable logic circuits in response to the digital signature being generated (Deletion request includes a signature, upon authentication of the signature, the deletion of the specific profile can occur (configuration of the region)).
With regards to claim 9, Park teaches through Tomlinson,an integrated circuit comprising: a region of configurable logic circuits (Park teaches the eUICC configuring a profile deletion policy rule; see paragraph 172, Park. The eUICC stores the policy rules (i.e. region); see paragraph 233, Park);
and a first control circuit that generates a digital signature based on a private key and first data using a signing engine for verifying that second data stored in the region of the configurable logic circuits has been deleted (Park teaches the eUICC transmitting a Deletion OK message to a terminal, the Deletion OK message includes a signature value encrypted with a private key; see paragraph 192, Park. The Deletion OK message indicates to the notification server that a specific profile (i.e. region) has been successfully deleted; see paragraph 192 and element 1825 of Figure 18, Park).
While Park teaches discarding/erasing portions of an eUICC (integrated circuit), Park does not explicitly configurable logic circuits being part of integrated circuits. In the same field of endeavor, Tomlinson also teaches a system that supports integrated circuits supporting erasure; see paragraphs 32 and 43, Tomlinson. In particular, Tomlinson explains how integrated circuits can comprise erasable capture register coupled to programmable logic circuit (configuration logic circuit) to be adapted to capture system status; see claim 10, Tomlinson. By using programmable logic circuits, integrated circuits can be reconfigured to erase/delete data. Therefore it would have been obvious to one skilled in the art, before the effective filing date, to have combined the teachings of Tomlinson with those of Park to use programmable logic circuits with integrated circuits to erase/delete data.
With regards to claim 14, Park teaches through Tomlinson,the integrated circuit further comprising: a second control circuit comprising a signature verifier engine that generates an output verifying whether the second data stored in the region of the configurable logic circuits has been deleted by performing a signature verification of the digital signature using a public key (Park supports a factory reset on the eUICC (delete second data in memory of logical circuit) with the request including a random challenge value; see paragraph 238, Park. An OK or Not OK message is sent (verification output) based on the factory reset success; see paragraph 243, Park).
With regards to claim 16, Park teaches through Tomlinson,a non-transitory computer readable storage medium comprising instructions stored thereon for causing a computer system to execute a method for verifying that data stored in a region of configurable logic circuits in an integrated circuit has been erased, the method comprising: generating a hash value with hash circuitry using a hash function (Park teaches the eUICC generating the hash value; see paragraph 231, Park. It is inherent a hash function is used when a hash is generated);
and performing a signature verification of a digital signature using the hash value and a first key with a signature verifier engine in a first control circuit to verify if the data stored in the region of the configurable logic circuits has been erased (Park teaches the eUICC transmitting a Deletion OK message to a terminal, the Deletion OK message includes a signature value encrypted with a private key; see paragraph 192, Park. The Deletion OK message indicates to the notification server that a specific profile (i.e. region) has been successfully deleted; see paragraph 192 and element 1825 of Figure 18, Park).
While Park teaches discarding/erasing portions of an eUICC (integrated circuit), Park does not explicitly configurable logic circuits being part of integrated circuits. In the same field of endeavor, Tomlinson also teaches a system that supports integrated circuits supporting erasure; see paragraphs 32 and 43, Tomlinson. In particular, Tomlinson explains how integrated circuits can comprise erasable capture register coupled to programmable logic circuit (configuration logic circuit) to be adapted to capture system status; see claim 10, Tomlinson. By using programmable logic circuits, integrated circuits can be reconfigured to erase/delete data. Therefore it would have been obvious to one skilled in the art, before the effective filing date, to have combined the teachings of Tomlinson with those of Park to use programmable logic circuits with integrated circuits to erase/delete data.
The obviousness motivation applied to independent claims 1, 9, and 16 are applicable to their respective dependent claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZIZUL Q CHOUDHURY whose telephone number is (571)272-3909. The examiner can normally be reached M-F.
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/AZIZUL CHOUDHURY/Primary Examiner, Art Unit 2455
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