DETAILED ACTION
This is the initial Office action based on the application filed on May 15, 2023.
Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
Please note that the limitation directed to “trigger an interrupt if the comparison indicates an abnormal operation condition” in Claims 2 and 16 and the limitation directed to “reduce a debug operation invasiveness if the indication of the comparison corresponds to an abnormal operation condition” in Claim 19 are optional. However, in the interest of compact prosecution, the Examiner is performing full examination on the optional limitations.
Claim Objections
Claims 8 and 19 are objected to because of the following informalities:
Claim 8, lines 3-4, recites “the voltage information and temperature information.” It should read – the voltage information and the temperature information --.
Claim 19, line 2, recites “if the indication of the comparison.” It should read – if the provided indication of the comparison --.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 3-15, and 17-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claim Interpretation: Under the broadest reasonable interpretation (BRI), the limitations of Claim 1 are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. See MPEP § 2111.
Step 1: Claim 1 is directed to a system, which is a machine, and falls within one of the statutory categories of invention.
Step 2A, Prong One: Claim 1 recites the limitations:
aggregate trace debug data;
collect operation parameters;
compare collected operation parameters against the stored debug risk threshold information; and
adjust an amount of debug invasiveness based on the provided indication of the comparison.
These recited steps, under the broadest reasonable interpretation (BRI), cover performance of the steps in the human mind alone or with the aid of pen and paper. That is, other than reciting:
a processor;
a trace controller coupled to the processor to;
a sensor fusion block coupled to the processor to;
the sensor fusion block comprising circuitry to;
wherein the trace controller is further to.
Nothing in the claim precludes the steps from practically being performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper. For example, the limitation (a) in the context of the claim encompasses a human observing trace debug data using observation, evaluation, judgment, and opinion to mentally aggregate the trace debug data with the aid of pen and paper. The limitation (b) in the context of the claim encompasses a human observing operation parameters using observation, evaluation, judgment, and opinion to mentally collect the operation parameters in the human mind alone or with the aid of pen and paper. The limitation (c) in the context of the claim encompasses a human observing operation parameters and threshold information using observation, evaluation, judgment, and opinion to mentally compare the operation parameters to the threshold information. The limitation (d) in the context of the claim encompasses a human observing an amount of debug invasiveness and an indication of a comparison using observation, evaluation, judgment, and opinion to mentally adjust an amount of debug invasiveness in the human mind alone or with the aid of pen and paper. See MPEP § 2106.04(a)(2)(III).
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind alone or with the aid of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A, Prong Two: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements:
a processor;
a trace controller coupled to the processor to;
a sensor fusion block coupled to the processor to;
the sensor fusion block comprising circuitry to;
wherein the trace controller is further to.
The additional elements (1) to (5) are recited at a high-level of generality such that they amount to no more than mere instructions to apply the judicial exception using generic computer components. The trace controller coupled to the processor is used as a tool to perform the aggregating and adjusting steps of the claim. The sensor fusion block coupled to the processor is used as a tool to perform the collecting, storing, comparing, and providing steps of the claim. See MPEP § 2106.05(f).
Also, the claim recites the additional elements:
store debug risk threshold information;
provide an indication of the comparison.
The additional elements (6) to (7) are mere data gathering/outputting recited at a high level of generality, and thus are insignificant extra-solution activities. See MPEP § 2106.05(g). Furthermore, all uses of the recited judicial exception require such data gathering/outputting, and, as such, the additional elements do not impose any meaningful limits on the claim. The additional elements amount to necessary data gathering/outputting. See MPEP § 2106.05.
Accordingly, even when viewed in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as a combination do not amount to significantly more than the abstract idea. As discussed above with respect to integration of the abstract idea into a practical application, the claim recites the additional elements:
a processor;
a trace controller coupled to the processor to;
a sensor fusion block coupled to the processor to;
the sensor fusion block comprising circuitry to;
wherein the trace controller is further to.
The additional elements (1) to (5) amount to no more than mere instructions to apply the judicial exception using generic computer components. Mere instructions to apply a judicial exception using generic computer components cannot provide an inventive concept.
Also, the claim recites the additional elements:
store debug risk threshold information;
provide an indication of the comparison.
The additional elements (6) to (7) simply append well-understood, routine, and conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception is not indicative of an inventive concept. MPEP § 2106.05(d)(II) expressly states that the courts have recognized the computer function of receiving or transmitting data over a network, e.g., using the Internet to gather data and storing/retrieving information in memory as a well‐understood, routine, and conventional computer function when it is claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activities. Thus, a person of ordinary skill in the art would readily comprehend that it is well-understood, routine, and conventional in the computing art to store information and provide/output an indication. Therefore, the limitations remain insignificant extra-solution activities even upon reconsideration and do not amount to significantly more.
Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as a combination adds nothing that is not already present when looking at the additional elements taken individually. Even when considered in combination, the additional elements represent mere instructions to apply a judicial exception using generic computer components and insignificant extra-solution activities, and therefore do not provide an inventive concept. The claim is not patent eligible.
Claims 3-6 are rejected under 35 U.S.C. 101 as directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more for at least the reasons stated above.
Claim 3 recites the limitations:
wherein the collected operation parameters include one or more of voltage information and temperature information; and
wherein the circuitry is further to;
provide the indication based on a comparison of one or more of the voltage information against a stored debug voltage risk threshold and the temperature information against a stored debug temperature risk threshold.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim 4 recites the limitations:
wherein the trace controller is further to;
adjust a number of null packets inserted into a trace export stream based at least in part on the provided indication of the comparison.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim 5 recites the limitations:
wherein the trace controller is further to;
adjust a trace export clock based at least in part on the provided indication of the comparison.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim 6 recites the limitations:
wherein the trace controller is further to;
adjust a trace verbosity level based at least in part on the provided indication of the comparison.
These claims are dependent on Claim 1, but do not add any feature or subject matter that would solve the judicial exception deficiencies of Claim 1.
Claims 4-6 (additional element (b) recited in Claims 4-6) recite further mental steps which can be practically performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper and thus, fail to make the claim any less abstract (see MPEP § 2106.04(a)(2)(III)).
Claims 3-6 recite further additional elements that do not integrate the judicial exception into a practical application of the judicial exception. Specifically, the additional element (b) recited in Claim 3 and the additional element (a) recited in Claims 4-6 fail to meaningfully limit the claim because they amount to no more than mere instructions to apply the judicial exception using generic computer components. See MPEP § 2106.05(f).
The additional element (a) recited in Claim 3 fails to meaningfully limit the claim because it amounts to merely indicating a field of use or technological environment in which to apply a judicial exception which does not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application. See MPEP § 2106.05(h).
The additional element (c) recited in Claim 3 fails to meaningfully limit the claim because it is mere data outputting recited at a high level of generality, and thus are insignificant extra-solution activities. See MPEP § 2106.05(g).
Therefore, Claims 3-6 when considered both individually and as a combination fail to integrate the abstract idea into a practical application.
The additional elements recited in Claims 3-6 are also not sufficient to amount to significantly more than the judicial exception. Specifically, Claims 4-6 do not amount to significantly more than the abstract idea because they recite further mental steps that fail to make the claim any less abstract.
The additional element (b) recited in Claim 3 and the additional element (a) recited in Claims 4-6 do not amount to significantly more than the abstract idea because they amount to no more than mere instructions to apply the judicial exception using generic computer components which cannot provide an inventive concept. See MPEP § 2106.05(f).
The additional element (a) recited in Claim 3 does not amount to significantly more because it amounts to merely indicating a field of use or technological environment in which to apply a judicial exception which does not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application. See MPEP § 2106.05(h).
The additional element (c) recited in Claim 3 does not amount to significantly more because it is mere data outputting recited at a high level of generality, and thus is an insignificant extra-solution activity which simply appends well-understood, routine, and conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception is not indicative of an inventive concept. MPEP § 2106.05(d)(II) expressly states that the courts have recognized the computer function of receiving or transmitting data over a network, e.g., using the Internet to gather data as a well‐understood, routine, and conventional computer function when it is claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activities. Thus, a person of ordinary skill in the art would readily comprehend that it is well-understood, routine, and conventional in the computing art to provide/output an indication.
Therefore, Claims 3-6 do not add any steps or additional elements, when considered both individually and as a combination, that amount to significantly more than the above-identified judicial exception that would convert Claim 1 into patent-eligible subject matter.
Claims 1 and 3-6 are therefore not drawn to patent-eligible subject matter as they are directed to an abstract idea without significantly more.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim Interpretation: Under the broadest reasonable interpretation (BRI), the limitations of Claim 7 are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. See MPEP § 2111.
Step 1: Claim 7 is directed to a system, which is a machine, and falls within one of the statutory categories of invention.
Step 2A, Prong One: Claim 7 recites the limitations:
monitor one or more sensors;
determine a debug condition based on the monitored one or more sensors; and
adjust a debug operation based at least in part on the provided indication of the debug condition.
These recited steps, under the broadest reasonable interpretation (BRI), cover performance of the steps in the human mind alone or with the aid of pen and paper. That is, other than reciting:
first circuitry to;
second circuitry coupled to the first circuitry to.
Nothing in the claim precludes the steps from practically being performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper. For example, the limitation (a) in the context of the claim encompasses a human observing one or more sensors using observation, evaluation, judgment, and opinion to mentally monitor one or more sensors. The limitation (b) in the context of the claim encompasses a human observing sensors using observation, evaluation, judgment, and opinion to mentally determine a debug condition based on the monitored sensors. The limitation (c) in the context of the claim encompasses a human observing an indication of a debug condition using observation, evaluation, judgment, and opinion to mentally adjust a debug operation in the human mind alone or with the aid of pen and paper. See MPEP § 2106.04(a)(2)(III).
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind alone or with the aid of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A, Prong Two: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements:
first circuitry to;
second circuitry coupled to the first circuitry to.
The additional elements (1) to (2) are recited at a high-level of generality such that they amount to no more than mere instructions to apply the judicial exception using generic computer components. The first circuitry is used as a tool to perform the monitoring, determining, and providing steps of the claim. The second circuitry is used as a tool to perform the adjusting step of the claim. See MPEP § 2106.05(f).
Also, the claim recites the additional element:
provide an indication of the debug condition.
The additional element (3) is mere data outputting recited at a high level of generality, and thus is an insignificant extra-solution activity. See MPEP § 2106.05(g). Furthermore, all uses of the recited judicial exception require such data outputting, and, as such, the additional element does not impose any meaningful limits on the claim. The additional element amount to necessary data outputting. See MPEP § 2106.05.
Accordingly, even when viewed in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as a combination do not amount to significantly more than the abstract idea. As discussed above with respect to integration of the abstract idea into a practical application, the claim recites the additional elements:
first circuitry to;
second circuitry coupled to the first circuitry to.
The additional elements (1) to (2) amount to no more than mere instructions to apply the judicial exception using generic computer components. Mere instructions to apply a judicial exception using generic computer components cannot provide an inventive concept.
Also, the claim recites the additional element:
provide an indication of the debug condition.
The additional element (3) simply appends well-understood, routine, and conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception is not indicative of an inventive concept. MPEP § 2106.05(d)(II) expressly states that the courts have recognized the computer function of receiving or transmitting data over a network, e.g., using the Internet to gather data as a well‐understood, routine, and conventional computer function when it is claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activities. Thus, a person of ordinary skill in the art would readily comprehend that it is well-understood, routine, and conventional in the computing art to provide/output an indication. Therefore, the limitations remain insignificant extra-solution activities even upon reconsideration and do not amount to significantly more.
Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as a combination adds nothing that is not already present when looking at the additional elements taken individually. Even when considered in combination, the additional elements represent mere instructions to apply a judicial exception using generic computer components and insignificant extra-solution activities, and therefore do not provide an inventive concept. The claim is not patent eligible.
Claims 8-13 are rejected under 35 U.S.C. 101 as directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more for at least the reasons stated above.
Claim 8 recites the limitations:
wherein the one or more sensors are to provide one or more of voltage information and temperature information; and
wherein the first circuitry is further to;
determine the debug condition based on one or more of the voltage information and temperature information.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim 9 recites the limitations:
wherein the second circuitry is further to;
adjust an amount of debug invasiveness based at least in part on the provided indication of the debug condition.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim 10 recites the limitations:
wherein the second circuitry is further to;
adjust an output bandwidth of trace debug data based at least in part on the provided indication of the debug condition.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim 11 recites the limitations:
wherein the second circuitry is further to;
adjust a number of null packets inserted into a trace export stream based at least in part on the provided indication of the debug condition.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim 12 recites the limitations:
wherein the second circuitry is further to;
adjust a trace export clock based at least in part on the provided indication of the debug condition.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim 13 recites the limitations:
wherein the second circuitry is further to;
adjust a trace verbosity level based at least in part on the provided indication of the debug condition.
These claims are dependent on Claim 7, but do not add any feature or subject matter that would solve the judicial exception deficiencies of Claim 7.
Claims 8-13 (additional element (c) recited in Claim 8, additional element (b) recited in Claims 9-13) recite further mental steps which can be practically performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper and thus, fail to make the claim any less abstract (see MPEP § 2106.04(a)(2)(III)).
Claims 8-13 recite further additional elements that do not integrate the judicial exception into a practical application of the judicial exception. Specifically, the additional element (b) recited in Claim 8 and the additional element (a) recited in Claims 9-13 fail to meaningfully limit the claim because they amount to no more than mere instructions to apply the judicial exception using generic computer components. See MPEP § 2106.05(f).
The additional element (a) recited in Claim 8 fails to meaningfully limit the claim because it is mere data outputting recited at a high level of generality, and thus is an insignificant extra-solution activity. See MPEP § 2106.05(g).
Therefore, Claims 8-13 when considered both individually and as a combination fail to integrate the abstract idea into a practical application.
The additional elements recited in Claims 8-13 are also not sufficient to amount to significantly more than the judicial exception. Specifically, Claims 8-13 do not amount to significantly more than the abstract idea because they recite further mental steps that fail to make the claim any less abstract.
The additional element (b) recited in Claim 8 and the additional element (a) recited in Claims 9-13 do not amount to significantly more than the abstract idea because they amount to no more than mere instructions to apply the judicial exception using generic computer components which cannot provide an inventive concept. See MPEP § 2106.05(f).
The additional element (a) recited in Claim 8 does not amount to significantly more because it is mere data outputting recited at a high level of generality, and thus is an insignificant extra-solution activity which simply appends well-understood, routine, and conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception is not indicative of an inventive concept. MPEP § 2106.05(d)(II) expressly states that the courts have recognized the computer function of receiving or transmitting data over a network, e.g., using the Internet to gather data as a well‐understood, routine, and conventional computer function when it is claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activities. Thus, a person of ordinary skill in the art would readily comprehend that it is well-understood, routine, and conventional in the computing art to provide information.
Therefore, Claims 8-13 do not add any steps or additional elements, when considered both individually and as a combination, that amount to significantly more than the above-identified judicial exception that would convert Claim 7 into patent-eligible subject matter.
Claims 7-13 are therefore not drawn to patent-eligible subject matter as they are directed to an abstract idea without significantly more.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim Interpretation: Under the broadest reasonable interpretation (BRI), the limitations of Claim 14 are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. See MPEP § 2111.
Step 1: Claim 14 is directed to a system, which is a machine, and falls within one of the statutory categories of invention.
Step 2A, Prong One: Claim 14 recites the limitations:
compare sensor information against the stored debug risk threshold information.
These recited steps, under the broadest reasonable interpretation (BRI), cover performance of the steps in the human mind alone or with the aid of pen and paper. That is, other than reciting:
sensor fusion circuitry coupled to the memory to.
Nothing in the claim precludes the steps from practically being performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper. For example, the limitation (a) in the context of the claim encompasses a human observing sensor information and threshold information using observation, evaluation, judgment, and opinion to mentally compare the sensor information against the threshold information. See MPEP § 2106.04(a)(2)(III).
If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind alone or with the aid of pen and paper but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
Step 2A, Prong Two: This judicial exception is not integrated into a practical application. In particular, the claim recites the additional elements:
memory to;
sensor fusion circuitry coupled to the memory to.
The additional elements (1) to (2) are recited at a high-level of generality such that they amount to no more than mere instructions to apply the judicial exception using generic computer components. The memory is used as a tool to perform the storing step of the claim. The sensor fusion circuitry coupled to the memory is used as a tool to perform the comparing and providing steps of the claim. See MPEP § 2106.05(f).
Also, the claim recites the additional elements:
store debug risk threshold information;
provide an indication of the comparison.
The additional elements (3) to (4) are mere data gathering/outputting recited at a high level of generality, and thus are insignificant extra-solution activities. See MPEP § 2106.05(g). Furthermore, all uses of the recited judicial exception require such data gathering/outputting, and, as such, the additional elements do not impose any meaningful limits on the claim. The additional elements amount to necessary data gathering/outputting. See MPEP § 2106.05.
Accordingly, even when viewed in combination, the additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Step 2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements when considered both individually and as a combination do not amount to significantly more than the abstract idea. As discussed above with respect to integration of the abstract idea into a practical application, the claim recites the additional elements:
memory to;
sensor fusion circuitry coupled to the memory to.
The additional elements (1) to (2) amount to no more than mere instructions to apply the judicial exception using generic computer components. Mere instructions to apply a judicial exception using generic computer components cannot provide an inventive concept.
Also, the claim recites the additional elements:
store debug risk threshold information;
provide an indication of the comparison.
The additional elements (3) to (4) simply append well-understood, routine, and conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception is not indicative of an inventive concept. MPEP § 2106.05(d)(II) expressly states that the courts have recognized the computer function of receiving or transmitting data over a network, e.g., using the Internet to gather data and storing/retrieving information in memory as a well‐understood, routine, and conventional computer function when it is claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activities. Thus, a person of ordinary skill in the art would readily comprehend that it is well-understood, routine, and conventional in the computing art to store information and provide/output an indication. Therefore, the limitations remain insignificant extra-solution activities even upon reconsideration and do not amount to significantly more.
Thus, taken alone, the additional elements do not amount to significantly more than the above-identified judicial exception (the abstract idea). Looking at the additional elements as a combination adds nothing that is not already present when looking at the additional elements taken individually. Even when considered in combination, the additional elements represent mere instructions to apply a judicial exception using generic computer components and insignificant extra-solution activities, and therefore do not provide an inventive concept. The claim is not patent eligible.
Claims 15 and 17-20 are rejected under 35 U.S.C. 101 as directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more for at least the reasons stated above.
Claim 15 recites the limitations:
wherein the sensor fusion circuitry is further to;
provide the indication of the comparison to one or more of a trace controller and a debug system.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim 17 recites the limitations:
wherein the sensor information includes one or more of voltage information and temperature information; and
wherein the sensor fusion circuitry is further to;
provide the indication based on a comparison of one or more of the voltage information against a stored debug voltage risk threshold and the temperature information against a stored debug temperature risk threshold.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim 18 recites the limitations:
further comprising debug circuitry coupled to the sensor fusion circuitry to;
adjust a debug operation based at least in part on the provided indication of the comparison.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim 19 recites the limitations:
wherein the debug circuitry is further to;
reduce a debug operation invasiveness if the indication of the comparison corresponds to an abnormal operation condition.
<<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>> + <<>>
Claim 20 recites the limitations:
wherein the debug circuitry is further to;
adjust an output bandwidth of trace debug data based at least in part on the provided indication of the comparison.
These claims are dependent on Claim 14, but do not add any feature or subject matter that would solve the judicial exception deficiencies of Claim 14.
Claims 18-20 (additional element (b) recited in Claims 18-20) recite further mental steps which can be practically performed in the human mind alone using observation, evaluation, judgment, and opinion or with the aid of pen and paper and thus, fail to make the claim any less abstract (see MPEP § 2106.04(a)(2)(III)).
Claims 15 and 17-20 recite further additional elements that do not integrate the judicial exception into a practical application of the judicial exception. Specifically, the additional element (a) recited in Claim 15, the additional element (b) recited in Claim 17, the additional element (a) recited in Claim 18, the additional element (a) recited in Claim 19, and the additional element (a) recited in Claim 20 fail to meaningfully limit the claim because they amount to no more than mere instructions to apply the judicial exception using generic computer components. See MPEP § 2106.05(f).
The additional element (a) recited in Claim 17 fails to meaningfully limit the claim because it amounts to merely indicating a field of use or technological environment in which to apply a judicial exception which does not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application. See MPEP § 2106.05(h).
The additional element (b) recited in Claim 15 and the additional element (c) recited in Claim 17 fail to meaningfully limit the claim because they are mere data outputting recited at a high level of generality, and thus are insignificant extra-solution activities. See MPEP § 2106.05(g).
Therefore, Claims 15 and 17-20 when considered both individually and as a combination fail to integrate the abstract idea into a practical application.
The additional elements recited in Claims 15 and 17-20 are also not sufficient to amount to significantly more than the judicial exception. Specifically, Claims 18-20 do not amount to significantly more than the abstract idea because they recite further mental steps that fail to make the claim any less abstract.
The additional element (a) recited in Claim 15, the additional element (b) recited in Claim 17, the additional element (a) recited in Claim 18, the additional element (a) recited in Claim 19, and the additional element (a) recited in Claim 20 do not amount to significantly more than the abstract idea because they amount to no more than mere instructions to apply the judicial exception using generic computer components which cannot provide an inventive concept. See MPEP § 2106.05(f).
The additional element (a) recited in Claim 17 does not amount to significantly more because it amounts to merely indicating a field of use or technological environment in which to apply a judicial exception which does not amount to significantly more than the exception itself, and cannot integrate a judicial exception into a practical application. See MPEP § 2106.05(h).
The additional element (b) recited in Claim 15 and the additional element (c) recited in Claim 17 do not amount to significantly more because they are mere data outputting recited at a high level of generality, and thus are insignificant extra-solution activities which simply appends well-understood, routine, and conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception is not indicative of an inventive concept. MPEP § 2106.05(d)(II) expressly states that the courts have recognized the computer function of receiving or transmitting data over a network, e.g., using the Internet to gather data as a well‐understood, routine, and conventional computer function when it is claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activities. Thus, a person of ordinary skill in the art would readily comprehend that it is well-understood, routine, and conventional in the computing art to provide an indication.
Therefore, Claims 15 and 17-20 do not add any steps or additional elements, when considered both individually and as a combination, that amount to significantly more than the above-identified judicial exception that would convert Claim 14 into patent-eligible subject matter.
Claims 14-15 and 17-20 are therefore not drawn to patent-eligible subject matter as they are directed to an abstract idea without significant more.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over US 2011/0067008 (hereinafter “Srivastava”) in view of US 2019/0073268 (hereinafter “Kantor”), US 9,490,995 (hereinafter “Salvo”), US 2017/0308491 (hereinafter “Gibbs”), and US 2015/0202770 (hereinafter “Patron”).
As per Claim 1, Srivastava discloses:
An apparatus (Figure 5), comprising:
a processor (paragraph [0098], “Computer system 500 includes a bus 502 or other communication mechanism for communicating information, and a hardware processor 504 coupled with bus 502 for processing information.”); the [processor] to:
collect operation parameters (paragraph [0019], “According to one technique, the adaptive trace logging module obtains [collects] input data [operation parameters] about trace logging behavior and computing resources (e.g., disk space and CPU cycles) used by trace logging operations. This input data may include, for example, a number of trace log messages added to a trace log in a period of time (trace logging volume), an amount of storage space available on a non-volatile computer-readable storage medium that stores a trace log (available disk space), a latency of an operation comprising writing a trace log message to a trace log (trace logging operation latency), a size of a trace log (trace log size), or any other metric or combination of metrics suitable for determining trace logging's impact on available computing resources (emphasis added).”; paragraph [0071], “In one embodiment, the adaptive trace logging module makes a decision whether to take action based on comparing obtained input data to threshold values.”);
compare collected operation parameters against the [threshold information] (paragraph [0019], “According to one technique, the adaptive trace logging module obtains input data [collected operation parameters] about trace logging behavior and computing resources (e.g., disk space and CPU cycles) used by trace logging operations. This input data may include, for example, a number of trace log messages added to a trace log in a period of time (trace logging volume), an amount of storage space available on a non-volatile computer-readable storage medium that stores a trace log (available disk space), a latency of an operation comprising writing a trace log message to a trace log (trace logging operation latency), a size of a trace log (trace log size), or any other metric or combination of metrics suitable for determining trace logging's impact on available computing resources […] In one embodiment, such determination is made by determining [comparing] whether the input data exceeds threshold values. If the adaptive trace logging module determines that an action should be taken, the adaptive trace logging module takes action to reduce an amount of computing resources consumed by trace logging operations. Such action may include, for example, changing the trace logging level of an executing software program so as to reduce the number of trace logging messages added to a trace log (emphasis added).”);
[…] adjust an amount of debug invasiveness based on the [comparison] (paragraph [0019], “In one embodiment, such determination is made by determining [comparing] whether the input data exceeds threshold values. If the adaptive trace logging module determines that an action should be taken, the adaptive trace logging module takes action to reduce an amount of computing resources consumed by trace logging operations [adjust an amount of debug invasiveness]. Such action may include, for example, changing the trace logging level of an executing software program so as to reduce the number of trace logging messages added to a trace log (emphasis added).”; paragraph [0071], “In one embodiment, the adaptive trace logging module makes a decision whether to take action based on comparing obtained input data to threshold values. For example, if the frequency or volume of trace logging messages generated by a particular software module exceeds a threshold, then the adaptive trace logging module may determine to take action to reduce the frequency or volume of trace logging messages generated by the particular software module.”).
Srivastav discloses “the comparison” and “[…] adjust an amount of debug invasiveness based on the [comparison],” but does not explicitly disclose:
provide an indication of the comparison;
[…] adjust an amount of debug invasiveness based on the provided indication of the comparison.
However, Kantor discloses:
provide an indication of the comparison (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition [comparison], the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”).
Srivastav is within the same field of endeavor as the claimed invention regarding tracing/debugging and comparing data against a threshold. Kantor is also within the same field of endeavor as the claimed invention regarding debug conditions and providing an indication of a comparison.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kantor into the teaching of Srivastav to include “provide an indication of the comparison; […] adjust an amount of debug invasiveness based on the provided indication of the comparison.” The modification would be obvious because one of ordinary skill in the art would be motivated to raise a flag or provide some other indication that a debug condition was satisfied in order to effectively notify that a problem/error occurred (Kantor, paragraphs [0036 & 0069]).
The combination of Srivastav and Kantor does not explicitly disclose:
store debug risk threshold information.
However, Salvo discloses:
store debug risk threshold information (col. 7 lines 11-17, “If debugging field 440 is not selected by the user, application 220 may store a default threshold level associated with the types of features being tested and/or the type of device being tested. Application 220 may use the default threshold level to determine, based on the simulation result, whether debugging of the simulation should occur (emphasis added).”).
Salvo is within the same field of endeavor as the claimed invention regarding debugging and storing threshold information.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Salvo into the combined teachings of Srivastav and Kantor to include “store debug risk threshold information.” The modification would be obvious because one of ordinary skill in the art would be motivated to store threshold information for quick access and to help prevent losing this data (Salvo, col. 7 lines 11-17).
The combination of Srivastav, Kantor, and Salvo discloses “the processor” and “[…] adjust an amount of debug invasiveness based on the provided indication of the comparison,” but does not explicitly disclose:
a trace controller coupled to the processor to aggregate trace debug data;
wherein the trace controller is further to adjust an amount of debug invasiveness based on the provided indication of the comparison.
However, Gibbs discloses:
a trace controller coupled to the [trace sources] to aggregate trace debug data (abstract, “An apparatus [trace controller] and method are provided for combining trace data from a plurality of trace sources. The apparatus has an input interface to receive trace data from the plurality of trace sources, and an output interface from which to issue a trace stream incorporating the trace data from each of those trace sources (emphasis added).”);
wherein the trace controller is further to […] (abstract, “An apparatus [trace controller] and method are provided for combining trace data from a plurality of trace sources. The apparatus has an input interface to receive trace data from the plurality of trace sources, and an output interface from which to issue a trace stream incorporating the trace data from each of those trace sources (emphasis added).”).
Gibbs is within the same field of endeavor as the claimed invention regarding the aggregation of trace data.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Gibbs into the combined teachings of Srivastav, Kantor, and Salvo to include “a trace controller coupled to the processor to aggregate trace debug data; wherein the trace controller is further to adjust an amount of debug invasiveness based on the provided indication of the comparison.” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize a system that aggregates trace data from various sources and uses a network of interconnected funnel elements that dynamically adjust timing allocations in order to ensure that each trace source obtains the desired proportion of the bandwidth in the output trace stream ultimately alleviating potential bandwidth-related issues (Gibbs, paragraphs [0003, 0004, & 0021]).
The combination of Srivastav, Kantor, Salvo, and Gibbs does not explicitly disclose:
a sensor fusion block coupled to the processor to […];
the sensor fusion block comprising circuitry to […].
However, Patron discloses:
a sensor fusion block coupled to the processor to […] (paragraph [0511], “The sensory fusion circuitry 5908 may include a set of sensors (e.g., the sensors of the sensor system 102) and/or the sensory fusion algorithm 5910 (e.g., the sensor fusion algorithm 238). The sensory fusion circuitry 5908 may execute a command (e.g., the command 5912 of the sensory fusion algorithm 5910 and/or the projection command) using the processor 5904 and/or the memory 5906 (emphasis added).”);
the sensor fusion block comprising circuitry to […] (paragraph [0511], “The sensory fusion circuitry 5908 may include a set of sensors (e.g., the sensors of the sensor system 102) and/or the sensory fusion algorithm 5910 (e.g., the sensor fusion algorithm 238). The sensory fusion circuitry 5908 may execute a command (e.g., the command 5912 of the sensory fusion algorithm 5910 and/or the projection command) using the processor 5904 and/or the memory 5906 (emphasis added).”).
Patron is within the same field of endeavor as the claimed invention regarding the utilization of sensor fusion circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Patron into the combined teachings of Srivastav, Kantor, Salvo, and Gibbs to include “a sensor fusion block coupled to the processor to […]; the sensor fusion block comprising circuitry to […].” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize sensor fusion circuitry that uses data from multiple sensors in order to effectively gain a more accurate and holistic/comprehensive view of a system/environment (Patron, paragraphs [0183 & 0485]).
As per Claim 3, the rejection of Claim 1 is incorporated; and Srivastav discloses “the collected operation parameters (paragraph [0019], “According to one technique, the adaptive trace logging module obtains [collects] input data [operation parameters] about trace logging behavior and computing resources (e.g., disk space and CPU cycles) used by trace logging operations. This input data may include, for example, a number of trace log messages added to a trace log in a period of time (trace logging volume), an amount of storage space available on a non-volatile computer-readable storage medium that stores a trace log (available disk space), […] or any other metric or combination of metrics suitable for determining trace logging's impact on available computing resources (emphasis added).”),” but the combination of Srivastav, Gibbs, and Patron does not explicitly disclose:
wherein the collected operation parameters include one or more of voltage information and temperature information; and
wherein the circuitry is further to: provide the indication based on a comparison of one or more of the voltage information against a stored debug voltage risk threshold and the temperature information against a stored debug temperature risk threshold.
However, Kantor discloses:
wherein the collected operation parameters include one or more of voltage information and temperature information (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied (emphasis added).”); and
wherein the circuitry is further to: provide the indication based on a comparison of one or more of the voltage information against a stored debug voltage risk threshold and the temperature information against a [debug temperature risk threshold] (Figure 1; paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”; paragraph [0022], “The data path 135 of the storage controller 120 may include a variety of busses, processing units, and other circuitry to receive/send information from/to the host device 110, process the information, and send/receive the information to/from the non-volatile storage 115.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kantor into the combined teachings of Srivastav, Gibbs, and Patron to include “wherein the collected operation parameters include one or more of voltage information and temperature information, and wherein the circuitry is further to: provide the indication based on a comparison of one or more of the voltage information against a stored debug voltage risk threshold and the temperature information against a [debug temperature risk threshold].” The modification would be obvious because one of ordinary skill in the art would be motivated to monitor temperature sensors to detect an unusual raise in the temperature of a component and raise a flag in order to effectively notify that a problem/error may have occurred and facilitate diagnosis (Kantor, paragraphs [0015, 0036, 0069]).
The combination of Srivastav, Kantor, Gibbs, and Patron discloses “debug temperature risk threshold,” but does not explicitly disclose:
stored debug temperature risk threshold.
However, Salvo discloses:
stored [debug risk threshold information] (col. 7 lines 11-17, “If debugging field 440 is not selected by the user, application 220 may store a default threshold level associated with the types of features being tested and/or the type of device being tested. Application 220 may use the default threshold level to determine, based on the simulation result, whether debugging of the simulation should occur (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Salvo into the combined teachings of Srivastav, Kantor, Gibbs, and Patron to include “stored debug temperature risk threshold.” The modification would be obvious because one of ordinary skill in the art would be motivated to store threshold information for quick access and to help prevent losing this data (Salvo, col. 7 lines 11-17).
As per Claim 6, the rejection of Claim 1 is incorporated; and Srivastav discloses “adjust a trace verbosity level based at least in part on the [comparison] (paragraph [0047], “When a trace logging level is based on a range of tracing severity, adaptive trace logging module 106 can adjust a trace logging level to control the amount of trace logging messages added to a trace log [adjusting trace verbosity level]. In general, when the adaptive trace logging module increases a trace logging level (i.e., from less severe to more severe), the number of trace logging messages subsequently added by the adaptive trace logging module to a trace log is reduced. Conversely, when the adaptive trace logging module deceases a trace logging level (i.e., from more severe to less severe), the number of trace logging messages subsequently added by the adaptive trace logging module to a trace log is increased (emphasis added).”; paragraph [0019], “In one embodiment, such determination is made by determining whether the input data exceeds threshold values [comparison]. If the adaptive trace logging module determines that an action should be taken, the adaptive trace logging module takes action to reduce an amount of computing resources consumed by trace logging operations. Such action may include, for example, changing the trace logging level of an executing software program so as to reduce the number of trace logging messages added to a trace log (emphasis added).”),” but the combination of Srivastav, Salvo, Gibbs, and Patron does not explicitly disclose:
adjust a trace verbosity level based at least in part on the provided indication of the comparison.
However, Kantor discloses:
the provided indication of the comparison (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition [comparison], the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kantor into the combined teachings of Srivastav, Salvo, Gibbs, and Patron to include “adjust a trace verbosity level based at least in part on the provided indication of the comparison.” The modification would be obvious because one of ordinary skill in the art would be motivated to raise a flag or provide some other indication that a debug condition was satisfied in order to effectively notify that a problem/error occurred (Kantor, paragraphs [0036 & 0069]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Srivastava in view of Kantor, Salvo, Gibbs, and Patron as applied to Claim 1 above, and further in view of US 2008/0052683 (hereinafter “Bates”).
As per Claim 2, the rejection of Claim 1 is incorporated; and the combination of Srivastava, Kantor, Salvo, Gibbs, and Patron does not explicitly disclose:
trigger an interrupt if the comparison indicates an abnormal operation condition.
However, Bates discloses:
trigger an interrupt if the comparison indicates an abnormal operation condition (paragraph [0010], “Only if a conditional breakpoint is encountered, and the value(s) of the variable(s) specified as the condition of the breakpoint are something other than what was expected [abnormal operation condition], is program execution halted (emphasis added).”; paragraph [0016], “During execution, the system maintains a record of the breakpoints or blockpoints encountered (whether or not a breakpoint was actually fired). When a new breakpoint is encountered in execution, the system compares the expected code path condition with the actual breakpoints or blockpoints encountered during execution. If the actual code path does not match the expectation [abnormal operation condition], the conditional breakpoint is fired [triggering an interrupt], regardless of the condition of any key variable specified as a condition of the conditional breakpoint (emphasis added).”; paragraph [0077], “Once the breakpoint is fired, the debugger halts execution and allows the programmer to examine the program state (block 620). Typically, the debugger will display the location in the code at which execution was halted, and the reasons for halting execution (i.e., the condition which caused the breakpoint to fire).”).
Bates is within the same field of endeavor as the claimed invention regarding debugging and triggering interrupts.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Bates into the combined teachings of Srivastav, Kantor, Salvo, Gibbs, and Patron to include “trigger an interrupt if the comparison indicates an abnormal operation condition.” The modification would be obvious because one of ordinary skill in the art would be motivated to trigger an interrupt when an abnormal/unexpected condition arises in order to improve the odds that strange and unusual program conditions, not anticipated by the programmer, will be appropriately identified (Bates, paragraph [0017]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Srivastava in view of Kantor, Salvo, Gibbs, and Patron as applied to Claim 1 above, and further in view of US 6,744,789 (hereinafter “Michener”).
As per Claim 4, the rejection of Claim 1 is incorporated; and the combination of Srivastava, Salvo, Gibbs, and Patron does not explicitly disclose:
adjust a number of null packets inserted into a trace export stream based at least in part on the provided indication of the comparison.
However, Michener discloses:
adjust a number of null packets inserted into a trace export stream based at least in part on [the comparison] (col. 13 lines 55-65, “In one embodiment, this is implemented by examining an I/O ledger comparing the number of bytes in the input data packets and the number of bytes in the output data packets. If the difference in the rate of input data (computed, for example, from the input clock rate and the number of input data units--e.g. bytes/bits/packets--) and the rate of output data (computed, for example, from the output clock rate and the number of output data units) exceeds a threshold amount, null packets are added to the output data stream, the ledger is adjusted, and the result is transmitted, as shown in blocks 1016-1018 (emphasis added).”).
Michener is within the same field of endeavor as the claimed invention regarding the adjustment of null packets.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Michener into the combined teachings of Srivastav, Salvo, Gibbs, and Patron to include “adjust a number of null packets inserted into a trace export stream based at least in part on [the comparison].” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize a system that adds null packets depending on whether a threshold has been exceeded in order to help provide a system that translates data packets to different protocols without losing signal quality or requiring additional bandwidth or hardware (Michener, col. 2 lines 5-9 & col. 13 lines 55-65).
The combination of Srivastav, Salvo, Gibbs, Patron, and Michener discloses “adjust a number of null packets inserted into a trace export stream based at least in part on [the comparison],” but does not explicitly disclose:
adjust a number of null packets inserted into a trace export stream based at least in part on the provided indication of the comparison.
However, Kantor discloses:
the provided indication of the comparison (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition [comparison], the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kantor into the combined teachings of Srivastav, Salvo, Gibbs, Patron, and Michener to include “adjust a number of null packets inserted into a trace export stream based at least in part on the provided indication of the comparison.” The modification would be obvious because one of ordinary skill in the art would be motivated to raise a flag or provide some other indication that a debug condition was satisfied in order to effectively notify that a problem/error occurred (Kantor, paragraphs [0036 & 0069]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Srivastava in view of Kantor, Salvo, Gibbs, and Patron as applied to Claim 1 above, and further in view of US 5,805,867 (hereinafter “Kodaira”).
As per Claim 5, the rejection of Claim 1 is incorporated; and the combination of Srivastava, Salvo, Gibbs, and Patron does not explicitly disclose:
adjust a trace export clock based at least in part on the provided indication of the comparison.
However, Kodaira discloses:
adjust a trace export clock based at least in part on the [frequency] (Figure 21; col. 14 lines 50-52, “Taking it into consideration that the frequency of the clock CLKA is different from that of the clock CLKB, the process 41 adjusts the clocks and edits the trace information (emphasis added).”).
Kodaira is within the same field of endeavor as the claimed invention regarding debugging and adjusting trace clocks.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kodaira into the combined teachings of Srivastav, Salvo, Gibbs, and Patron to include “adjust a trace export clock based at least in part on the [frequency].” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize a system adjusts trace clocks and edit trace information in order to effectively put time-matched trace information into a trace file and synchronize trace information between simulators that provide easier debugging compared to debugging conducted with actual devices (Kodaira, col. 14 lines 50-60 & col. 15 lines 17-22).
The combination of Srivastav, Salvo, Gibbs, Patron, and Kodaira discloses “adjust a trace export clock based at least in part on the [frequency],” but does not explicitly disclose:
adjust a trace export clock based at least in part on the provided indication of the comparison.
However, Kantor discloses:
the provided indication of the comparison (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition [comparison], the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kantor into the combined teachings of Srivastav, Salvo, Gibbs, Patron, and Kodaira to include “adjust a trace export clock based at least in part on the provided indication of the comparison.” The modification would be obvious because one of ordinary skill in the art would be motivated to raise a flag or provide some other indication that a debug condition was satisfied in order to effectively notify that a problem/error occurred (Kantor, paragraphs [0036 & 0069]).
Claims 7-9 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Kantor in view of Srivastava.
As per Claim 7, Kantor discloses:
An apparatus (Figure 1), comprising:
first circuitry to monitor one or more sensors (Figure 1; paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied (emphasis added).”; paragraph [0022], “The data path 135 of the storage controller 120 may include a variety of busses, processing units, and other circuitry to receive/send information from/to the host device 110, process the information, and send/receive the information to/from the non-volatile storage 115.”);
determine a debug condition based on the monitored one or more sensors (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”), and
provide an indication of the debug condition (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”).
Kantor discloses “the first circuitry” and “the provided indication of the debug condition,” but does not explicitly disclose:
second circuitry coupled to the first circuitry to adjust a debug operation based at least in part on the provided indication of the debug condition.
However, Srivastav discloses:
second circuitry coupled to the first circuitry to adjust a debug operation based at least in part on the [comparison] (Figure 5; paragraph [0019], “In one embodiment, such determination is made by determining [comparing] whether the input data exceeds threshold values. If the adaptive trace logging module determines that an action should be taken, the adaptive trace logging module takes action to reduce an amount of computing resources consumed by trace logging operations. Such action may include, for example, changing the trace logging level of an executing software program so as to reduce the number of trace logging messages added to a trace log (emphasis added).”; paragraph [0071], “In one embodiment, the adaptive trace logging module makes a decision whether to take action based on comparing obtained input data to threshold values. For example, if the frequency or volume of trace logging messages generated by a particular software module exceeds a threshold, then the adaptive trace logging module may determine to take action to reduce the frequency or volume of trace logging messages generated by the particular software module (emphasis added).”; paragraph [0099], “Computer system 500 also includes a main memory 506, such as a random access memory (RAM) or other dynamic storage device, coupled to bus 502 for storing information and instructions to be executed by processor 504.”).
Kantor is within the same field of endeavor as the claimed invention regarding debug conditions and providing an indication of a comparison. Srivastav is also within the same field of endeavor as the claimed invention regarding tracing/debugging and comparing data against a threshold.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Srivastav into the teaching of Kantor to include “second circuitry coupled to the first circuitry to adjust a debug operation based at least in part on the provided indication of the debug condition.” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize a system of adaptive trace logging that takes action to reduce an amount of computing resources consumed by trace logging operations in order to help prevent significant performance degradation to executing software processes that compete with trace logging operations for scarce computing resources while at the same time capturing sufficient trace logging messages useful for troubleshooting problems (Srivastav, paragraphs [0009 & 0019]).
As per Claim 8, the rejection of Claim 7 is incorporated; and Kantor further discloses:
wherein the one or more sensors are to provide one or more of voltage information and temperature information (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”), and wherein the first circuitry (Figure 1) is further to:
determine the debug condition based on one or more of the voltage information and temperature information (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”).
As per Claim 9, the rejection of Claim 7 is incorporated; and Kantor discloses “the provided indication of the debug condition (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”),” but does not explicitly disclose:
adjust an amount of debug invasiveness based at least in part on the provided indication of the debug condition.
However, Srivastav discloses:
adjust an amount of debug invasiveness based at least in part on the [comparison] (paragraph [0019], “In one embodiment, such determination is made by determining [comparing] whether the input data exceeds threshold values. If the adaptive trace logging module determines that an action should be taken, the adaptive trace logging module takes action to reduce an amount of computing resources consumed by trace logging operations [adjust an amount of debug invasiveness]. Such action may include, for example, changing the trace logging level of an executing software program so as to reduce the number of trace logging messages added to a trace log (emphasis added).”; paragraph [0071], “In one embodiment, the adaptive trace logging module makes a decision whether to take action based on comparing obtained input data to threshold values. For example, if the frequency or volume of trace logging messages generated by a particular software module exceeds a threshold, then the adaptive trace logging module may determine to take action to reduce the frequency or volume of trace logging messages generated by the particular software module.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Srivastav into the teaching of Kantor to include “adjust an amount of debug invasiveness based at least in part on the provided indication of the debug condition.” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize a system of adaptive trace logging that takes action to reduce an amount of computing resources consumed by trace logging operations in order to help prevent significant performance degradation to executing software processes that compete with trace logging operations for scarce computing resources while at the same time capturing sufficient trace logging messages useful for troubleshooting problems (Srivastav, paragraphs [0009 & 0019]).
As per Claim 13, the rejection of Claim 9 is incorporated; and Kantor discloses “the provided indication of the debug condition (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”),” but does not explicitly disclose:
adjust a trace verbosity level based at least in part on the provided indication of the debug condition.
However, Srivastav discloses:
adjust a trace verbosity level based at least in part on the [comparison] (paragraph [0047], “When a trace logging level is based on a range of tracing severity, adaptive trace logging module 106 can adjust a trace logging level to control the amount of trace logging messages added to a trace log [adjusting trace verbosity level]. In general, when the adaptive trace logging module increases a trace logging level (i.e., from less severe to more severe), the number of trace logging messages subsequently added by the adaptive trace logging module to a trace log is reduced. Conversely, when the adaptive trace logging module deceases a trace logging level (i.e., from more severe to less severe), the number of trace logging messages subsequently added by the adaptive trace logging module to a trace log is increased (emphasis added).”; paragraph [0019], “In one embodiment, such determination is made by determining whether the input data exceeds threshold values [comparison]. If the adaptive trace logging module determines that an action should be taken, the adaptive trace logging module takes action to reduce an amount of computing resources consumed by trace logging operations. Such action may include, for example, changing the trace logging level of an executing software program so as to reduce the number of trace logging messages added to a trace log (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Srivastav into the teaching of Kantor to include “adjust a trace verbosity level based at least in part on the provided indication of the debug condition.” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize a system of adaptive trace logging that adjusts a trace verbosity level and reduces an amount of computing resources consumed by trace logging operations in order to help prevent significant performance degradation to executing software processes that compete with trace logging operations for scarce computing resources while at the same time capturing sufficient trace logging messages useful for troubleshooting problems (Srivastav, paragraphs [0009 & 0019]).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kantor in view of Srivastav as applied to Claim 9 above, and further in view of WO 2016/148803 (Provided by Applicant’s IDS, hereinafter “Menon”).
As per Claim 10, the rejection of Claim 9 is incorporated; and Kantor discloses “the provided indication of the debug condition (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”),” but the combination of Kantor and Srivastav does not explicitly disclose:
adjust an output bandwidth of trace debug data based at least in part on the provided indication of the debug condition.
However, Menon discloses:
adjust an output bandwidth of trace debug data based at least in part on the [debug scenario] (paragraph [0024], “With such functional and debug architecture, power efficiency may be achieved, and output bandwidth may be modulated based on a given debug scenario (emphasis added).”; paragraph [0023], “Debug interconnect 130 may be dynamically controlled to perform both dynamic voltage and frequency scaling (DVFS) and dynamic bandwidth management system (DBMS) to effectively provide a given debug bandwidth depending on the debug scenario (emphasis added).”; paragraph [0025], “In an embodiment, DVFS may be performed in multiple steps or levels, in which one or more of voltage and frequency is increased one step at a time until bandwidth close to a desired bandwidth (e.g., target bandwidth) is achieved.”).
Menon is within the same field of endeavor as the claimed invention regarding debugging and adjusting bandwidth of data.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Menon into the combined teachings of Kantor and Srivastav to include “adjust an output bandwidth of trace debug data based at least in part on the provided indication of the debug condition.” The modification would be obvious because one of ordinary skill in the art would be motivated to adjust bandwidth of data in order to effectively handle a functional workload and help avoid/prevent bottlenecks (Menon, paragraphs [0003 & 0014]).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kantor in view of Srivastav as applied to Claim 9 above, and further in view of Michener.
As per Claim 11, the rejection of Claim 9 is incorporated; and Kantor discloses “the provided indication of the debug condition (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”),” but the combination of Kantor and Srivastav does not explicitly disclose:
adjust a number of null packets inserted into a trace export stream based at least in part on the provided indication of the debug condition.
However, Michener discloses:
adjust a number of null packets inserted into a trace export stream based at least in part on [the comparison] (col. 13 lines 55-65, “In one embodiment, this is implemented by examining an I/O ledger comparing the number of bytes in the input data packets and the number of bytes in the output data packets. If the difference in the rate of input data (computed, for example, from the input clock rate and the number of input data units--e.g. bytes/bits/packets--) and the rate of output data (computed, for example, from the output clock rate and the number of output data units) exceeds a threshold amount, null packets are added to the output data stream, the ledger is adjusted, and the result is transmitted, as shown in blocks 1016-1018. (emphasis added).”).
Michener is within the same field of endeavor as the claimed invention regarding the adjustment of null packets.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Michener into the combined teachings of Kantor and Srivastav to include “adjust a number of null packets inserted into a trace export stream based at least in part on the provided indication of the debug condition.” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize a system that adds null packets depending on whether a threshold has been exceeded in order to help provide a system that translates data packets to different protocols without losing signal quality or requiring additional bandwidth or hardware (Michener, col. 2 lines 5-9 & col. 13 lines 55-65).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kantor in view of Srivastav as applied to Claim 9 above, and further in view of Kodaira.
As per Claim 12, the rejection of Claim 9 is incorporated; and Kantor discloses “the provided indication of the debug condition (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”),” but the combination of Kantor and Srivastav does not explicitly disclose:
adjust a trace export clock based at least in part on the provided indication of the debug condition.
However, Kodaira discloses:
adjust a trace export clock based at least in part on the [frequency] (Figure 21; col. 14 lines 50-52, “Taking it into consideration that the frequency of the clock CLKA is different from that of the clock CLKB, the process 41 adjusts the clocks and edits the trace information (emphasis added).”).
Kodaira is within the same field of endeavor as the claimed invention regarding debugging and adjusting trace clocks.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kodaira into the combined teachings of Kantor and Srivastav to include “adjust a trace export clock based at least in part on the provided indication of the debug condition.” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize a system adjusts trace clocks and edit trace information in order to effectively put time-matched trace information into a trace file and synchronize trace information between simulators that provide easier debugging compared to debugging conducted with actual devices (Kodaira, col. 14 lines 50-60 & col. 15 lines 17-22).
Claims 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kantor in view of Salvo and Patron.
As per Claim 14, Kantor discloses:
An apparatus (Figure 1), comprising:
memory to […] (paragraph [0020], “The non-volatile storage 115 includes one or more storage arrays having one or more memory cells configured to store one or more bits of data.”); and
[circuitry] coupled to the memory (Figure 1; paragraph [0022], “The data path 135 of the storage controller 120 may include a variety of busses, processing units, and other circuitry to receive/send information from/to the host device 110, process the information, and send/receive the information to/from the non-volatile storage 115.”) to:
compare sensor information against the [debug risk threshold information] (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”), and
provide an indication of the comparison (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”).
Kantor discloses “memory to […]” and “debug risk threshold information,” but does not explicitly disclose:
memory to store debug risk threshold information.
However, Salvo discloses:
[…] to store debug risk threshold information (col. 7 lines 11-17, “If debugging field 440 is not selected by the user, application 220 may store a default threshold level associated with the types of features being tested and/or the type of device being tested. Application 220 may use the default threshold level to determine, based on the simulation result, whether debugging of the simulation should occur (emphasis added).”).
Kantor is within the same field of endeavor as the claimed invention regarding debug conditions and providing an indication of a comparison. Salvo is also within the same field of endeavor as the claimed invention regarding debugging and storing threshold information.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Salvo into the teaching of Kantor to include “memory to store debug risk threshold information.” The modification would be obvious because one of ordinary skill in the art would be motivated to store threshold information for quick access and to help prevent losing this data (Salvo, col. 7 lines 11-17).
The combination of Kantor and Salvo discloses “[circuitry] coupled to the memory to […],” but does not explicitly disclose:
sensor fusion circuitry coupled to the memory to […].
However, Patron discloses:
sensor fusion circuitry coupled to the memory to […] (paragraph [0511], “The sensory fusion circuitry 5908 may include a set of sensors (e.g., the sensors of the sensor system 102) and/or the sensory fusion algorithm 5910 (e.g., the sensor fusion algorithm 238). The sensory fusion circuitry 5908 may execute a command (e.g., the command 5912 of the sensory fusion algorithm 5910 and/or the projection command) using the processor 5904 and/or the memory 5906 (emphasis added).”).
Patron is within the same field of endeavor as the claimed invention regarding the utilization of sensor fusion circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Patron into the combined teachings of Kantor and Salvo to include “sensor fusion circuitry coupled to the memory to […].” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize sensor fusion circuitry that uses data from multiple sensors in order to effectively gain a more accurate and holistic/comprehensive view of a system/environment (Patron, paragraphs [0183 & 0485]).
As per Claim 17, the rejection of Claim 14 is incorporated; and Kantor discloses “wherein the sensor information includes one or more of voltage information and temperature information (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied (emphasis added).”), and wherein the [circuitry] is further to: provide the indication based on a comparison of one or more of the voltage information against a stored debug voltage risk threshold and the temperature information against a [debug temperature risk threshold] (Figure 1; paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”; paragraph [0022], “The data path 135 of the storage controller 120 may include a variety of busses, processing units, and other circuitry to receive/send information from/to the host device 110, process the information, and send/receive the information to/from the non-volatile storage 115.”),” but does not explicitly disclose:
the sensor fusion circuitry;
a stored debug temperature risk threshold.
However, Patron discloses:
the sensor fusion circuitry (paragraph [0511], “The sensory fusion circuitry 5908 may include a set of sensors (e.g., the sensors of the sensor system 102) and/or the sensory fusion algorithm 5910 (e.g., the sensor fusion algorithm 238). The sensory fusion circuitry 5908 may execute a command (e.g., the command 5912 of the sensory fusion algorithm 5910 and/or the projection command) using the processor 5904 and/or the memory 5906 (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Patron into the teaching of Kantor to include “the sensor fusion circuitry.” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize sensor fusion circuitry that uses data from multiple sensors in order to effectively gain a more accurate and holistic/comprehensive view of a system/environment (Patron, paragraphs [0183 & 0485]).
The combination of Kantor and Patron discloses “debug temperature risk threshold,” but does not explicitly disclose:
a stored debug temperature risk threshold.
However, Salvo discloses:
a stored [debug risk threshold information] (col. 7 lines 11-17, “If debugging field 440 is not selected by the user, application 220 may store a default threshold level associated with the types of features being tested and/or the type of device being tested. Application 220 may use the default threshold level to determine, based on the simulation result, whether debugging of the simulation should occur (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Salvo into the combined teachings of Kantor and Patron to include “a stored debug temperature risk threshold.” The modification would be obvious because one of ordinary skill in the art would be motivated to store threshold information for quick access and to help prevent losing this data (Salvo, col. 7 lines 11-17).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kantor in view of Salvo and Patron as applied to Claim 14 above, and further in view of Gibbs.
As per Claim 15, the rejection of Claim 14 is incorporated; and Kantor discloses “provide the indication of the comparison (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”),” but the combination of Kantor, Salvo, and Patron does not explicitly disclose:
provide the indication of the comparison to one or more of a trace controller and a debug system.
However, Gibbs discloses:
provide the [data] to one or more of a trace controller and a debug system (abstract, “An apparatus [trace controller] and method are provided for combining trace data from a plurality of trace sources. The apparatus has an input interface to receive trace data from the plurality of trace sources, and an output interface from which to issue a trace stream incorporating the trace data from each of those trace sources (emphasis added).”);
Gibbs is within the same field of endeavor as the claimed invention regarding the aggregation of trace data.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Gibbs into the combined teachings of Kantor, Salvo, and Patron to include “provide the indication of the comparison to one or more of a trace controller and a debug system.” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize a system that aggregates trace data received from various trace sources and uses a network of interconnected funnel elements that dynamically adjust timing allocations in order to ensure that each trace source obtains the desired proportion of the bandwidth in the output trace stream ultimately alleviating potential bandwidth-related issues (Gibbs, paragraphs [0003, 0004, & 0021]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kantor in view of Salvo and Patron as applied to Claim 14 above, and further in view of Bates.
As per Claim 16, the rejection of Claim 14 is incorporated; and Kantor discloses “an abnormal operation condition (paragraph [0053], “If the comparison indicates that the value of the parameter is equal to or greater than the temperature threshold (or in some cases lower than the threshold), the switcher module may determine that the debug condition has been satisfied and that there is an occurring or impending problem within the storage system 100 (emphasis added).”; paragraph [0069], “The switcher module 210 monitors one or more conditions indicative of a problem or failure within the storage system 100 and automatically triggers the firmware switch when at least one of the one or more conditions are satisfied (emphasis added).”),” but the combination of Kantor, Salvo, and Patron does not explicitly disclose:
trigger an interrupt if the comparison indicates an abnormal operation condition.
However, Bates discloses:
trigger an interrupt if the comparison indicates an abnormal operation condition (paragraph [0010], “Only if a conditional breakpoint is encountered, and the value(s) of the variable(s) specified as the condition of the breakpoint are something other than what was expected [abnormal operation condition], is program execution halted (emphasis added).”; paragraph [0016], “During execution, the system maintains a record of the breakpoints or blockpoints encountered (whether or not a breakpoint was actually fired). When a new breakpoint is encountered in execution, the system compares the expected code path condition with the actual breakpoints or blockpoints encountered during execution. If the actual code path does not match the expectation [abnormal operation condition], the conditional breakpoint is fired [triggering an interrupt], regardless of the condition of any key variable specified as a condition of the conditional breakpoint (emphasis added).”; paragraph [0077], “Once the breakpoint is fired, the debugger halts execution and allows the programmer to examine the program state (block 620). Typically, the debugger will display the location in the code at which execution was halted, and the reasons for halting execution (i.e., the condition which caused the breakpoint to fire).”).
Bates is within the same field of endeavor as the claimed invention regarding debugging and triggering interrupts.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Bates into the combined teachings of Kantor, Salvo, and Patron to include “trigger an interrupt if the comparison indicates an abnormal operation condition.” The modification would be obvious because one of ordinary skill in the art would be motivated to trigger an interrupt when an abnormal/unexpected condition arises in order to improve the odds that strange and unusual program conditions, not anticipated by the programmer, will be appropriately identified (Bates, paragraph [0017]).
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kantor in view of Salvo and Patron as applied to Claim 14 above, and further in view of Srivastava.
As per Claim 18, the rejection of Claim 14 is incorporated; and Kantor discloses “the provided indication of the comparison (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”),” but the combination of Kantor and Salvo does not explicitly disclose:
further comprising debug circuitry coupled to the sensor fusion circuitry to:
adjust a debug operation based at least in part on the provided indication of the comparison.
However, Srivastava discloses:
further comprising debug circuitry coupled to [circuitry] (Figure 5; paragraph [0099], “Computer system 500 also includes a main memory 506, such as a random access memory (RAM) or other dynamic storage device, coupled to bus 502 for storing information and instructions to be executed by processor 504.”) to:
adjust a debug operation based at least in part on the [comparison] (paragraph [0019], “In one embodiment, such determination is made by determining [comparing] whether the input data exceeds threshold values. If the adaptive trace logging module determines that an action should be taken, the adaptive trace logging module takes action to reduce an amount of computing resources consumed by trace logging operations. Such action may include, for example, changing the trace logging level of an executing software program so as to reduce the number of trace logging messages added to a trace log (emphasis added).”; paragraph [0071], “In one embodiment, the adaptive trace logging module makes a decision whether to take action based on comparing obtained input data to threshold values. For example, if the frequency or volume of trace logging messages generated by a particular software module exceeds a threshold, then the adaptive trace logging module may determine to take action to reduce the frequency or volume of trace logging messages generated by the particular software module (emphasis added).”).
Srivastav is within the same field of endeavor as the claimed invention regarding tracing/debugging and comparing data against a threshold.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Srivastav into the combined teachings of Kantor and Salvo to include “further comprising debug circuitry coupled to [circuitry] to: adjust a debug operation based at least in part on the provided indication of the comparison.” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize a system of adaptive trace logging that takes action to reduce an amount of computing resources consumed by trace logging operations in order to help prevent significant performance degradation to executing software processes that compete with trace logging operations for scarce computing resources while at the same time capturing sufficient trace logging messages useful for troubleshooting problems (Srivastav, paragraphs [0009 & 0019]).
The combination of Kantor, Salvo, and Srivastav does not explicitly disclose:
the sensor fusion circuitry.
However, Patron discloses:
the sensor fusion circuitry (paragraph [0511], “The sensory fusion circuitry 5908 may include a set of sensors (e.g., the sensors of the sensor system 102) and/or the sensory fusion algorithm 5910 (e.g., the sensor fusion algorithm 238). The sensory fusion circuitry 5908 may execute a command (e.g., the command 5912 of the sensory fusion algorithm 5910 and/or the projection command) using the processor 5904 and/or the memory 5906 (emphasis added).”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Patron into the combined teachings of Kantor, Salvo, and Srivastav to include “the sensor fusion circuitry.” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize sensor fusion circuitry that uses data from multiple sensors in order to effectively gain a more accurate and holistic/comprehensive view of a system/environment (Patron, paragraphs [0183 & 0485]).
As per Claim 19, the rejection of Claim 18 is incorporated; and Kantor discloses “the indication of the comparison (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”)” and “an abnormal operation condition (paragraph [0053], “If the comparison indicates that the value of the parameter is equal to or greater than the temperature threshold (or in some cases lower than the threshold), the switcher module may determine that the debug condition has been satisfied and that there is an occurring or impending problem within the storage system 100 (emphasis added).”; paragraph [0069], “The switcher module 210 monitors one or more conditions indicative of a problem or failure within the storage system 100 and automatically triggers the firmware switch when at least one of the one or more conditions are satisfied (emphasis added).”),” but the combination of Kantor, Salvo, and Patron does not explicitly disclose:
reduce a debug operation invasiveness if the indication of the comparison corresponds to an abnormal operation condition.
However, Srivastav discloses:
reduce a debug operation invasiveness if the indication of the comparison corresponds to [exceeding a threshold] (paragraph [0019], “In one embodiment, such determination is made by determining [comparing] whether the input data exceeds threshold values. If the adaptive trace logging module determines that an action should be taken, the adaptive trace logging module takes action to reduce an amount of computing resources consumed by trace logging operations. Such action may include, for example, changing the trace logging level of an executing software program so as to reduce the number of trace logging messages added to a trace log (emphasis added).”; paragraph [0071], “In one embodiment, the adaptive trace logging module makes a decision whether to take action based on comparing obtained input data to threshold values. For example, if the frequency or volume of trace logging messages generated by a particular software module exceeds a threshold, then the adaptive trace logging module may determine to take action to reduce the frequency or volume of trace logging messages generated by the particular software module.”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Srivastav into the combined teachings of Kantor, Salvo, and Patron to include “reduce a debug operation invasiveness if the indication of the comparison corresponds to an abnormal operation condition.” The modification would be obvious because one of ordinary skill in the art would be motivated to utilize a system of adaptive trace logging that takes action to reduce an amount of computing resources consumed by trace logging operations in order to help prevent significant performance degradation to executing software processes that compete with trace logging operations for scarce computing resources while at the same time capturing sufficient trace logging messages useful for troubleshooting problems (Srivastav, paragraphs [0009 & 0019]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kantor in view of Salvo, Patron, and Srivastav as applied to Claim 18 above, and further in view of Menon.
As per Claim 20, the rejection of Claim 18 is incorporated; and Kantor discloses “the provided indication of the comparison (paragraph [0036], “Another debug condition that the switcher module 210 may be configured to monitor may include a temperature debug condition. For example, condition module 260 of the condition detection module 245 may be configured for the temperature debug condition. Specifically, the condition module 260 may include or be associated with one or more temperature sensors that are configured to measure temperature of one or more components within the storage system 100. If the one or more temperature sensors determine an unusual rise of temperature that is not associated with ambient temperature, significant variations in temperatures, etc., based upon the measured temperature exceeding a temperature threshold associated with the temperature debug condition, the condition module 260 may determine that the temperature debug condition has been satisfied. Similar to the condition module 255, the condition module 260 may be configured to raise a flag or indicate via another mechanism that the temperature debug condition has been detected (emphasis added).”),” but the combination of Kantor, Salvo, Patron, and Srivastav does not explicitly disclose:
adjust an output bandwidth of trace debug data based at least in part on the provided indication of the comparison.
However, Menon discloses:
adjust an output bandwidth of trace debug data based at least in part on the [debug scenario] (paragraph [0024], “With such functional and debug architecture, power efficiency may be achieved, and output bandwidth may be modulated based on a given debug scenario (emphasis added).”; paragraph [0023], “Debug interconnect 130 may be dynamically controlled to perform both dynamic voltage and frequency scaling (DVFS) and dynamic bandwidth management system (DBMS) to effectively provide a given debug bandwidth depending on the debug scenario (emphasis added).”; paragraph [0025], “In an embodiment, DVFS may be performed in multiple steps or levels, in which one or more of voltage and frequency is increased one step at a time until bandwidth close to a desired bandwidth (e.g., target bandwidth) is achieved.”).
Menon is within the same field of endeavor as the claimed invention regarding debugging and adjusting bandwidth of data.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Menon into the combined teachings of Kantor, Salvo, Patron, and Srivastav to include “adjust an output bandwidth of trace debug data based at least in part on the provided indication of the comparison.” The modification would be obvious because one of ordinary skill in the art would be motivated to adjust bandwidth of data in order to effectively handle a functional workload and help avoid/prevent bottlenecks (Menon, paragraphs [0003 & 0014]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Feven H. Huruy whose telephone number is (571) 272-3826. The examiner can normally be reached Mon-Fri. 7:30am-3:45pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wei Mui can be reached at (571) 272-3708. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/F.H.H./Examiner, Art Unit 2191 /WEI Y MUI/Supervisory Patent Examiner, Art Unit 2191
Prosecution Insights