Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2ndNon-Final Office Action
DETAILED ACTION
Examiner’s Notes
(a) Claim date: 05/13/2026.
(b) Priority date: 12/22/2022.
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1-20, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of record “Subramaniam” < US 20160246911 A1>.(As to claim 1, 10, 16, Subramaniam discloses)
1. (Original) A method comprising:
"providing a placeholder for a component in a block of a first-level integrated circuit design without wiring at least one port of the component" [¶0019-0021: the RTL description 150 includes calls to a generic memory model (Gmem) for each memory instance M1-MK within blocks Block1 through BlockN of the IC design 100, wherein each generic memory call (Gmem.k) serves as a placeholder for a specific memory component using a generic memory call interface with memory parameters mpar1-mparM, without requiring instantiation of the specific memory component or its ports at the RTL description level];
"determining a mapping to a provider interface in the block" [¶0051: "the memory model generator 200 receives the memory parameters (i.e., mpar1-mparM) from the call to the generic memory model. It uses these parameters to select the appropriate model generators 215, 225, 235, 245," thereby determining a mapping from the generic memory call in the block to the appropriate specific memory model generator];
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and "invoking an integrated circuit generator to generate a second-level integrated circuit design based on the first-level integrated circuit design, the integrated circuit generator when executed replaces the provider interface with the component including wiring ports of the component, including the at least one port, in the second-level integrated circuit design according to the mapping" [¶0042-0044, ¶0057-0060, Fig. 2, Fig. 4: the memory model generator 200 is invoked to process the generic memory call in the RTL description 150 (first-level integrated circuit design) and generate specific memory models 217, 227, 237, 247 for each memory instance, thereby replacing the generic placeholder with a specific memory component in the downstream design representations including synthesis, netlist, and physical design outputs (second-level integrated circuit design), according to the mapping determined by the memory parameters].
(As to claim 2, 11, Subramaniam discloses)
(Original) The method of claim 1, further comprising:
"configuring an application program interface (API) that enables a provider to communicate with the integrated circuit generator, wherein the provider utilizes the API to instantiate the provider interface and determine the mapping" [¶0048: "if the called memory compiler uses a call interface that is different than the generic memory call interface, the generic memory model may also include a wrapper for the memory compiler so that the generic memory model can seamlessly interface with the external memory compiler," disclosing a configured interface that enables an external memory provider/compiler to communicate with the memory model generator 200 and supply the appropriate specific memory model, analogous to a provider utilizing an API to instantiate the provider interface and determine the mapping].
(As to claim 3, 12, 18, Subramaniam discloses)
(Original) The method of claim 1, further comprising:
"requesting, by the integrated circuit generator, the provider interface in the block" [¶0051: "the memory model generator 200 receives the memory parameters (i.e., mpar1-mparM) from the call to the generic memory model. It uses these parameters to select the appropriate model generators,"]; and
"providing, by a provider that communicates with the integrated circuit generator, the provider interface in the block" [Fig. 2, ¶0048: "The memory model generator 200 may call a separate memory compiler," disclosing that an external memory compiler (provider) communicates with the memory model generator 200 and provides the specific memory model (provider interface) in the block].
(As to claim 4, 19, Subramaniam discloses)
(Original) The method of claim 1, further comprising:
"receiving, by the integrated circuit generator, design parameters for the first-level integrated circuit design, wherein the design parameters specify the component" [¶0021, ¶0051: "the memory model generator 200 receives the memory parameters (i.e., mpar1-mparM) from the call to the generic memory model.].
(As to claim 5, Subramaniam discloses)
(Original) The method of claim 1, wherein:
"the first-level integrated circuit design corresponds to a language program used by the integrated circuit generator" [¶0020: "The RTL description is typically created using hardware description languages such as VHDL or Verilog,"]; and
"the second-level integrated circuit design corresponds to an intermediate representation (IR) data structure or a register-transfer level (RTL) data structure"
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[¶0045, ¶0050, Fig. 4: the specific memory simulation model 217 is a Verilog (.v) model, and "the memory models are written in synthesizable RTL description,"].
(As to claim 6, Subramaniam discloses)
(Original) The method of claim 1, wherein:
"the block is a level of a hierarchy" [¶0019, Fig. 1: the IC design 100 includes multiple hierarchical blocks Block1 through BlockN, with Block1 containing logic components L1-LJ and memory components M1-MK, disclosing that each block is a level of a hierarchy]; and
"the mapping to the provider interface is through multiple levels of the hierarchy" [¶0019, Fig. 1: the RTL description 150 includes hierarchical blocks Block1 through BlockN, wherein the generic memory call Gmem.k in Block1 is mapped through the block hierarchy to the memory model generator 200, disclosing that the mapping traverses multiple levels of the hierarchy].
(As to claim 7, Subramaniam discloses)
(Original) The method of claim 1, wherein:
"the component includes a first set of one or more ports and a second set of one or more ports, and the provider interface is instantiated in the block to provide access to the first set of one or more ports without wiring the second set of one or more ports" [¶0025, ¶0071: the generic memory call interface includes "a parameter defining a number of read/write ports in the memory" (first set of ports) and "Built-In-Self-Test logic or hooks to such test logic" (second set of ports), disclosing that the memory component includes at least two distinct sets of ports; further, ¶0021 and ¶0044 disclose that the generic memory call Gmem.k instantiates a generic memory interface in the block providing access to the read/write ports through the memory parameters, while the test/BIST ports are handled separately through distinct test model generators 235, disclosing that the generic interface provides access to one set of ports without requiring wiring of the other set at the RTL description level].
(As to claim 8, Subramaniam discloses)
(Original) The method of claim 1, wherein:
"the component is a static random access memory (SRAM) having read and write ports and a test port, and the provider interface is instantiated in the block to provide access to the read and write ports without wiring the test port" [¶0071: Subramaniam explicitly discloses SRAM as the memory component, with "a parameter defining a number of read/write ports in the memory" and "Built-In-Self-Test logic or hooks to such test logic"].
(As to claim 9, Subramaniam discloses)
(Original) The method of claim 1, wherein:
"the provider interface provides the placeholder for a generic component, and the integrated circuit generator when executed replaces the provider interface with a specific component" [¶0021, ¶0044, ¶0049: "Gmem is a call to a generic memory model because the call interface is generic enough to accommodate many different types of memory models," disclosing that the generic memory call interface provides the placeholder for a generic memory component].
(As to claim 13, Subramaniam discloses)
(Original) The apparatus of claim 10, wherein the processor is further configured to execute instructions stored in the memory to:
"receive, by the integrated circuit generator, design parameters that specify the component as corresponding to a particular technology process" [¶0047-0048, "different model generators can be used to model different technology nodes (i.e., geometry size, foundry and/or process variant)”].
(As to claim 14, Subramaniam discloses)
(Original) The apparatus of claim 10, wherein:
"the second-level integrated circuit design corresponds to a netlist or a physical design" [¶0057, Fig. 4: "the RTL description is synthesized to a gate-level netlist," and the final output of the design flow is a GDSII physical design description 450, disclosing that the second-level integrated circuit design corresponds to a netlist or a physical design].
(As to claim 15, Subramaniam discloses)
(Original) The apparatus of claim 10, wherein:
"the block is a register file implemented by a processor core that is implemented by an SoC, and the mapping to the provider interface is through processor core to the register file" [¶0005, ¶0019: "It is not uncommon for advanced system-on-chip (SoC) designs to include over a thousand memory instances,"].
(As to claim 17, Subramaniam discloses)
(Original) The non-transitory computer readable medium storing instructions of claim 16, the operations further comprising:
"configuring an application program interface (API) that encapsulates logic to enable a provider to communicate with the integrated circuit generator, wherein the integrated circuit generator utilizes the API to request the provider interface from the provider" [¶0048: "the generic memory model may also include a wrapper for the memory compiler so that the generic memory model can seamlessly interface with the external memory compiler," model generator 200, and wherein the memory model generator utilizes this interface to request the specific memory model from the provider, analogous to an API enabling a provider to communicate with the integrated circuit generator].
(As to claim 20, Subramaniam discloses)
(Original) The non-transitory computer readable medium storing instructions of claim 16, wherein:
"the component is a clock gate or a strap pin" [Fig. 4, usage of various components (clock gate, strap pin) are well-known in the art].
Conclusion
The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851
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