DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior art
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/08/2026 has been entered.
Applicant’s arguments filed on 12/18/2025 with respect to claims 1-8, 10, 13-15 and 17-24 have been fully considered but are moot in view of newly interpretation of the cited reference.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-8, 10, 13-15 and 17-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Tabor et al. (US pat. #9,280,508), hereinafter, “Tabor”, in view of Duran (US pub. # 2014/0250256), hereinafter, “Duran”
3. As per claims 1, 8 and 15, Tabor discloses a device
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, comprising: a first connector configured to receive a network signal (see figure above); an interface section coupled to the first connector (see figure above); a second connector coupled to the interface section and configured to connect to a first solid state storage device using a first interconnect signal (see figure above); a third connector coupled to the interface section and configured to connect to a second solid state storage device using a second interconnect signal (see figure above); and a compute resource in communication with and connected to the second connector, the third connector, and the interface section (see figure above), wherein the compute resource is configured to: use a first storage protocol (PCIe) to receive data using the network signal (see figure above); use a second storage protocol (SAS) to transfer data from the first connector to the first solid state storage device using the first interconnect signal (see figure above); and use the second storage protocol to transfer data from the first connector to the second solid state storage device using the second interconnect signal [see ‘internal SAS link’ inside host bus adaptor (interface section) to the SAS-PCIe bridge and ‘second interconnect signal’].
But fails to specifically disclose wherein the compute resource is configured to communicate with the first solid state storage device using a first data path and a second data path.
Duran discloses, wherein the compute resource is configured to communicate with the first solid state storage device using a first data path and a second data path (see fig. 2 and paragraph 0037, which discloses “in some implementations there will be exactly one SSD interface 320. In other implementations, there may be more than one SSD interfaces 320. In preferred embodiments the number of SSD interfaces is defined by the specific RAID configuration implemented”).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Duran’s teaching of a techniques for providing multiple interfaces in a solid-state based storage system employing OSD techniques, into Lee’s teaching of a method for enabling interoperability between a serial attached small computer system interface (SAS) protocol with a peripheral component interconnect express (PCIe) protocol, for the benefit of providing multiple interfaces in a solid-state device (SSD) storage system within a freestanding storage cabinet, or in a desk side chassis, or in an industry-standard drawer-type form factor.
4. As per claim 2, the combination of Tabor and Duran discloses “The device of claim 1” [See rejection to claim 1 above], wherein the compute resource is configured to perform a translation between the first storage protocol and the second storage protocol (see figure above).
5. As per claims 3, 10 and 17, Tabor discloses wherein the interface section is configured to emulate, using the first solid state storage device, a behavior of the first storage protocol (see abstract of Tabor, which discloses “a SAS-PCIe bridge includes a SAS component configured to communicate with a SAS device in a SAS domain and a PCIe component configured to communicate with a PCIe switch in a PCIe domain. The SAS component and the PCIe component are configured to convert data between the SAS protocol and the PCIe protocol”).
6. As per claims 4 and 18, Tabor discloses wherein the interface section is configured to emulate, using the first storage protocol, a behavior of the first solid state storage device (see figure above and abstract of Tabor).
7. As per claims 5 and 19, Tabor discloses wherein the interface section is configured to operate, as a virtual device, the first solid state storage device and the second solid state storage device (see col. 5, line 66).
8. As per claims 6, 13 and 20, Tabor discloses, wherein the first storage protocol comprises a nonvolatile memory protocol (see col. 4, line 57).
9. As per claims 7 and 14, Tabor discloses wherein the device has a drive bay form factor (see figure above).
10. Claims 21-24 are rejected under 35 U.S.C. 103(a) as being unpatentable over Tabor et al. (US pat. #9,280,508), hereinafter, “Tabor”, in view of Duran (US pub. # 2014/0250256), hereinafter, “Duran” and further in view of Strasser et al. (US pub. # 2013/0019072), hereinafter, “Strasser”.
11. As per claim 21, the combination of Tabor and Duran discloses “The device of claim 1” [See rejection to claim 1 above], but fails to specifically disclose wherein the compute resource is configured to aggregate management information.
Strasser discloses wherein the compute resource is configured to aggregate management information (see fig. 4 and paragraph 0129, which discloses “for example, data from a portion of a first data packet may be combined with data from a portion of a second data packet”).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Strasser’s teaching of an adaptive logical storage element comprises a plurality of solid-state storage elements accessible in parallel, into Duran’s teaching of a techniques for providing multiple interfaces in a solid-state based storage system employing OSD techniques, and Lee’s teaching of a method for enabling interoperability between a serial attached small computer system interface (SAS) protocol with a peripheral component interconnect express (PCIe) protocol, for the benefit of providing parallel access to multiple interfaces in a solid-state device (SSD) storage system within a freestanding storage cabinet, or in a desk side chassis, or in an industry-standard drawer-type form factor.
12. As per claim 22, the combination of Strasser, Tabor and Duran discloses “The device of claim 21” [See rejection to claim 21 above], further comprising a fourth connector configured to transfer the management information using a management protocol (see paragraph 0070 of Strasser).
13. As per claim 23, the combination of Strasser, Tabor and Duran discloses “The device of claim 21” [See rejection to claim 21 above], wherein the compute resource is configured to transfer the management information using in-band communications (see paragraph 0073 of Strasser).
14. As per claim 24, the combination of Strasser, Tabor and Duran discloses “The device of claim 21” [See rejection to claim 21 above], wherein the compute resource is configured to transfer the management information using out-of-band communications (see paragraph 0073 of Strasser).
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-8, 10, 13-15 and 17-24 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov.
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/Ernest Unelus/
Primary Examiner
Art Unit 2181