Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
2. Applicant’s arguments with respect to claim(s) 1-23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 7, 10, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Cioffi et al. (US 20210099277 A1) in view of Isson (US 8699591 B2).
Cioffi et al. discloses a wireless and wireline architecture comprising the following: regarding claim 1, An intermediate node comprising: a first interface coupled to a baseband unit BBU, the first interface receives a cellular signal (see [0034] “Embodiments of the invention include infrastructure that uses the existing wires to carry (at low carrier frequency) the wireless baseband signals through base-station-located intermediate-frequency (IF) modulator/demodulator converters. These up/down-convert the baseband unit's (BBU) signals to the appropriate carrier frequency for transmission through the wireline link”);
downlink intermediate node multi-stream processing logic coupled to the xIFFT core, the downlink intermediate node multi-stream processing logic multiplexes the at least one stream in the time domain into at least one multi-stream signal (see [0116], “5G-DSL may still need to buffer (and frequency scale) downlink and uplink signals to multiplex into down/up time slots, just two such identical buffers occur in parallel, one for each wireline link in various embodiments of the invention”; see [0120], “In FIG. 9A’s m-way system 900, there is no crosstalk between the wireline channels in the different time bursts, say for instance with an LTE system using two 20-MHz-wide spatial streams (m_LTE=16 for the original m definition on each LTE spatial stream, but the wireline link has m_5G-DSL=2 channels time multiplexed with a single IF carrier at 18.4 MHz), which then ultimately occupy the same wireless frequency band (use the same RF carrier) between the 5G-RF and the user device(s), and thus also on the wireless link. The 5G-RF uses the same carrier to modulate separately each of the two spatial streams, one for each of the antennas.”);
and a digital-to-analog converter coupled to receive the at least one multi-stream signal, the digital-to-analog converter converts the at least one multi-stream signal into an at least one analog multi-stream signal that is transmitted on a wireline segment within a wireline-wireless architecture (see [0058], “When the downlink is active, the output non-zero real samples will be regularly spaced at 3.84m MHz and will be converted at that continuing rate into analog by the DAC 420 before (continuous-time) modulation to the selected channel carrier frequency of f_c,down=f_LTE,down−f_IF. This operation removes the downlink wireline link’s frequency scaling prior to wireless transmission downlink”).
Cioffi et al. discloses the claimed limitations of converting celluar stream to the stream in a time domain (see [0049] “One simple way that a 5G-IF might interpolate repeats LTE's pre-DFT baseband LTE signal in frequency, zeroes the upper image, and then translates the remaining signal up by ½ the size of the FFT, although this may require a DFT to time domain to occur in the interpolation box before taking the real part at the new doubled sampling rate”; see [0047] “These digital time-domain (two-dimensional or complex) samples will recycle in time index…” ). However, Cioffi et al. does not disclose an xIFFT core coupled to receive at least one cellular stream corresponding to the cellular signal, the xIFFT converts the at least one cellular stream to a set of at least one stream in a time domain (emphasis added).
Isson discloses a communication system comprising: an xIFFT core (Fig. 1, IFFT) coupled to receive at least one cellular stream (Fig. 1, X1, Xk, Xn) corresponding to the cellular signal, the xIFFT converts the at least one cellular stream to a set of at least one stream in a time domain (see paragraph 13 “The IFFT then transforms the signal of the frequency domain to the time domain”).
It would have been obvious to one ordinary skilled in the art before the effective filing date of the claimed invention to modify the invention of Cioffi et al., by using the features as taught by Isson, in order to to enable efficient conversion of cellular streams from the frequency domain to the time domain.
Regarding claim 7, Cioffi et al. discloses wherein the downlink intermediate node multi-stream processing logic comprises a single multiplexing path (Fig. 3 depicts a single multiplexing path to customer premises; see claim 1, “A radio access node comprising, a wireless interface … a demodulator … an interpolator …a frequency-scaling buffer … a digital-to-analog …and a wireline interface that transmits the analog frequency-scaled time-duplexed signal on a wireline link” ).
Regarding claim 10, Cioffi et al. discloses wherein the downlink intermediate node multi-stream processing comprises a plurality of multiplexing paths (See [0007], “The application of this wireless and wireline architecture is particularly relevant to LTE, 5G and Wi-Fi deployments. LTE's advance through 4G releases and to 5G releases has leveraged well the multicarrier modulation methods deployed in earlier DSL networks, including also LTE's Multiple-Input-Multiple Output (hereinafter, “MIMO”) and Multi-User MIMO (hereinafter, “MU-MIMO”) that are similar to DSL's vectoring methods, particularly for large numbers of antennas”; see [0023] “FIG. 9B illustrates a full MIMO implementation of a cellular and wireline architecture with RF+ that allows for intermediate steering according to various embodiments of the invention”).
Regarding claim 11, Cioffi et al. discloses wherein each of the plurality of multiplexing paths interleaves the set of at least one stream in the time domain with the at least a portion of the control signal (see [0053], “Another pilot-frequency choice could be 384 kHz (although this may be less ideal on some heavily distorted transmission links) and consequently place both up and down control channels below this alternative pilot (perhaps moving the down control from 180 kHz to 300 kHz). Both LTE and fast modes also easily allow asymmetry to be proportionately introduced without concern for spectrum planning. This buffering accommodates any asymmetry from 12:0 (broadcast LTE) to 0:12 (all upstream); for instance, 8 symbols downlink for every 4 uplink would provide a 2:1 asymmetry ratio in the format, while 9 symbols downlink for every 3 uplink would be 3:1 asymmetry and 10/2 would allow 5:1 asymmetry”; see [0116] “5G-DSL may still need to buffer (and frequency scale) downlink and uplink signals to multiplex into down/up time slots”).
5. Claims 2, 3, 4, 5, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Cioffi et al. (US 20210099277 A1) in view of Isson (US 8699591 B2) as applied to claim 1 above, and further in view of Ahmed et al. (US 20210135722 A1).
Cioffi et al. and Isson disclose the claimed limitations above. Cioffi et al. and Isson do not disclose the following features: regarding claim 2, further comprising an ORAN IP core coupled to the xIFFT core, the ORAN IP core provides interoperability between the intermediate node and the BBU; regarding claim 3, further comprising a control signal generator coupled to the ORAN IP core and the xIFFT core, the control signal generator receives at least one of a first control information from the xIFFT core and a second control information from the ORAN IP core, the control signal generator generates a control signal based at least partially on the at least one of the first and second control information.
Ahmed et al. discloses a method of enabling an Open RAN-compatible radio unit (O-RU) to apply different beamforming weights to different physical resource blocks (PRBs) comprising: regarding claim 2, further comprising an ORAN IP core coupled to the xIFFT core, the ORAN IP core provides interoperability between the intermediate node and the BBU (see [0005], “One of the splits recently standardized by O-RAN Alliance is split option 7-2x (Intra-Physical (PHY) layer split). In the uplink (UL), Fast Fourier Transform (FFT), Cyclic Prefix (CP) removal, and possibly pre-filtering functions reside in the RU, while the rest of PHY functions reside in the DU. In the downlink (DL), inverse Fast Fourier Transform (iFFT), CP addition, and beamforming functions reside in the RU, the rest of PHY functions reside in the DU. This split has multiple advantages such as simplicity, transport bandwidth scalability, beamforming support, interoperability, support for advanced receivers and inter-cell coordination, lower O-RU complexity, future proof-ness, interface and functions symmetry.”; see [0125] “FIG. 5 illustrates an example 0-RAN system architecture, in which the upper physical layer (U-PHY) blocks such as the scrambling, modulation, layer mapping, RE mapping, and I/Q compression (as well as optional precoding, which may be bypassed in bypass mode) can be implemented in the O-DU. The I/Q decompression, precoding, digital beamforming, IFFT, CP addition, digital-to-analog conversion, and optionally analog beamforming can be implemented in the O-RU. O-RAN fronthaul (FH) is shown between 0-DU and O-RU”);
regarding claim 3, Ahmed et al. further comprising a control signal generator coupled to the ORAN IP core and the xIFFT core, the control signal generator receives at least one of a first control information from the xIFFT core and a second control information from the ORAN IP core, the control signal generator generates a control signal based at least partially on the at least one of the first and second control information (see [0010] “There are four planes specified in the O-RAN specs namely user-plane (U-plane), control plane (C-plane), synchronization plane (S-plane), and management plane (M-plane). The main focus of this invention is the C-plane messages”; see [0011] “The main purpose of the C-plane messages is to transmit data-associated control information required for processing of user data (e.g., scheduling and beamforming commands). These messages are sent separately for DL related commands and UL related commands”; see [0041] “Beamforming via sending real-time weights: [0042] In this method, the O-DU generates complex weights that create the beam and send these weights to the O-RU via the fronthaul interface. To be able to do so, the O-DU needs to know the specific antenna characteristics of the O-RU including how many antenna elements are present in the vertical and horizontal directions and the antenna element spacing, among other properties”).
It would have been obvious to one ordinary skilled in the art before the effective filing date of the claimed invention to modify the invention of Cioffi et al., and Isson by using the features as taught by Ahmed et al., in order to provide standardized interoperability and enhanced control signaling between the intermediate node and the BBU.
Cioffi et al. (US 20210099277 A1) further discloses: regarding claim 4, comprising at least one buffer coupled to the xIFFT core, the at least one buffer receives and stores the set of at least one stream in the time domain received from the xIFFT core (see claim 1, “a frequency-scaling buffer coupled to receive the interpolated signal, the buffer stores a plurality of sampled symbols within the interpolated signal and subsequently bursts the stored plurality of sampled symbols across a plurality of time slots to generate a frequency-scaled time-duplexed signal used for wireline communication”; See [0050] “As shown in FIG. 3, a buffer 330 time-duplexes downlink and uplink signals into the single wireline link. Each baseband slot contains a certain number of symbols (e.g., for LTE, 6 successive symbols or 960m samples (in 500 μs) that corresponds to a 2-kHz clock”).
Cioffi et al. (US 20210099277 A1) further discloses: regarding claim 5, wherein the downlink intermediate node multi-streaming processing logic comprises a multiplexer coupled to receive the set of at least one stream in the time domain and the control signal, the multiplexer generates a multi-stream signal comprising the set of at least one stream in the time domain and at least a portion of the control signal (see [0053], “Another pilot-frequency choice could be 384 kHz (although this may be less ideal on some heavily distorted transmission links) and consequently place both up and down control channels below this alternative pilot (perhaps moving the down control from 180 kHz to 300 kHz). Both LTE and fast modes also easily allow asymmetry to be proportionately introduced without concern for spectrum planning. This buffering accommodates any asymmetry from 12:0 (broadcast LTE) to 0:12 (all upstream); for instance, 8 symbols downlink for every 4 uplink would provide a 2:1 asymmetry ratio in the format, while 9 symbols downlink for every 3 uplink would be 3:1 asymmetry and 10/2 would allow 5:1 asymmetry”; see [0116] “5G-DSL may still need to buffer (and frequency scale) downlink and uplink signals to multiplex into down/up time slots”).
Cioffi et al. (US 20210099277 A1) further discloses: regarding claim 6, wherein the downlink intermediate node multi-stream processing logic further comprises one or more of upsample logic (see [0161] “At a step 1230, an interpolated signal is generated by interpolating the analytic signal at a second sampling rate. The second sampling rate is faster (or higher) than the first sampling rate. In particular, the second sample rate may be twice the first sampling rate”), a low-pass filter, an IF mixer up-converter, and a real-part extractor.
6. Claim 8, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Cioffi et al. (US 20210099277 A1) in view of Isson (US 8699591 B2) as applied to claims 1, 7 above, and further in view of Lin et al. (US 20130077603 A1).
Cioffi et al. and Isson disclose the claimed limitations above. Cioffi et al. and Isson do not disclose the following features: regarding claim 8, wherein the single multiplexing path interleaves the set of at least one stream in the time domain and the at least a portion of the control signal on a data block-by-data block basis; regarding claim 9, wherein the single multiplexing path interleaves the set of at least one stream in the time domain and the at least a portion of the control signal on a multi-data-block-by-multi-data-block bases, the multi-block having a block length greater than one.
Lin et al. (US 20130077603 A1) discloses a communication system comprising: regarding claim 8, wherein the single multiplexing path interleaves the set of at least one stream in the time domain and the at least a portion of the control signal on a data block-by-data block basis (see [0024] “the invention provides a method for IQ data mapping, comprising: mapping IQ data of one or more standards to a CPRI radio frame, wherein, the CPRI radio frame comprises multiple multi-frames, and boundaries of the multi-frames are aligned with a header of the CPRI radio frame; each multi-frame comprises K basic frames, and each basic frame comprises a plurality of IQ sub-containers; one IQ sub-container constitutes one time slot”; see [0007] The data link layer provides that the period for each basic frame is 1/3.84 M (about 260.42 ns), which is composed of 1 control word plus an IQ area of 15 words);
regarding claim 9, wherein the single multiplexing path interleaves the set of at least one stream in the time domain and the at least a portion of the control signal on a multi-data-block-by-multi-data-block bases, the multi-block having a block length greater than one (see [0024] “the invention provides a method for IQ data mapping, comprising: mapping IQ data of one or more standards to a CPRI radio frame, wherein, the CPRI radio frame comprises multiple multi-frames, and boundaries of the multi-frames are aligned with a header of the CPRI radio frame; each multi-frame comprises K basic frames, and each basic frame comprises a plurality of IQ sub-containers; one IQ sub-container constitutes one time slot”; see [0007] “The data link layer provides that the period for each basic frame is 1/3.84 M (about 260.42 ns), which is composed of 1 control word plus an IQ area of 15 words”; see Fig. 5 depicts W (numbers of words included in one basic frame) is 15 bytes, which is greater than one).
It would have been obvious to one ordinary skilled in the art before the effective filing date of the claimed invention to modify the invention of Cioffi et al. and Isson by using features, as taught by Lin et al., in order to improve data organization and transmission flexibility.
7. Claims 12, 14-23 are rejected under 35 U.S.C. 103 as being unpatentable over LIVA et al. (US 20100031305 A1) in view of Niu et al. (US 20160183248 A1).
LIVA et al. discloses an enhanced Cable Modem Termination System comprising: regarding claim 12, a intermediate node (see [0005] “In traditional Hybrid Fiber-Coax (HFC) systems for Cable Television systems, Fiber Nodes (FN) are intermediate sub-systems in an overall information distribution network hierarchy”) comprising:
a first interface coupled to a wireline segment, the first interface receives a multi-stream signal from the wireline segment (see [0052] “The analog return spectrum (5-42 MHz) is digitized and selected upstream DOCSIS channels are demodulated and the data extracted”; [0056] “Over the coaxial RF interface, the mini-CMTS supports DOCSIS MAC/PHY services over a number of upstream and downstream channels. The 5-42 MHz upstream spectrum from the legacy analog distribution generally includes both DOCSIS channels and legacy channels. This upstream is isolated by appropriate filtering and provided to one or more digitization paths”);
an analog-to-digital converter coupled to receive the multi-stream signal, the analog-to-digital converter converts to the multi-stream signal to a first digital multi-stream signal (see [0018] “The digital demodulator section of the enhanced CMTS digitizes the entire return spectrum on each of multiple upstream inputs, each of which may include multiple upstream channels with no particular interrelationship”; [0055] “The mini-CMTS 9000 is made up of D/As 9020, A/Ds 9010, DSP Multi-Channel Transceiver ASIC 3B, and the MAC Processor and Shared Memory”; [0083] “one of the provided A/Ds (see reference 9010 in FIG. 3A) digitizes the entire return spectrum in the Nyquist space”; [0084] “Once digitized, the desired legacy signal needs to be converted to baseband, isolated from other upstream signals, and decimated. FIGS. 4C through 4E illustrate these functions conceptually. FIG. 4C represents a band-pass (channel isolation) operation performed in the digital domain at the provisioned frequency and bandwidth, as directed by the MAC control functions. As illustrated in FIG. 4D, the signal is then resampled, converted to baseband, and decimated by a multistage decimation process”);
an uplink intermediate node multi-stream processing logic coupled to the analog-to-digital converter, the uplink intermediate node multi-stream processing logic demultiplexes the digital multi-stream signal to at least one of one stream and control information within the time domain (see [0061], “Front-end 6000 includes separate front-ends 6005 for each channel. Separate digitized signal outputs are provided for each channel”; See Fig. 5 and 6 digitized return channel data includes control signal CTRL, and DATA );
LIVA et al. discloses the features in paragraphs [0072], “Each QPSK or QAM burst modulated channel signal is then demodulated within a respective DOCSIS demodulator and Return DSP block 16 in order to extract the data transmitted within the burst”; [0101]: “fully digital upstream implementation of DOCSIS modulated upstream channels, including direct IF sampling, digital baseband conversion, and parallel demodulation of at least 2 channels”. Thus, LIVA et al. inherently involves FFT-based processing to convert time-domain channel samples to frequency-domain symbols for data extraction. However, LIVA et al. does not explicitly disclose a dedicated xFFT core as the following claimed limitation: regarding claim 1, an xFFT core coupled to receive the at least one of one stream and the control information within the time domain, the xFFT converts the at least one of one stream and control information within the time domain to at least one of one stream and control information within the frequency domain for subsequent transmission to a baseband unit BBU; regarding claim 18, wherein the xFFT core is coupled to receive the at least one of the first and second streams, the xFFT core converts the at least one of the first and second streams to the frequency domain.
Niu et al. disclose a communication system comprising: regarding claim 1, an xFFT core coupled to receive the at least one of one stream and the control information within the time domain, the xFFT converts the at least one of one stream and control information within the time domain to at least one of one stream and control information within the frequency domain for subsequent transmission to a baseband unit BBU (see Abstract, “In an uplink communication using the same baseband unit, a corresponding fast Fourier transform and a remove cyclic prefix operation are performed at a remote radio unit. This generates different levels of traffic on a physical communication link between the baseband unit and the remote radio unit for uplink and downlink communications with similar characteristics”; paragraph [0020], “FFT 174 of RRU 130 to transmit power control and feedback information detection 172 of BBU 110 in the uplink systems”); regarding claim 18, wherein the xFFT core is coupled to receive the at least one of the first and second streams, the xFFT core converts the at least one of the first and second streams to the frequency domain (see Claim 1 on page 8, “receive an uplink communication via an air interface from a user equipment (UE); convert the uplink communication from an uplink time domain signal to an uplink frequency domain signal; communicate the uplink frequency domain signal to a baseband unit (BBU) via a physical communication link”).
It would have been obvious to one ordinary skilled in the art before the effective filing date of the claimed invention to modify the invention of LIVA et al., by using the features, as taught by Niu et al., in order to enable efficient conversion of time-domain streams and control information to the frequency domain for transmission to a baseband unit.
LIVA et al. further discloses: regarding claim 14, at least one buffer (see [0095], “As shown in FIG. 3C, a 4 MB SDRAM is attached as local RAM, between 16 and 64 MB of SDRAM is attached to the multi-master 60.times. bus as shared RAM, and between 8 and 32 MB of Flash memory is coupled (via buffers) to the multi-master 60.times. bus, as shared NV Memory. The 4 MB SDRAM operates at 66 MHz, is 32-bits wide, and is intended for use exclusively by the CPM to buffer descriptors for the communication channels or raw data that is transmitted between channels”) and control processing logic (see [0062], “The DOCSIS Demodulator and Return DSP logic 16 provides the MAC layer with channel profile information, including timing, power, and frequency estimation data”) coupled to the uplink intermediate node multi-stream processing logic.
LIVA et al. further discloses: regarding claim 15, wherein the uplink intermediate node multi-stream processing logic comprises a single demultiplexing path (see [0048] “the mini-CMTS 9000 of each eFN incorporates two downstream (DS) and four upstream (US) channels. These four available selectable US channels are provided by a single physical digitized input”).
LIVA et al. further discloses: regarding claim 16, wherein the uplink intermediate node multi-stream processing logic comprising a demultiplexer coupled to receive the digital multi-stream signal, the demultiplexer generates at least one of a first stream, a second stream and control information from the digital multi-stream signal (See [0061], “Front-end 6000 includes separate front-ends 6005 for each channel. Separate digitized signal outputs are provided for each channel; collectively these outputs comprise signals 1900”; [0072] “Each QPSK or QAM burst modulated channel signal is then demodulated within a respective DOCSIS demodulator and Return DSP block 16 in order to extract the data transmitted within the burst”; the extracted control information is described in [0074]-[0082]).
LIVA et al. further discloses: regarding claim 17, wherein the plurality of buffers receives and stores the at least one of the first and second streams ([0059], “The transmitter and receiver are shown coupled to the bus controller via interconnect and buffering 9080”).
LIVA et al. further discloses: regarding claim 19, wherein the uplink intermediate node multi-stream processing logic comprises a plurality of demultiplexing paths ([0049] “the mini-CMTS 9000 of each eFN incorporates four downstream (DS) and sixteen upstream (US) channels. Four available selectable US channels for each of four physical digitized inputs provide the sixteen US channels”).
LIVA et al. further discloses: regarding claim 20, wherein the plurality of demultiplexing paths receives the digital multi-stream signal from the analog-to-digital converter, each of the plurality of demultiplexing paths generates at least one stream from the digital multi-stream signal ([0061], “At least one digitized return signal is provided to front-end 6000. In a preferred embodiment, each of a plurality of provided digitized return signals, corresponding to respective external A/Ds and associated analog input circuits, is selectively coupled to one or more of the individual front-ends 6005”).
LIVA et al. further discloses: regarding claim 21, wherein the at least one stream comprises control information ([0085], “Legacy Digitizing Framer and Return DSP 15 facilitates the framing process, including the identification of each frame by eFN-ID, channel-ID and Payload control (using Source Address, SA, and Destination Address, DA”).
LIVA et al. further discloses: regarding claim 22, wherein the multi-stream signal comprises at least one of one stream and control information ([0056], “the mini-CMTS supports DOCSIS MAC/PHY services over a number of upstream and downstream channels. The 5-42 MHz upstream spectrum from the legacy analog distribution generally includes both DOCSIS channels and legacy channels”; [0087], “MAC layer functions beyond those required by DOCSIS are also provided to support at least two Legacy channels, with respective MIBs and Messages”).
LIVA et al. further discloses: regarding claim 23, wherein the control processing logic receives the control information and generates a control signal ([0062], “The DOCSIS Demodulator and Return DSP logic 16 provides the MAC layer with channel profile information, including timing, power, and frequency estimation data”; [0070], “The receiver extracts the data packets transmitted by the Cable Modems (CMs) and sends them to the MAC layer ….. Each upstream receiver channel is provisioned appropriately for each of these parameters via the management and control functions of the MAC layer. In addition, the upstream receiver integrates channel performance and monitoring function that feeds the MAC layer with all the necessary information for ranging purposes and for channel capacity optimization”).
8. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over LIVA et al. (US 20100031305 A1) in view of Niu et al. (US 20160183248 A1) as applied to claim 12 above, and further in view of Ahmed et al. (US 20220021423 A1).
LIVA et al. (US 20100031305 A1) in view of Niu et al. (US 20160183248 A1) disclose the claimed limitations above. LIVA et al. (US 20100031305 A1) in view of Niu et al. (US 20160183248 A1) do not disclose: an ORAN IP core coupled to the xFFT core, the ORAN IP core provides interoperability between the intermediate node and the BBU.
Ahmed et al. (US 20220021423 A1) discloses a communication system comprising: an ORAN IP core coupled to the xFFT core, the ORAN IP core provides interoperability between the intermediate node and the BBU ([0005], “One of the splits recently standardized by O-RAN Alliance is split option 7-2× (Intra-Physical (PHY) layer split). In the uplink (UL), Fast Fourier Transform (FFT), Cyclic Prefix (CP) removal, and possibly pre-filtering functions reside in the RU, while the rest of PHY functions reside in the DU. In the downlink (DL), inverse Fast Fourier Transform (iFFT), CP addition, and beamforming functions reside in the RU, the rest of PHY functions reside in the DU. This split has multiple advantages such as simplicity, transport bandwidth scalability, beamforming support, interoperability, support for advanced receivers and inter-cell coordination, lower O-RU complexity, future proof-ness, interface and functions symmetry”).
It would have been obvious to one ordinary skilled in the art before the effective filing date of the claimed invention to modify the invention of LIVA et al. and Niu et al., by using the features as taught by Ahmed et al., in order to provide standardized interoperability and enhanced control signaling between the intermediate node and the BBU.
Conclusion
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/KWANG B YAO/Supervisory Patent Examiner, Art Unit 2473
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