Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicants’ election without traverse of Species D, Fig. 9-11 of claims 10-19 in the reply filed on December 17, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AlA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 10-19 are rejected under 35 U.S.C. 102 as being unpatentable in view of 前川 慎志 et al. (JP 5688448 B2).
Regarding Claim 10, 前川 慎志 et al. discloses a semiconductor package comprising:
A film (base insulating film 110);
A wiring pattern layer (source wiring 104, drain wiring 105) disposed on the film, wherein the wiring pattern layer includes a first area (104), a second area (105) spaced apart from the first area, and a third area (wiring pattern 517) surrounding the first and second area;
A first semiconductor chip (810) disposed on the first area of the wiring pattern layer and electrically connected to the wiring pattern layer;
A second semiconductor chip disposed on the second area of the wiring pattern layer and electrically connected to the wiring pattern layer; a first insulating layer (insulating film 11, insulating film 107) disposed on the third area of the wiring pattern layer; a first metal layer (112, silver or aluminum) disposed on the first insulating layer and spaced apart from the first semiconductor chip and the second semiconductor chip; and a heat dissipating layer covering the first semiconductor chip and the second semiconductor chip and made of a synthetic resin (“resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin.”)
Regarding Claim 11, 前川 慎志 et al. discloses a semiconductor package further comprising a second metal layer (metal mask) disposed on a bottom surface of the film (Fig. 8).
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Regarding Claim 12, 前川 慎志 et al. discloses a semiconductor package wherein the first metal layer includes one of copper and aluminum (“A conductive film pattern 503 is formed by selectively discharging a composition containing u (gold), Cu (copper), W (tungsten), Al (aluminum), or the like.”) wherein the heat dissipating layer includes one of epoxy resin and a silicon compound (“Further, as another material of the interlayer insulating film 513, an organic resin (resin material such as an epoxy resin, an acrylic resin, a phenol resin, a novolac resin, a melamine resin, or a urethane resin) whose surface is planarized using a coating method is used. May be. Further, as another material of the interlayer insulating film 513, a SiOx film containing an alkyl group using a siloxane polymer may be used.”). 前川
Regarding Claim 13, 前川 慎志 et al. discloses a semiconductor package wherein the first semiconductor chip includes a gate driver integrated circuit (driver 411) wherein the second semiconductor chip includes a data driver integrated circuit (driver 41).
Regarding Claim 14, 前川 慎志 et al. discloses a semiconductor package comprising a lower wiring pattern layer (505) disposed on a bottom surface of the film and connected to the wiring pattern layer (Fig. 6).
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Regarding Claim 15, 前川 慎志 et al. discloses a semiconductor package comprising a second insulating layer (107) disposed between the first semiconductor chip and the first area of the wiring pattern layer, and between the second semiconductor chip and the second area of the wiring pattern layer.
Regarding Claim 16, 前川 慎志 et al. discloses a semiconductor package wherein the wiring pattern layer has a first opening which overlaps the first semiconductor chip, wherein the wiring pattern layer has a second opening, and the second opening overlaps the second semiconductor chip, and wherein each of the first opening and the second opening is filled with the second semiconductor layer.
Regarding Claim 17, 前川 慎志 et al. discloses a semiconductor package further comprising:
A first electrode bump (102) disposed in the second insulating layer electrically connecting the first semiconductor chip and wiring pattern layer to each other;
A second electrode bump (112) disposed in the second insulating layer and electrically connecting the second semiconductor chip and wiring pattern to each other.
Regarding Claim 18, 前川 慎志 et al. discloses a semiconductor package wherein the heat dissipating layer (interlayer insulating film 811, barrier film 812) is in contact with a display panel.
Regarding Claim 19, 前川 慎志 et al. discloses a semiconductor package wherein the heat dissipating layer (interlayer insulating film 811, barrier film 812) covers a portion of the first metal layer.
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Conclusion
Any inquiry concerning this communication should be directed to JOSHUA SCOTT WYATT at telephone number (703)756-1937.
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/JOSHUA SCOTT WYATT/Examiner, Art Unit 2815
/JAY C KIM/Primary Examiner, Art Unit 2815