DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
The Amendment filled 11/12/2025 in response to Non-Final Office Action mailed 08/12/2025 has been entered. Claims 1, 2, 5, 13-14, and 16 are amended. Claim 2 is placed in independent form. Claims 12 and 15 are canceled. Claims 21-23 are newly added. No new matter has been introduced.
Claims 1-11, 13-14, and 16-23 are currently pending.
Response to Objections
In view of the foregoing amendments, the objections to claims 5 and 12 are withdrawn.
Response to 35 USC § 112(b) Rejections
In view of the foregoing amendments, the 112(b) rejections with respect to claim 16 is withdrawn.
Response to Arguments/Remarks
Applicant's arguments filed 11/12/2025 have been fully considered but they are not persuasive. Applicant asserts (Remarks, p 9) that paragraph [0069] Sandkuijl does not disclose sequentially mechanically positioning of the laser across coarse locations (i.e., moving across different coarse and moving after an image is taken at each coarse location). In (¶[0069]), a focal map disclosed which provides positional adjustments for the laser. The focal map provides optimum focal positions and is represented as a smooth (i.e., continuous) surface, exhibited in FIG 11, as a result of interpolation (“further comprises interpolating between the optimum focal position at each of the positions in the plane of the sample to produce a surface representation of the sample”; ¶[0178]), across which the laser may be “alternatively, continuously scanned”. However, this continuous surface focal map representation does not correspond to the image acquisition. Sandkuijl discloses in the preceding section titled “Arrangement of components” (¶¶[0135]-[0149]), that the stage itself may move continuously (i.e., across positions provided by the focal map), yet, the images are acquired at specific positions (see ¶[0148], shown below). Sandkuijl additionally discloses “by scanning the sample through a range of positions, in a relatively coarse manner with large distances between the positions” (¶[0155]). Put another way, the images are acquired at discrete locations although, the sample may be continuously moved. Image acquisition at specific positions across a continuously translated sample as taught by Sandkuijl specifically describes sequential image capture.
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Examiner respectfully disagrees with applicant’s assertion. Accordingly, Sandkuijl is found to meet the limitation of sequential image acquisition as claimed, and the rejection is maintained.
Applicant asserts (Remarks, p 10-11) that Sandkuijl (¶[0069]) and (¶[0155]) do not disclose "acquiring an image tile by steering the focal point of the focused optical beam to fine locations of a set of fine locations on or in the IC under test." However, Sandkuijl teaches a method for autofocusing which utilizes a focal map to assist with for repositioning a sample to obtain the position with highest focus score (¶[0155]), described as a refinement step. The refinement step is expressly for the purpose of picking the best position in comparison to the prior coarse step. See excerpt of (¶[0155]), shown below.
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Sandkuijl additionally discloses in (¶[0166]) a first coarse estimate of the focal position followed by refined positions. The purpose of the refined position (i.e., fine location) is to “bring the sample close to the focal plane”, or in other words, move the location of the sample to improve the focus over the previous “coarse focus position”.
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Examiner respectfully disagrees with applicant. Accordingly, Sandkuijl is found to meet the limitation of scanning at coarse and fine positions and the rejection is maintained.
Information Disclosure Statement
No Information Disclosure Statement (IDS) was filed; therefore, no applicant-submitted references were considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-9, 13, 15, 16, 18, and 21-23, are rejected under 35 U.S.C. 103 as being unpatentable over Simon et al. (Simon, J., et al., "Two-Photon Optical Beam Induced Current for Circuit Level Verification and Validation of a 130 nm Microelectronic Device," 2021 IEEE Physical Assurance and Inspection of Electronics (PAINE), Washington, DC, USA, 2021, pp. 1-7), hereinafter “Simon”, in view of Sandkuijl.
Regarding claim 1, Simon teaches an integrated circuit (IC) validation method comprising:
{sequentially mechanically positioning a focal point of a focused optical beam at coarse locations of a set of coarse locations in or on an IC under test;
with the focal point of the focused optical beam positioned at each coarse location},
acquiring an image tile of the IC under test {by steering the focal point of the focused optical beam to fine locations of a set of fine locations} on or in the IC under test {using electronic beam steering of the focused optical beam to optically inject carriers into the IC under test, and with the focal point of the focused optical beam positioned at each fine location}, measuring an output signal comprising a value, a set of values, or a waveform at each pixel or voxel of the image tile generated by the IC under test in response to the optical carrier injection (laser is rastered across the DUT (i.e., IC under test)…the intrinsic electric fields of junctions in the DUT transport the charge carriers in the form of a current signal…An image is generated where the intensity of the pixel represents the detected current; Simon, [p 3, §III. A., Col 1, ¶1:4-12]);
using an electronic processor, stitching the image tiles together to generate an image of the IC under test (Mosaic stitching capabilities enable an entire IC to be scanned and aggregated into a full device image; Simon, [p 3, Col 2, §III. A., ¶1])
computing a comparison between the image of the IC under test and a reference image (we compare the predicted TOBIC image from the trained CGAN model (i.e., reference image) and the actual signature from the modified chip (i.e., image of IC under test); Simon, [p 2, §1, Col 1, ¶1:11-13]); and
identifying suspect regions of the IC under test based on the computed comparison (using the similarity metrics to demonstrate the identification of the deviations from the circuit edit; Simon, [p 2, §1, Col 1¶1:13-15]).
Simon does not explicitly teach sequentially mechanically positioning a focal point of a focused optical beam at coarse locations of a set of coarse locations in or on an IC under test; with the focal point of the focused optical beam positioned at each coarse location; steering the focal point of the focused optical beam to fine locations of a set of fine locations on or in the IC under test using electronic beam steering of the focused optical beam to optically inject carriers into the IC under test, and with the focal point of the focused optical beam positioned at each fine location.
However, Sandkuijl discloses sequentially mechanically positioning a focal point of a focused optical beam at coarse locations of a set of coarse locations in or on an IC under test; with the focal point of the focused optical beam positioned at each coarse location (Sandkuijl, ¶[0155]; scanning the sample through a range of positions, in a relatively coarse manner with large distances between the positions, and picking the position which is closest to the focal plane of the autofocussing system (i.e. which has the highest focus score)); steering the focal point of the focused optical beam to fine locations of a set of fine locations on or in the IC under test using electronic beam steering of the focused optical beam to optically inject carriers into the IC under test, and with the focal point of the focused optical beam positioned at each fine location (Sandkuijl, ¶[0155]; further refinement about that position can be performed, by again moving the sample through a series of positions, wherein the positions are much closer together in the refinement step in comparison to the prior coarser step; the method comprises a first coarse estimate of the focal position followed by one or more further rounds which refine the position of the sample to bring it closer to the focal plane; ¶[0166]).
Regarding claim 3, the combination of Simon and Sandkuijl teaches the IC validation method of claim 1. Simon further teaches wherein the IC under test is fabricated in accordance with an IC under test layout, the method further comprising:
acquiring images of one or more training ICs fabricated in accordance with one or more training IC layouts by scanning the optical beam over the one or more training ICs (Two 130 nm test articles, containing a variety of similar and unique structures were used to test the TOBIC imaging capabilities and deep learning process. The matching architectures of the SPI in both chips provided independent testing and training data to evaluate the deep learning models enabling the evaluation of this methodology; Simon, [p 4, §III. C., Col 1, ¶1]) to optically inject carriers into the one or more training ICs and measuring an output signal comprising a value, a set of values, or a waveform at each pixel or voxel generated by the one or more training ICs in response to the optical carrier injection (laser is rastered across the DUT (i.e., IC under test)…the intrinsic electric fields of junctions in the DUT transport the charge carriers in the form of a current signal…An image is generated where the intensity of the pixel represents the detected current; Simon, [p 3, §III. A., Col 1, ¶1:4-12]);
training a deep learning algorithm to transform the one or more training IC layouts to the images of the one or more training ICs (Deep learning algorithms, implemented using a Conditional Generative Adversarial Network (CGAN) in the Pix2Pix framework, were used to train a model for the translation of GDSII layer images to TOBIC mosaic images; Simon, [p 3, §III. B., Col 2, ¶1:1-3]); and
transforming the IC under test layout using the trained deep learning algorithm to generate the reference image (only three GDSII layers were used, and they were mapped to a three-channel RGB image for integration into Pix2Pix. The GDSII and TOBIC images were aligned, split into 128 x 128 pixel images, and separated into a training and test set of data. To create a more robust model from the relatively sparse amount of data for training, extra training data was produced by data augmentation.; Simon, [pg. 3, §III. B., Col 2, ¶1]).
Regarding claim 4, the combination of Simon and Sandkuijl teaches the IC validation method of claim 3. Simon further teaches wherein the deep learning algorithm comprises a Conditional Generative Adversarial Network (C-GAN) (Deep learning algorithms, implemented using a Conditional Generative Adversarial Network (CGAN) in the Pix2Pix framework, were used to train a model for the translation of GDSII layer images to TOBIC mosaic images; Simon, [p 3, §III. B., Col 2, ¶1:1-4])
Regarding claim 5, the combination of Simon and Sandkuijl teaches the IC validation method of claim 3. Simon further teaches wherein the IC under test layout and the one or more training IC design layouts are GSDII layouts (Deep learning algorithms, implemented using a Conditional Generative Adversarial Network (CGAN) in the Pix2Pix framework, were used to train a model for the translation of GDSII layer images to TOBIC mosaic images; Simon, [p 3, §III. B., Col 2, ¶1:1-4]).
Regarding claim 6,. the combination of Simon and Sandkuijl teaches the IC validation method of claim 1. Simon further teaches further comprising:
identifying regions depicting instances of standard cells in the reference image (logic cells from TOBIC imagery were systematically identified… classification results are shown in Figure 3(b), where the detected cells are outlined in red, and the determined cell type is overlayed in white; Simon, [p 4, §IV, Col 2, ¶3:1-2, 6-8]);
wherein the computing of the comparison comprises computing an error metric for each of the identified regions (To evaluate the accuracy of the model, a test set of images were produced and the pixel-wise error or a similarity metric was calculated; Simon, [p 3, §III. B., Col 2, ¶1:12-14])
Regarding claim 7, the combination of Simon and Sandkuijl teaches the IC validation method of claim 6. Simon further teaches wherein the error metric comprises a mean squared error (MSE) or a structural similarity index measure (SSIM) (An image difference and normalized Mean Square Error (MSE) value was computed between both of the above combinations with the results included in Figure 3(c); Simon, [p 4, §IV, Col 1, ¶2:5-7]).
Regarding claim 8, the combination of Simon and Sandkuijl teaches the IC validation method of claim 1. Simon further teaches further comprising: displaying the image of the IC under test on a display with the suspect regions highlighted in the displayed image of the IC under test (The resulting difference images are displayed using a common pseudo color scale where the brighter colors (green and yellow) represent a greater difference between the two images; Simon, [p 4, §IV, Col 1, ¶2:7-10])).
Regarding claim 9, the combination of Simon and Sandkuijl teaches the IC validation method of claim 1. Simon further teaches wherein the IC validation method does not include thinning or removing a substrate of the IC under test (Simon teaches that optical beam induced current (OBIC) requires thinning the device due to the absorption of the laser beam in the bulk silicon and the large diffraction limited focal point size. An alternative, the two-photon induced current beam (TOBIC), similarly claimed in the invention, has lower absorption volume in both the lateral and axial directions where thinning is not required; Simon, [p 4, §IV, Col 1, ¶2:5-7])
Regarding claim 13, the combination of Simon and Sandkuijl teaches the IC validation method of claim 1. Sandkuijl further teaches wherein the sequentially mechanical positioning of the focal point of the focused optical beam comprises translating the IC under test relative to the focal point of the focused optical beam using a mechanical translation stage on which the IC under test is disposed (Sandkuijl, ¶[0063] The apparatus may be configured to provide autofocusing (e.g., autofocusing correction) by moving the sample stage and/or adjusting optical elements. In certain aspects, the apparatus may be configured to provide autofocusing by moving the sample stage in response to a readout from the autofocus component. In certain aspects, the apparatus is not configured for autofocusing by adjusting optics, such as when only the z-position of a sample stage is moved. As such, optics may not be movable to provide focusing.)
Claim 15 is similarly analyzed as analogous claim 1.
Regarding Claim 16, Simon teaches an integrated circuit (IC) validation device comprising:
an optical carrier injection imaging system for acquiring an image of an IC under test (Two-photon Optical Beam Induced Current (TOBIC) imaging; Simon, [p 1, §1, Col 2, ¶3]), the optical carrier injection imaging system configured to scan an optical beam over an IC under test (allows the laser to rapidly scan across the Device Under Test (DUT); Simon, [p 3, §III. A., Col 1, ¶1]) to optically inject carriers into the IC under test (the IR femtosecond laser excites charge carriers in the IC’s circuitry; Simon, [p 3, §III. A., Col 1, ¶1]) and to measure an output signal comprising a value, a set of values, or a waveform at each pixel or voxel of the image generated by the IC under test in response to the optical carrier injection (The intrinsic electric fields of junctions in the DUT transport the charge carriers through the VCC and Ground pads where they are detected in the form of a current signal using a lock-in detection scheme synced to the laser’s repetition rate for a high SNR. An image is generated where the intensity of the pixel represents the detected current; Simon, [p 3, §III. A., Col 1, ¶1]);
an electronic processor programmed to (See Simon, FIG 2 exhibits a Data Acquisition and Control including a computer (e.g., processor)):
compute a difference image between the image of the IC under test and {a reference} image (Simon teaches a difference image between different cells, rather than difference between test and reference images: “to differentiate between logic cells, a test comparison of a DFFSR cell and buffer/XOR cell as well as a control comparison between two different DFFSR cells was conducted. An image difference and normalized Mean Square Error (MSE) value was computed between both of the above combinations with the results included in Figure 3(c). An image difference and normalized Mean Square Error (MSE) value was computed between both of the above combinations with the results included in Figure 3(c)”, and not the difference between the test and reference images Simon, [p 4, Col 1, §IV, ¶2]; FIG 3(c) shown below:
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);
identify suspect regions of the IC under test based on the computed {difference image}, wherein each suspect region deviates significantly from the reference image (See FIG 3c shown above, and “The resulting difference images are displayed using a common pseudo color scale where the brighter colors (green and yellow) represent a greater difference between the two images”; Simon, [p 4, Col 1, §IV, ¶2]);
{identify a source of the deviation of at least one suspect region from the reference image based on an analysis of the deviation of the at least one suspect region from the reference image};
generate a validation report (interpretation: specification, ¶[0030] In an output operation 7, a validation report for the IC under test is generated which identifies the suspect regions and the results of any further analysis performed at optional operation 6. For example, the validation report may include the images of the IC under test and the reference IC with the suspect regions highlighted by a red outline or other highlighting ) presenting the suspect regions and further including the source of the deviation of the at least one suspect region from the reference image (See Simon FIG 6 (e) and (f), shown below, exhibits validation report presenting suspect regions outlined. [caption] “(e) MSE between the TOBIC image of the modified (i.e., with defect) and unmodified chip (i.e., reference, or without defect). (f) MSE between the modified chip TOBIC image (i.e., with defect) and the synthesized TOBIC image of the unmodified chip (i.e., synthesized reference)”.
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); and
a display configured to present the report (See Simon FIG 2 exhibits a computer with display to present the report of FIG 6.).
Simon does not explicitly disclose a difference image, wherein each suspect region deviates significantly from the reference image.
However, Talbot, a similar field of endeavor of detecting defects in patterned substrates, teaches: an electronic processor programmed to (image-capture processing electronics 672; Talbot, [Col 11:65]):
compute a difference image between the image of the IC under test and a reference image (conventional pixel-to-pixel subtraction in which each pixel of an image is subtracted from the corresponding pixel in a reference image; Talbot, [Col 13:62-64]);
identify suspect regions of the IC under test based on the computed difference image, wherein each suspect region deviates significantly from the reference image; identify a source of the deviation of at least one suspect region from the reference image based on an analysis of the deviation of the at least one suspect region from the reference image (The resulting difference image then shows any real defects (image differences) as well as nuisance information (i.e., source of deviation); Talbot, [Col 13:64-14:1]);
generate a validation report presenting the suspect regions and further including the source of the deviation of the at least one suspect region from the reference image (report or display defects (for example, in KLA wafer-map format); Talbot, [Col 14:63-64]); and
a display configured to present the report (a display 1250; Talbot, [Col 17:9]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include computing a difference image between the DUT image and a reference image and identify the source as taught by Talbot to the invention Simon. The motivation to do so would be to reveal nuisance information caused by subtle but real differences between the images that are not killer defects.
Claim 18 is similarly analyzed as analogous claim 3.
Regarding claim 21, the combination of Simon and Talbot teaches the IC validation device of claim 16. Simon further teaches wherein the electronic processor is programmed to identify the source of the deviation of the at least one suspect region based on a magnitude of the deviation of the at least one suspect region from the reference image (normalized Mean Square Error (MSE) value was computed (i.e. magnitude of deviation); Simon [p 4, §IV, Col 1, ¶2:5-6]).
Regarding claim 22, the combination of Simon and Talbot teaches the IC validation device of claim 16. Simon further teaches wherein the electronic processor is programmed to identify the source of the deviation of the at least one suspect region based on a sign of the difference of the at least one suspect region from the reference image (error maps (i.e., sign); Simon, [p 4, §IV, Col 1, ¶2:11]).
Regarding claim 23, the combination of Simon and Talbot teaches the IC validation device of claim 16. Simon further teaches wherein the electronic processor is programmed to identify the source of the deviation of the at least one suspect region based on a distribution or pattern of differences of the at least one suspect region from the reference image (The resulting difference images are displayed using a common pseudo color scale where the brighter colors (green and yellow) represent a greater difference between the two images. Upon visual inspection of the error maps, a patterned structure is present in the comparison of the DFFSR and Buffer/XOR cell, while there are only a couple faint patches present; Simon, [p 4, §IV, Col 1, ¶2:8-14]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Simon in view of Lee et al. US 20170047195 A1, hereinafter “Lee”.
Regarding claim 2, Simon discloses an integrated circuit (IC) validation method comprising:
{acquiring a reference image of a reference IC by scanning the optical beam over the reference IC} to optically inject carriers into the reference IC and measuring an output signal comprising a value, a set of values, or a waveform at each pixel or voxel generated by the reference IC in response to the optical carrier injection;
acquiring an image of an IC under test by scanning the optical beam over the IC under test to optically inject carriers into the IC under test and measuring an output signal comprising a value, a set of values, or a waveform at each pixel or voxel of the image generated by the IC under test in response to the optical carrier injection (laser is rastered across the DUT (i.e., device/IC under test)…the intrinsic electric fields of junctions in the DUT transport the charge carriers in the form of a current signal…An image is generated where the intensity of the pixel represents the detected current; Simon, [p 3, §III. A., Col 1, ¶1:4-12]);
computing a comparison between the image of the IC under test and the reference image acquired of the reference IC (we compare the predicted TOBIC image from the trained CGAN model (i.e., reference image) and the actual signature from the modified chip (i.e., image of IC under test); Simon, [p 2, §1, Col 1, ¶1:11-13]); and identifying suspect regions of the IC under test based on the computed comparison (using the similarity metrics to demonstrate the identification of the deviations from the circuit edit; Simon, [p 2, §1, Col 1, ¶1:13-15]).
Simon teaches that a reference image is generated by a deep learning process, but does not explicitly teach acquiring a reference image of a reference IC.
However, Lee teaches acquiring a reference image of a reference IC by scanning the optical beam over the reference IC to optically inject carriers into the reference IC and measuring an output signal comprising a value, a set of values, or a waveform at each pixel or voxel generated by the reference IC in response to the optical carrier injection (reference image may be any suitable reference image known in the art.; the test image may be acquired at one instance of pattern(s) formed on a wafer and the reference image may be acquired at another instance of the pattern(s) formed on the wafer (i.e., the reference IC is on the same wafer as the test IC, however they are separate ICs). Therefore, the test and reference images may be generated by the optical inspection system; Lee, ¶[0064]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Simon in view of Talbot and further in view of Lee et al. US 20170047195 A1, hereinafter “Lee”.
Claim 17 is similarly analyzed as analogous claim 2.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Simon in view of Sandkuijl, and further in view of Xu et al, (Xu, C. and Denk, W., "Two-photon optical beam induced current (OBIC) imaging through the backside of integrated circuits," in Conference on Lasers and Electro-Optics, D. Killinger, G. Valley, C. Chang-Hasnain, and W. Knox, eds., Vol. 11 of OSA Technical Digest (Optica Publishing Group, 1997), paper CPD2), hereinafter “Xu”.
Regarding claim 10, the combination of Simon and Sandkuijl teaches the IC validation method of claim 1. Simon further taches focusing the pulsed optical beam at a focal point in an active layer disposed on a frontside of the substrate of the IC under test (An IR femtosecond laser is chosen for this application and is focused through the substrate onto a point in the active region of the device; Simon, [pg. 2, §II. A., Col 2, ¶2:3-5]).
The combination does not explicitly teach wherein the optical beam comprises a pulsed optical beam having pulse duration of 900 femtoseconds or lower; the acquiring of the image of the IC under test includes: applying the pulsed optical beam on a backside of a substrate of the IC under test; and wherein a photon energy of the pulsed optical beam is lower than a bandgap of the substrate; and wherein photons of the optical beam are absorbed at the focal point in the active layer of the IC under test by nonlinear optical interaction to inject carriers at the focal point in the active layer.
However, Xu teaches wherein the optical beam comprises a pulsed optical beam having pulse duration of 900 femtoseconds or lower (the illumination source was an optical parametric oscillator 120 fs pulses with 80 MHz repetition rate; Xu, [p 2578, Col 2, ¶2:1-5]), and
the acquiring of the image of the IC under test includes: applying the pulsed optical beam on a backside of a substrate of the IC under test (See Xu, FIG 1, shown below, where the polished surface is the backside, and the beam is shown being applied to the back of the substrate of the IC under test); and
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wherein a photon energy of the pulsed optical beam is lower than a bandgap of the substrate; and wherein photons of the optical beam are absorbed at the focal point in the active layer of the IC under test (An excitation beam with a photon energy below the band gap can traverse even thick substrates virtually unattenuated; [Abstract]; If the wavelength is chosen so that the photon energy is slightly below the band gap, one-photon absorption is almost completely eliminated while minimizing the loss of resolution due to the increase in wavelength; Xu, [p 2578, Col 1, ¶3:3-11]) by nonlinear optical interaction to inject carriers at the focal point in the active layer (The advantages of nonlinear excitation have also been demonstrated for laser scanning fluorescence microscopy; Xu, [p 2578, Col 2, ¶1:1-7]).
Simon and Xu are analogous art because they are from the same field of endeavor of two-photon optical beam scanning of integrated circuits. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include an ultrashort photon beam pulse as taught by Xu to the invention of Simon. The motivation to do so would be to have a broadband spectrum increasing the optical requirements to focus the photon beam to a tiny spot.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a photon energy that is lower than the substrate bandgap as taught by Xu to the combined invention of Simon and Sandkuijl. The motivation to do so would be to avoid substrate absorption of the beam and attenuation of the beam through the substrate.
Regarding claim 11, the combination of Simon, Sandkuijl, and Xu teach the IC validation method of claim 10. Xu further teaches wherein the photon energy of the pulsed optical beam is lower than a bandgap of the active layer (the quadratic intensity dependence of two-photon excitation, electron-hole pairs are generated rather efficiently at the focus (i.e., active layer) but virtually nowhere else (i.e., the energy is below the bandgap of the active layer); Xu, [p 2578, Col 1, ¶3:3-11]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a photon energy that is lower than the active layer bandgap as taught by Xu to the combined invention of Simon and Sandkuijl. The motivation to do so would be to enable minimal absorption and efficient focus at the active layer and out of focus at background layer.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Simon in view of Sandkuijl, and further in view of Lo (US 20050073675 A1).
Regarding claim 14, the combination of Simon and Sandkuijl teaches the method of claim 1. The combination does not explicitly teach wherein the electronic beam steering is performed using a galvo mirror, and an optical train including an f-theta scan lens and an objective are used to generate the focused optical beam.
However, Lo teaches wherein the electronic beam steering is performed using a galvo mirror, and an optical train including an f-theta scan lens and an objective are used to generate the focused optical beam (F-theta lens 106 converts the angular scan produced by galvo-mirrors 104; Lo, ¶[0022]).
Simon and Lo are analogous art because they are from the same field of endeavor of integrated circuit wafer and die testing using scanning optical microscopes. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include an f-theta scan lens and galvo mirror as taught by Lo to the combined invention of Simon and Sandkuijl. The motivation to do so would be to image a flat focal plane with the photon beam.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Simon in view of Talbot, and further in view of Lo (US 20050073675 A1).
Claim 20 is similarly analyzed as analogous claims 1, 13 and 14.
Regarding claim 20, the combination of Simon and Talbot teaches the IC validation device of claim 16. Simon further teaches wherein the optical beam is a focused optical beam (IR femtosecond laser is chosen for this application and is focused through the substrate onto a point in the active region of the device; Simon, [p 2, Col 2, §2A, ¶2]) and wherein: the optical carrier injection imaging system includes:
an optical train arranged to focus the optical beam at a focal point (See Simon FIG 2, exhibits “Scanning Laser Components”, including an optical train focusing the beam at a “Sample” (i.e., focal point)),
a translation stage configured to move the IC under test to sequentially place the focal point at coarse locations of a set of coarse locations in or on the IC under test (See Simon FIG 2 exhibits “Translation Sample Stage”), and
{an electronic beam steering device configured to, with the focal point at each coarse location, steer the focal point to fine locations of a set of fine locations on or in the IC under test whereby} the optical carrier injection system acquires an image tile at the coarse location (An image is generated where the intensity of the pixel represents the detected current magnitude; Simon, [p 3, Col 1, §III.A., ¶1]); and
the electronic processor is programmed to stitch the image tiles together to generate the image of the IC under test (Mosaic stitching capabilities enable an entire IC to be scanned and aggregated into a full device image; Simon, [p 3, Col 2, §III. A., ¶1]).
Simon does not explicitly disclose an electronic beam steering device configured to, with the focal point at each coarse location, steer the focal point to fine locations of a set of fine locations on or in the IC under test.
However, Sankuijl teaches an electronic beam steering device configured to, with the focal point at each coarse location (scanning the sample through a range of positions, in a relatively coarse manner with large distances between the positions; Sandkuijl, ¶[0155]), steer the focal point to fine locations of a set of fine locations on or in the IC under test (further refinement about that position can be performed, by again moving the sample through a series of positions; Sandkuijl, ¶[0155]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Simon in view of Xu and further in view of Talbot.
Claim 19 is similarly analyzed as analogous claims 10 and 13.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ozaki et al., (US 5331275 A), would have been relied upon for teaching coarse and fine mechanical stages, sequential measurements, in addition to a voltage measurement unit.
Li (Anhu Li, Xuchun Jiang, Jianfeng Sun, Lijuan Wang, Zhizhong Li, and Liren Liu, "Laser coarse–fine coupling scanning method by steering double prisms," Appl. Opt. 51, 356-364 (2012)) teaches double-prism scanner that combines the two scanning modes of rotating and titling motions into a nested device.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHANDHANA PEDAPATI whose telephone number is (571)272-5325. The examiner can normally be reached M-F 8:30am-6pm (ET).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chan Park can be reached at 5712727409. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHANDHANA PEDAPATI/Examiner, Art Unit 2669 /CHAN S PARK/Supervisory Patent Examiner, Art Unit 2669