DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/02/2026 has been entered.
Notice to Applicant
This office action is in response to the amendment filed on 07/02/2026.
Affidavit filed on 07/02/2026 was received and acknowledged.
Limitations appearing inside of {} are intended to indicate the limitations not taught by said prior art(s)/combinations.
Response to Amendments
The Amendment filled 07/02/2026 in response to the Final Office Action mailed 02/02/2026 has been entered. Claims 1,13, 14, 16, 21, 22, and 23 have been amended. Claims 12 and 15 have been previously canceled. Rejections under 35 USC §103 have been withdrawn in light of amended claims 07/02/2026, and affidavit filed on 07/02/2026.
Claims 1-11, 13-14, and 16-23 are pending in the application.
Response to Arguments/Remarks
Applicant’s arguments with respect to claims 1,13, 14, 16, 21, 22, and 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Remarks on page 9, shown below, states IDS is submitted, however, no IDS has been submitted with the amendment of 07/02/2026.
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Information Disclosure Statement
No Information Disclosure Statement (IDS) was filed; therefore, no applicant-submitted references were considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 6, 8, 18, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Ross ‘811” (Ross et al., US 20140149811 A1), previously cited in (PTO-892 on 08/12/2025).
1. (Currently Amended) Ross ‘811 teaches an integrated circuit (IC) validation method comprising:
acquiring an image of an IC under test by scanning an optical beam over the IC under test to optically inject carriers into the IC under test (A laser 132 produces an incident beam 128 that is steered to an illumination location on the backside of the target device 102 (e.g., an IC); The radiation of the beam interacts with the charge carriers within the IC, and the reflection of the beam from the IC is modulated by such interactions to create a modulated reflected beam 122; Ross ‘811, ¶[0063]), and
measuring an output signal comprising a value, a set of values, or a waveform at each pixel or voxel of the image generated by the IC under test in response to the optical carrier injection (The output signal from the photon detector, shown as signal 136, results from detection of photons that are then transduced into an electrically-varying signal; Ross ‘811, ¶[0065]);
computing a comparison between the image of the IC under test and a reference image (reference pattern is compared to a series of measured logic states; Ross ‘811, ¶[0089]); and
identifying suspect regions of the IC under test based on the computed comparison (the comparison determines a match/no-match for each clock cycle. The "matched" bits are then used for pass/fail testing criteria; Ross ‘811, ¶[0089]).
2. (Previously Presented) Ross ‘811 teaches an integrated circuit (IC) validation method comprising:
acquiring a reference image of a reference IC by scanning the optical beam over the reference IC to optically inject carriers into the reference IC and measuring an output signal comprising a value, a set of values, or a waveform at each pixel or voxel generated by the reference IC in response to the optical carrier injection (the reference patterns may be generated by capturing patterns of interest from: Other circuit locations within the same IC or other ICs. For instance, a logic pattern measured at the first cell of a scan chain can be used as a reference logic pattern to apply to scan cells further down the chain; Ross ‘811, ¶¶[0068-0069]);
acquiring an image of an IC under test by scanning the optical beam over the IC under test to optically inject carriers into the IC under test and measuring an output signal comprising a value (The radiation of the beam interacts with the charge carriers within the IC is modulated by such interactions to create a modulated reflected beam 122.; Ross ‘811, ¶[0063]), a set of values, or a waveform at each pixel or voxel of the image generated by the IC under test in response to the optical carrier injection (within a few pixels of accuracy ( e.g. , sub - pixel accuracy); Ross ‘811, [0043]);
computing a comparison between the image of the IC under test and the reference image acquired of the reference IC (reference pattern is compared to a series of measured logic states; Ross ‘811, ¶[0089]); and
identifying suspect regions of the IC under test based on the computed comparison (the comparison determines a match/no-match for each clock cycle. The "matched" bits are then used for pass/fail testing criteria; Ross ‘811, ¶[0089]).
6. (Original) Ross ‘811 teaches the IC validation method of claim 1. Ross ‘811 further teaches further comprising:
identifying regions depicting instances of standard cells (the spatial location of logic cells (e.g., scan cells) can be translated to the scanning optical microscope (SOM) stage coordinates and then scanned or probed within the cell(s) only in the form of separated automated optical inspections performed within an area of interest (AOI); Ross ‘811, ¶[0084]) in the reference image (A time-based logic pattern in a loop sequence (e.g., using a generated reference logic state or pattern 148) can be used … to illuminate specific XY sites in order to read the time-variant logic values at said sites; Ross ‘811, ¶[0086]);
wherein the computing of the comparison comprises computing an error {metric} for each of the identified regions (A match of a particular probed logic value can be displayed, as can be a mismatch. In some embodiments a particular time-series of logic values is needed to verify expected operation. A time-based logic pattern in a loop sequence (e.g., using a generated reference logic state or pattern 148) can be used in conjunction with a laser probe to illuminate specific XY sites in order to read the time-variant logic values at said sites.; Ross ‘811, ¶[0085]; Error metric is interpreted as follows: [0155] Cross referencing logic cell chains or cones and correlate the cells to determine a passing or failing status. [0156] Sampling Boolean logic and filtering or averaging such as by using thresholding techniques, and/or box car averaging, and/or edge enhancements etc. [0157] Calculating a minimum number of samples to determine a passing state within a statistical likelihood. [0158] Autocorrelation analysis in order to determine probability of a match to the pre-determined logic pattern).
8. (Original) Ross ‘811 teaches the IC validation method of claim 1. Ross ‘811 further teaches further comprising: displaying the image of the IC under test on a display with the suspect regions highlighted in the displayed image of the IC under test (Matches and mismatches can be displayed at a corresponding XY location on a display surface (see operation 180). A match of a particular probed logic value can be displayed, as can be a mismatch; Ross ‘811, ¶¶[0085]-[0086]; FIG. 2 depicts an analysis technique to analyze a time-based logic pattern in a loop sequence to verify and highlight expected logic transitions; Ross ‘811 ¶[0028]).
13. (Currently Amended) Ross ‘811 teaches the IC validation method of claim 1. Ross ‘811 further teaches further comprising sequentially mechanically positioning a focal point of the optical beam by translating the IC under test relative to the focal point of the optical beam using a mechanical translation stage on which the IC under test is disposed (a target device 102 is affixed to a stage, and the stage can be moved in the X and Y directions within the XY plane. Or, a target device 102 is affixed to a stage, and the laser 132 and detector 126 can be moved in the X and Y Ross, ‘811, ¶[0122]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Ross ‘811 in view of “Sah” (Sah et al., US 20220270212 A1).
3. (Original) Ross ‘811 teaches the IC validation method of claim 1. Ross ‘811 further teaches wherein the IC under test is fabricated in accordance with an IC under test layout (GDSII layout; Ross ‘811, ¶[0099]), the method further comprising:
acquiring images of one or more training ICs fabricated in accordance with one or more training IC layouts (acquire , with the characterization sub - system 202 , one or more training images 234; Ross ‘811, [0038]) by scanning the optical beam over the one or more training ICs to optically inject carriers into the one or more training ICs (The radiation of the beam interacts with the charge carriers within the IC is modulated by such interactions to create a modulated reflected beam 122.; Ross ‘811, ¶[0063]) and measuring an output signal comprising a value, a set of values, or a waveform at each pixel or voxel generated by the one or more training ICs in response to the optical carrier injection (The output signal from the photon detector, shown as signal 136, results from detection of photons that are then transduced into an electrically-varying signal. In exemplary embodiments, the signal 136 is processed by a high band width preamp and a bias tee (e.g., to separate AC components from the DC components of interest). The DC components can be used for various forms of imaging. The AC components are further amplified (e.g., using a high bandwidth amplifier) and provided to inputs of a digitizer; Ross ‘811, ¶[0065]);
{training a deep learning algorithm to transform the one or more training IC layouts to the images of the one or more training ICs; and
transforming the IC under test layout using the trained deep learning algorithm to generate the reference image}.
Ross ‘811 does not explicitly disclose training a deep learning algorithm to transform the one or more training IC layouts to the images of the one or more training ICs; and transforming the IC under test layout using the trained deep learning algorithm to generate the reference image.
However Sah, a similar field of endeavor of machine learning generated images for improving optical inspection of chip design, teaches training a deep learning algorithm to transform the one or more training IC layouts to the images of the one or more training ICs (the controller 204 is configured to align one or more training images 234 with one or more training design images 302; alignment may be performed by a characterization system 200 that is configured to be capable of alignment within a few pixels of accuracy; that having some training pairs (e.g., a training image 234 aligned with a training design image 302) with alignment accuracy error within a few pixels is not only acceptable, but may help to regularize (i.e., train) the machine learning model; Sah, ¶[0043]); and
transforming the IC under test layout using the trained deep learning algorithm to generate the reference image (a design of the specimen may be modified through geometric transformations that may, in some embodiments, be configured to modify the design such that the design is more conducive to being used as training data of a machine learning model; Sah, ¶[0042]; The enhanced images may appear to be, but not limited to, a design image (e.g., derived design image) or an approximation of a design image; Sah ¶[0053]; the enhanced images 308 generated by the machine learning model 304 may be used as reference images for subsequent characterization, inspection, and detection; Sah, ¶[0055]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include training the model to transform the data as taught by Sah to the invention of Ross ‘811. The motivation to do so would be to prevent overfitting the machine learning model.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include generating reference data as taught by Sah to the invention of Ross ‘811. The motivation to do so would be because acquiring additional or higher resolution SEM images may be difficult, time consuming, and expensive to create for training data.
4. (Original) The combination of Ross ‘811 and Sah teaches the IC validation method of claim 3. Sah further teaches wherein the deep learning algorithm comprises a Conditional Generative Adversarial Network (C-GAN).(machine learning model 304 may include … a conditional generative adversarial network (CGAN); Sah, ¶[0049]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include C-GAN as taught by Sah to the invention of Ross ‘811. The motivation to do so would be to feed the model the label information (Singh 2020, see PTO-892 Notice of References Cited for full citation).
5. (Previously Presented) The combination of Ross ‘811 and Sah teaches the IC validation method of claim 3. Ross ‘811 further teaches wherein the IC under test layout and the one or more training IC design layouts are GDSII layouts (GDSII layout; Ross ‘811, ¶[0099]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ross ‘811 in view of “Lavley” (Lavley et al., US 20190311881 A1).
7. (Original) Ross ‘811 further teaches the IC validation method of claim 6.
Ross ‘811 does not explicitly disclose wherein the error metric comprises a mean squared error (MSE) or a structural similarity index measure (SSIM).
However, Lavley, a similar field of endeavor of imaging an IC sample, teaches wherein the error metric comprises a mean squared error (MSE) or a structural similarity index measure (SSIM) (mean squared error between predicted interferometer readouts from a nominal stage system and measured interferometer readouts; Lavley, ¶[0113]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include MSE error metric as taught by Lavley to the invention of Ross ‘811. The motivation to do so would be to minimize the error treated as fitting parameters to be solved for.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ross ‘811 in view of “Dantus” (Dantus, US 7973936 B2).
9. (Original) Ross ‘811 teaches the IC validation method of claim 1.
Ross ‘811 does not explicitly disclose wherein the IC validation method does not include thinning or removing a substrate of the IC under test.
However, Dantus, a similar field of endeavor of detection of defects in a substrate using an optical beam, teaches wherein the IC validation method does not include thinning or removing a substrate of the IC under test (Two-photon microscopy provides significant possibilities for fluorescence imaging and photochemistry. It offers attractive advantages, including higher resolution, background-free signal, lower background scattering, better penetration in thick samples, and reduced photon-induced damage, which arise from the basic physical principle that the absorption depends on the square of the excitation intensity; Dantus, [Col 20:26-32]; better penetration in thick samples and reduced photon-induced damage are interpreted not needing to thin or remove substrate of the IC under test.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include not needing to thin the substrate as taught by Dantus to the invention of Ross ‘811. The motivation to do so would be because a two-photon beam has lower absorption, reducing the need to thin the material to avoid damage.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Ross ‘811 in view of “Xu” (Xu, C. and Denk, W., "Two-photon optical beam induced current (OBIC) imaging through the backside of integrated circuits," in Conference on Lasers and Electro-Optics, D. Killinger, G. Valley, C. Chang-Hasnain, and W. Knox, eds., Vol. 11 of OSA Technical Digest (Optica Publishing Group, 1997), paper CPD2), previously cited in PTO-892 on 08/12/2025.
10. (Original) Ross ‘811 teaches the IC validation method of claim 1.
Ross ‘811 further teaches wherein the optical beam comprises a pulsed optical beam having pulse duration of {900 femtoseconds or lower}, and the acquiring of the image of the IC under test includes:
applying the pulsed optical beam on a backside of a substrate of the IC under test focusing the pulsed optical beam at a focal point in an active layer disposed on a frontside of the substrate of the IC under test (The incident beam might be steered at a fixed angle by a mirror or might be steered to any arbitrary XY location on the backside of the IC (e.g., using XY scan mirror 119; Ross ‘811, ¶[0063]. logic value or values from any area or areas of an integrated circuit (IC) detected from viewing the backside of the IC can be imaged; Ross ‘811, ¶[0100]); and
{wherein a photon energy of the pulsed optical beam is lower than a bandgap of the substrate}; and
{wherein photons of the optical beam are absorbed at the focal point in the active layer of the IC under test by nonlinear optical interaction to inject carriers at the focal point in the active layer}.
Ross ‘811 does not explicitly disclose optical beam having pulse duration of 900 femtoseconds or lower; and wherein a photon energy of the pulsed optical beam is lower than a bandgap of the substrate; and wherein photons of the optical beam are absorbed at the focal point in the active layer of the IC under test by nonlinear optical interaction to inject carriers at the focal point in the active layer
However, Xu, a similar field of endeavor of optical beam scanning of integrated circuits, teaches wherein the optical beam comprises a pulsed optical beam having pulse duration of 900 femtoseconds or lower (the illumination source was an optical parametric oscillator 120 fs pulses with 80 MHz repetition rate; Xu, [p 2578, Col 2, ¶2:1-5]), and
wherein a photon energy of the pulsed optical beam is lower than a bandgap of the substrate; and wherein photons of the optical beam are absorbed at the focal point in the active layer of the IC under test (An excitation beam with a photon energy below the band gap can traverse even thick substrates virtually unattenuated; [Abstract]; If the wavelength is chosen so that the photon energy is slightly below the band gap, one-photon absorption is almost completely eliminated while minimizing the loss of resolution due to the increase in wavelength; Xu, [p 2578, Col 1, ¶3:3-11]) by nonlinear optical interaction to inject carriers at the focal point in the active layer (The advantages of nonlinear excitation have also been demonstrated for laser scanning fluorescence microscopy; Xu, [p 2578, Col 2, ¶1:1-7]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include an ultrashort photon beam pulse as taught by Xu to the invention of Ross ‘811. The motivation to do so would be to have a broadband spectrum increasing the optical requirements to focus the photon beam to a tiny spot.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a photon energy that is lower than the substrate bandgap as taught by Xu to the invention of Ross ‘811. The motivation to do so would be to avoid substrate absorption of the beam and attenuation of the beam through the substrate.
11. (Original) The combination of Ross ‘811 and Xu teaches the IC validation method of claim 10. Xu further teaches wherein the photon energy of the pulsed optical beam is lower than a bandgap of the active layer.
Xu further teaches wherein the photon energy of the pulsed optical beam is lower than a bandgap of the active layer (the quadratic intensity dependence of two-photon excitation, electron-hole pairs are generated rather efficiently at the focus (i.e., active layer) but virtually nowhere else (i.e., the energy is below the bandgap of the active layer); Xu, [p 2578, Col 1, ¶3:3-11]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a photon energy that is lower than the active layer bandgap as taught by Xu to the invention of Ross ‘811. The motivation to do so would be to enable minimal absorption and efficient focus at the active layer and out of focus at background layer.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ross ‘811 in view of “Lo” (Lo, US 20050073675 A1), previously cited in PTO-892 on 02/02/2026.
14. (Currently Amended) Ross ‘811 further teaches the imaging method of claim 1. Ross ‘811 further teaches wherein the optical beam is electronically steered using a {galvo} mirror, and
an optical train including {an f-theta} scan lens and an objective are used to generate the optical beam (an incident beam steering mirror 816, and return beam mirror 818. The incident beam steering mirror 816 can be tipped/rotated so as to steer the incident laserbeam to any location on the backside of the target device 102. Similarly, the return beam mirror 818 can be tipped/rotated so as to steer the return beam to the detector; Ross ‘811, ¶[0125]).
Ross does the explicitly disclose a galvo mirror and an f-theta lens.
However, Lo, a similar field of endeavor of integrated circuit wafer and die testing using scanning optical microscopes, teaches wherein the electronic beam steering is performed using a galvo mirror, and an optical train including an f-theta scan lens and an objective are used to generate the focused optical beam (F-theta lens 106 converts the angular scan produced by galvo-mirrors 104; Lo, ¶[0022]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include an f-theta scan lens and galvo mirror as taught by Lo to the invention of Ross ‘811. The motivation to do so would be to image a flat focal plane with the photon beam.
Claims 16-18, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Ross ‘811, in view of “Talbot” (Talbot et al., US 6252412 B1), previously cited in PTO-892 on 02/02/2026.
16. (Currently Amended) Ross ‘811 teaches an integrated circuit (IC) validation device comprising:
an optical carrier injection imaging system for acquiring an image of an IC under test (scanning optical microscope; Ross ‘811, ¶[0061]), the optical carrier injection imaging system configured to scan an optical beam over an IC under test to optically inject carriers into the IC under test (The radiation of the beam interacts with the charge carriers within the IC is modulated by such interactions to create a modulated reflected beam 122.; Ross ‘811, ¶[0063]) and to measure an output signal comprising a value, a set of values, or a waveform at each pixel or voxel of the image generated by the IC under test in response to the optical carrier injection (The output signal from the photon detector, shown as signal 136, results from detection of photons that are then transduced into an electrically-varying signal. In exemplary embodiments, the signal 136 is processed by a high band width preamp and a bias tee (e.g., to separate AC components from the DC components of interest). The DC components can be used for various forms of imaging. The AC components are further amplified (e.g., using a high bandwidth amplifier) and provided to inputs of a digitizer; Ross ‘811, ¶[0065]);
an electronic processor (logic processor, Ross ‘811, ¶[0066]) programmed to: compute {a difference image} between the image of the IC under test and a reference image (the logic values corresponding to the collected samples can be compared to expected logic values (see operation 1 D06); Ross ‘811, ¶[0080]); and
identify suspect regions of the IC under test based on the computed {difference} image (t to identify logic matches and mismatches; Ross ‘811, [0081]);and
a display configured to present {report} presenting the suspect regions (Matches and mismatches can be displayed at a corresponding XY location on a display surface (see operation 180); Ross ‘811, ¶[0085]).
Ross ‘811 discloses a display presenting the matches and mismatches which may be interpreted as a report according to specification of the instant application, (¶[0030] “In an output operation 7, a validation report for the IC under test is generated which identifies the suspect regions and the results of any further analysis performed at optional operation 6. For example, the validation report may include the images of the IC under test and the reference IC with the suspect regions highlighted by a red outline or other highlighting”).
However, Talbot, a similar field of endeavor of detecting defects in patterned substrates, teaches a difference image (conventional pixel-to-pixel subtraction in which each pixel of an image is subtracted from the corresponding pixel in a reference image; Talbot, [Col 13:62-64]); and
additionally, Talbot explicitly teaches present a report (report or display defects (for example, in KLA wafer-map format); Talbot, [Col 14:63-64]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include computing a difference image between the DUT image and a reference image and identify the source as taught by Talbot to the invention Ross ‘811. The motivation to do so would be to reveal nuisance information caused by subtle but real differences between the images that are not killer defects.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include presenting a report as taught by Talbot to the invention Ross ‘811. The motivation to do so would be to enable ease of error checking for the end user.
17. (Original) The combination of Ross ‘811 and Talbot teaches the IC validation device of claim 16. Ross ‘811 further teaches wherein: the optical carrier injection imaging system is further configured to acquire an image of a reference IC by scanning the optical beam over the reference IC to optically inject carriers into the reference IC and measuring an output signal comprising a value, a set of values, or a waveform at each pixel or voxel generated by the reference IC in response to the optical carrier injection; wherein the reference image comprises the image of the reference IC (the reference patterns may be generated by capturing patterns of interest from: Other circuit locations within the same IC or other ICs. For instance, a logic pattern measured at the first cell of a scan chain can be used as a reference logic pattern to apply to scan cells further down the chain; Ross ‘811, ¶¶[0068-0069]).
Regarding Claim 18, the combination of Ross ‘811 and Talbot teaches the IC validation device of claim 16. Claim 18 is similarly analyzed as analogous claim 3.
21. (Currently Amended) The combination of Ross ‘811 and Talbot teaches the IC validation device of claim 16.
Ross ‘811 further teaches wherein the electronic processor is programmed to:
identify at least one of the suspect regions (A software module can be used to loop a test and to compare the recovered logic states (and timing information) to a reference signal in order to determine correctness of the logic patterns and to verify observation; Ross ‘811, ¶[0090]) based on a {magnitude of} the deviation of the at least one suspect region from the reference image (The reference pattern and the measured logic states are compared (e.g., using logic comparator circuitry), and the comparison determines a match/no-match for each clock cycle; Ross ‘811, ¶[0089]);
identify a source of the deviation of the at least one suspect region from the reference image based on an analysis of the deviation of the at least one suspect region from the reference image (The reference pattern and the measured logic states are compared (e.g., using logic comparator circuitry), and the comparison determines a match/no-match for each clock cycle. The "matched" bits are then used for pass/fail testing criteria; an area on the display surface corresponding to a particular XY location can be highlighted; Ross ‘811, ¶¶[0089]-[0090]); and
generate the report presenting the suspect regions and further including the source of the deviation of the at least one suspect region from the reference image (Matches and mismatches can be displayed at a corresponding XY location on a display surface (see operation 180); Ross ‘811, ¶[0085]).
Ross ‘811 does not explicitly disclose based on a magnitude of the deviation.
However, Talbot teaches based on a magnitude of the deviation (The resulting difference image then shows any real defects (image differences) as well as nuisance information caused by subtle but real differences between the images that are not killer defects (i.e., resulting differences between real and nuisance information is interpreted as “magnitude of the deviation”). Image processing techniques such as feature erosion (dilation and expansion) can be used to minimize or eliminate those of the nuisance defects which are smaller than a selected size (i.e., based on magnitude of the deviation); Talbot, [Col 13:64 – Col 14:4]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include basing the deviation detection on magnitude as taught by Talbot to the invention of Ross ‘811. The motivation to do so would be to minimize or eliminate nuisance defects which are smaller than a selected size.
22. (Currently Amended) The combination of Ross ‘811 and Talbot teaches the IC validation device of claim 21.
Ross ‘811 further teaches wherein the electronic processor is programmed to identify the source of the deviation of the at least one suspect region {based on a magnitude of the deviation of the at least one suspect region from the reference image, or on a sign of the} difference of the at least one suspect region from the reference image (A software module can be used to loop a test and to compare the recovered logic states (and timing information) to a reference signal in order to determine correctness of the logic patterns and to verify observation; Ross ‘811, ¶[0090]).
Ross ‘811 does not explicitly disclose based on a magnitude of the deviation of the at least one suspect region from the reference image, or on a sign of the difference.
However, Talbot teaches based on a magnitude of the deviation of the at least one suspect region from the reference image, or on a sign of the difference (The resulting difference image then shows any real defects (image differences) as well as nuisance information caused by subtle but real differences between the images that are not killer defects (i.e., resulting differences between real and nuisance information is interpreted as “magnitude of the deviation”). Image processing techniques such as feature erosion (dilation and expansion) can be used to minimize or eliminate those of the nuisance defects which are smaller than a selected size (i.e., based on magnitude of the deviation); Talbot, [Col 13:64 – Col 14:4]).
23. (Currently Amended) The combination of Ross ‘811 and Talbot teaches the IC validation device of claim 21.
Ross ‘811 further teaches wherein the electronic processor is programmed to identify the source of the deviation of the at least one suspect region (A software module can be used to loop a test and to compare the recovered logic states (and timing information) to a reference signal in order to determine correctness of the logic patterns and to verify observation; Ross ‘811, ¶[0090]) {based on a distribution or pattern of differences of the at least one suspect region from the reference image}.
Ross ‘811 does not explicitly disclose based on a distribution or pattern of differences of the at least one suspect region from the reference image.
However, Talbot teaches based on a distribution (KLA wafer-map format); Talbot, [Col 14:63-64]) or pattern of differences of the at least one suspect region from the reference image (the biases are set to zero or are set to maximize topographic contrast. Moreover, pattern defects can be significantly smaller than the minimum critical dimension of circuit feature size and higher magnification (more pixels per micron) may be required for reliable operation. The actual settings will vary depending on the material and layer inspected; Talbot, [Col 15:61-65])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include identifying the source of deviation based on a pattern as taught by Talbot to the invention of Ross ‘811. The motivation to do so would be to capture deviations that might be interpreted as noise due to having a lower magnitude of the deviations, however a deviation may be better indicated by the pattern.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ross ‘811 in view of Xu, and further in view of “Nakasuji” (Nakasuji et al., US 20020109090 A1).
19. (Original) The combination of Ross ‘811 and Talbot teaches the IC validation device of claim 16. Ross ‘811 further teaches wherein optical carrier injection imaging system includes:
a positioning stage configured to hold the IC under test (a target device 102 is affixed to a stage, and the stage can be moved in the X and Y directions within the XY plane. Or, a target device 102 is affixed to a stage, and the laser 132 and detector 126 can be moved in the X and Y Ross, ‘811, ¶[0122]);
{a laser configured to output the optical beam comprising a pulsed optical beam having pulse duration of 900 femtoseconds or lower};
an optical train arranged to focus the pulsed optical beam at a focal point in the IC under test to generate the output signal by absorption of the pulsed optical beam via nonlinear optical interaction at the focal point (Ross ‘811, Fig 1B, shown below, exhibits objective lens 110, tube lens 112, scan lens 114 in a train:
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); and
{a readout device comprising one or more of a voltmeter, an ammeter, or an ohmmeter configured to measure the output signal}.
Ross ‘811 does not explicitly disclose a laser configured to output the optical beam comprising a pulsed optical beam having pulse duration of 900 femtoseconds or lower; and a readout device comprising one or more of a voltmeter, an ammeter, or an ohmmeter configured to measure the output signal.
However, Xu teaches having pulse duration of 900 femtoseconds or lower (the illumination source was an optical parametric oscillator 120 fs pulses with 80 MHz repetition rate; Xu, [p 2578, Col 2, ¶2:1-5]); an optical train arranged to focus the pulsed optical beam at a focal point in the IC under test to generate the output signal by absorption of the pulsed optical beam via nonlinear optical interaction at the focal point (The advantages of nonlinear excitation have also been demonstrated for laser scanning fluorescence microscopy; Xu, [p 2578, Col 2, ¶1:1-7]).
However, Nakasuji, a similar field of endeavor of testing or inspecting a property or aspect of a sample such as a wafer, teaches a readout device comprising one or more of a voltmeter, an ammeter, or an ohmmeter configured to measure the output signal (wafer current meter 21-12; Nakasuji, ¶[0313]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a readout device to measure the output signal as taught by Nakasuji to the combined invention of Ross ‘811, Talbot, and Xu. The motivation to do so would be to detect a discharge between the wafer W and objective lens 726 or the discharge leading phenomenon to generate a signal.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ross ‘811 in view of Talbot and further in view of “Loney” (Loney et al., US 20120312957 A1).
20. (Original) The combination of Ross ‘811 and Talbot teaches the IC validation device of claim 16.
Ross ‘811 further teaches wherein the optical beam is a focused optical beam and wherein:
the optical carrier injection imaging system includes:
an optical train arranged to focus the optical beam at a focal point (The beam may be further conditioned using a scan lens 114, a tube lens 112, and an objective lens 110 before the beam is incident on the IC; Ross ‘811; ¶[0063]),
a translation stage configured to move the IC under test (a target device 102 is affixed to a stage, and the stage can be moved in the X and Y directions within the XY plane. Or, a target device 102 is affixed to a stage, and the laser 132 and detector 126 can be moved in the X and Y Ross, ‘811, ¶[0122]) to sequentially place the focal point at coarse locations of a set of coarse locations in or on the IC under test (FIG. 9 is a schematic depicting a node isolation technique 900 using a sequence of observations from a stepped optical microscope as used in Systems for at-speed integrated circuit device observation and analysis of a pre selected set of sites for fast through-silicon in-circuit logic analysis; Ross ‘811, ¶[0126]), and
an electronic beam steering device (The apparatus corresponding to schematic 8B00 comprises an illumination device, a detector 126, an incident beam steering mirror 816, and return beam mirror 818. The incident beam steering mirror 816 can be tipped/rotated so as to steer the incident laser beam to any location on the backside of the target device 102. Similarly, the return beam mirror 818 can be tipped/rotated so as to steer the return beam to the detector; ¶[0125]) configured to,
{ with the focal point at each coarse location, steer the focal point to fine locations of a set of fine locations on or in the IC under test whereby the optical carrier injection system acquires an image tile at the coarse location; and
the electronic processor is programmed to stitch the image tiles together to generate the image of the IC under test}.
Ross ‘811 does not explicitly disclose:
with the focal point at each coarse location, steer the focal point to fine locations of a set of fine locations on or in the IC under test whereby the optical carrier injection system acquires an image tile at the coarse location; and
the electronic processor is programmed to stitch the image tiles together to generate the image of the IC under test.
However, Loney, a similar field of endeavor of scanning and collecting focused images, teaches
with the focal point at each coarse location, steer the focal point to fine locations of a set of fine locations on or in the IC under test whereby the optical carrier injection system acquires an image tile at the coarse location (i) determining a first focus point on the tissue to establish a nominal focus plane by moving the coarse focus stage through the entire z range and monitoring sharpness values; ii) positioning the tissue in x and y to start at a corner of an area of interest; iii) setting the dither fine focus stage to move, wherein the dither focus stage is synchronized to a master clock which also controls the velocity of the xy stage; Loney ¶[0066]); and
the electronic processor is programmed to stitch the image tiles together to generate the image of the IC under test ( a step 720 where the collected image frames are stitched or otherwise combined together to create the mosaic; Loney [0106]; processing of the collected images into a mosaic image of an area of interest requires suitable organization mechanisms and/or image tagging to correctly correlate the multiple rows of frames between the multiple slides that are rotated on the tray 1512. Suitable imaging processing techniques may be used to tag images so as to correlate captured images to the proper slide, since the arced motion of the collection of image tiles may be addressed by known stitching software; Loney, ¶[0155]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include course to fine location steering as taught by Loney to the combined invention of Ross ‘811 and Talbot. The motivation to do so would be to provide further refinement of spatial orientation and improve pixel-level accuracy in imaging the DUT.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include stitching tiles as taught by Loney to the combined invention of Ross ‘811 and Talbot. The motivation to do so would be to obtain a mosaic that appears seamless.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892 Notice of References Cited for full citations.
Chou, et al., US 20210232745 A1, teaches capturing test images of a semiconductor wafer, and would have been relied upon for teaching identifying source from a difference image (¶[0059]).
Singh, Rajhans, et al. (2020) teaches CGAN for synthesizing images in generation in assembly and test manufacturing.
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/CHANDHANA PEDAPATI/Examiner, Art Unit 2669 /CHAN S PARK/Supervisory Patent Examiner, Art Unit 2669
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