Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim (s) 1,4, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai (JP 2017023234A; English Translation; published in 2017) in view of Miyashita et al. (US 6567115 B1) hereinafter Miyashita.
Regarding claim 1 Imai discloses an image pickup unit (Fig.3) comprising: an image pickup substrate (21;Fig.3) having a first principal surface (f0) and a second principal surface (f2) and including an image pickup device (22), a first electrode ( electrodes on f0 ) of the image pickup device being connected to a second electrode ( 23) disposed on the second principal surface (f2); a first wiring plate (30) having a third principal surface (see f3), a fourth principal surface (f4), and a first side surface (see side surface of 30), a third electrode (electrode on bottom of 30) on the third principal surface (f3) being bonded to the second electrode (electrode on f3 is bonded to 23 by 24); and a second wiring plate (40;Fig.3) having a fifth principal surface (f5), a sixth principal surface (f10), and a second side surface (f6), a fifth electrode (41c) on the fifth principal surface (f5) and a sixth electrode (44c) on the second side surface being bonded to a fourth electrode (33c) on the fourth principal surface (f4) of the first wiring plate by using solder ( part 41c is connected to 33c by solder), the sixth electrode (44c) being extended from the fifth electrode (41c), wherein a first conductor block (see 41c in Fig.4) is embedded in the second wiring plate (40;Fig.4), an exposed surface of the first conductor block on the fifth principal surface being the fifth electrode (see exposed surface of 41c being the fifth electrode), an exposed surface of the first conductor block on the second side surface being the sixth electrode (44c on being the 6th electrode as shown in Fig.3).
Imai is silent with respect to and the solder bonding the fourth electrode and the sixth electrode forms a fillet.
Miyashita discloses solder bonding the fourth electrode (26; Fig.6b) and the sixth electrode (26a; Fig.6B) forms a fillet (see 28).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Miyashita to modify the solder connection of Imai in order to ensure a stable mechanical and electrical connection that allows performance of circuit operations.
Regarding claim 4, Imai fails to specifically discloses wherein the fourth electrode is extended to a region not facing the fifth principal surface of the second wiring plate.
Miyashita discloses wherein the fourth electrode (26; Fig.6b) is extended to a region not facing the fifth principal surface of the second wiring plate (surface of 20 facing 20a; Fig.6A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Miyashita to modify the solder connection of Imai in order to ensure a stable mechanical and electrical connection that allows performance of circuit operations.
Regarding claim 9, Imai discloses endoscope comprising an image pickup unit(20;Fig.3), wherein the image pickup unit includes: an image pickup substrate (21) having a first principal surface (bottom surface of 21) and a second principal surface (top surface of 21) and including an image pickup device (22), a first electrode of the image pickup device (electrode on bottom of 21) being connected to a second electrode (23) disposed on the second principal surface; a first wiring plate (30) having a third principal surface (f3), a fourth principal surface (f4), and a first side surface (side surface of 30), a third electrode (electrode on bottom 30) on the third principal surface being bonded to the second electrode (23); and a second wiring plate (40;Fig.3-4) having a fifth principal surface (f5), a sixth principal surface (f10), and a second side surface (f6), a fifth electrode (41c:Fig.3) on the fifth principal surface (f5) and a sixth electrode (44c) on the second side surface being bonded to a fourth electrode (42c;Fig.8) on the fourth principal surface of the first wiring plate by using solder, the sixth electrode being extended from the fifth electrode, wherein a first conductor block (embedded part of 41c in Fig.4) is embedded in the second wiring plate (40), an exposed surface of the first conductor block (see 41c) on the fifth principal surface (f5) being the fifth electrode, an exposed surface of the first conductor block on the second side surface (f6) being the sixth electrode (see 44c),
Imai is silent with respect to and the solder bonding the fourth electrode and the sixth electrode forms a fillet.
Miyashita discloses solder bonding the fourth electrode (26; Fig.6b) and the sixth electrode (26a; Fig.6B) forms a fillet (see 28).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Miyashita to modify the solder connection of Imai in order to ensure a stable mechanical and electrical connection that allows performance of circuit operations.
Claim (s) 2-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imai in view of Miyashita as applied to claim 1 above, and further in view of Xiao (CN 112470057).
Regarding claim 2, Imai fails to specifically discloses: a third wiring plate having a seventh principal surface and a third side surface, the seventh principal surface contacting the sixth principal surface; and a cable bonded to a cable land on the third side surface, wherein the second wiring plate and the third wiring plate are an integrated solid ceramic wiring plate.
Xiao discloses, in Fig.3, a third wiring plate (see top layer of 63 with 65 on the side ) having a seventh principal surface (see top surface of top layer 63) and a third side surface (side surface with 65) , the seventh principal surface contacting the sixth principal surface (top layer of 63 contacting top surface of middle layer of 63); and a cable (17) bonded to a cable land (65) on the third side surface, wherein the second wiring plate and the third wiring plate are an integrated solid ceramic wiring plate (multiple layers of 63 are made of ceramic).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Xiao to modify the second printed circuit board of Imai into multiple printed circuit boards in order to increase rigidity and resistance to thermal expansion during temperature changes.
Regarding claim 3, Imai discloses wherein the solder bonds the fourth electrode (33c) and the fifth electrode (41c).
Allowable Subject Matter
Claims 5-8 and 10 are allowed over prior art of record.The following is an examiner's statement of reasons for allowance:
Regarding claim 5, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein a second conductor block is embedded in the third wiring plate, an exposed surface of the second conductor block on the third side surface being the cable land " in combination with the remaining limitations of the claim 1 and 2.
Regarding claim 6, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the second wiring plate includes a groove in a fifth side surface orthogonal to the first side surface, the groove having a conductor film as a wall surface, the first wiring plate includes an eighth electrode on the fourth principal surface, and solder filling the groove of the second wiring plate bonds the conductor film and the eighth electrode" in combination with the remaining limitations of the claim 1.
Regarding claim 7, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach" wherein the second wiring plate is a multi-layer board in which a plurality of wiring layers are stacked in an optical axis direction, the plurality of wiring layers including two wiring layers in each of which a third conductor block and a fourth conductor block are embedded, an interval between the two wiring layers in each of which the fourth conductor blocks are embedded among the plurality of wiring layers is substantially equal to an interval between two chip electrodes of a chip component, the chip electrodes are bonded to chip lands that are exposed surfaces of the fourth conductor blocks of the two wiring layers, the exposed surfaces being exposed on one side surface of the second wiring plate, the cable is bonded to cable lands that are exposed surfaces of the third conductor blocks of the two wiring layers, the exposed surfaces being exposed on a side surface opposite the one side surface, and an interval between the chip lands is equal to an interval between the cable lands in the optical axis direction" in combination with the remaining limitations of the claim 1.
Regarding claim 8, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach"
the second wiring plate being a multi-layer board in which a plurality of wiring layers are stacked in an optical axis direction, an interval between two wiring layers in each of which a third conductor block and a fourth conductor block are embedded among the plurality of wiring layers being substantially equal to an interval between two chip electrodes of a chip component; the chip component the two chip electrodes of which are bonded to two chip lands that are exposed surfaces of the fourth conductor blocks of the two wiring layers, the exposed surfaces being exposed on the second side surface; and a cable bonded to any of cable lands that are exposed surfaces of the third conductor blocks of the two wiring layers, the exposed surfaces being exposed on a side surface opposite the second side surface, wherein a disposition pitch between the chip lands is equal to a disposition pitch between the cable lands in the optical axis direction" in combination with the remaining limitations of the claim 8.
Regarding claim 10, The prior art of record neither anticipates norrenders obvious the claimed subject matter of the instant application as a whole eithertaken alone or in combination, in particular, prior art of record does not teach
“producing a third substrate having a seventh principal surface and a third side surface and including a cable land on the third side surface; integrating the second substrate and the third substrate by stacking with the sixth principal surface of the second substrate being in contact with the seventh principal surface of the third substrate, and then firing the second substrate and the third substrate to produce a solid wiring plate including a second wiring plate and a third wiring plate; bonding the second electrode of the image pickup substrate to the third electrode of the first wiring plate; bonding the fourth electrode of the first wiring plate to the fifth electrode and the sixth electrode of the second wiring plate by using solder; and bonding a cable to the cable land of the third wiring plate" in combination with the remaining limitations of the claim 10.
Therefore, prior art of record neither anticipates nor renders obvious the instantapplication claimed invention as a whole either taken alone or in combination.
Any comments considered necessary by applicant must be submitted no laterthan the payment of the issue fee and, to avoid processing delays, should preferablyaccompany the issue fee. Such submissions should be clearly labeled "Comments onStatement of Reasons for Allowance."
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/PETE T LEE/Primary Examiner, Art Unit 2848