DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
Receipt is acknowledged of a request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e) and a submission, filed on 02/13/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 8 recite “wherein a dopant concentration in the active region decreases from the first surface toward the second surface of the substrate” is unclear and indefinite if “a dopant concentration” is that of “a first concentration” or that of “a second concentration” or that of total concentration of both “a first concentration” and “a second concentration”. As such the claim is unclear and indefinite.
Response to Arguments
Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over SHIM et al. 20190057898 in view of Wang et al. 20170125473 in view of Liu et al. 20210226008.
PNG
media_image1.png
398
708
media_image1.png
Greyscale
Regarding claim 1, fig. 28 of SHIM discloses a semiconductor device comprising:
a substrate 1 including first and second surfaces opposing each other;
a device isolation layer extending into the substrate from the first surface toward the second surface of the substrate, the device isolation layer defining an active region in the substrate;
a gate electrode on the first surface of the substrate;
a wiring structure on the first surface of the substrate, the wiring structure is electrically connected to the gate electrode and the active region; and
a protective layer 50 covering the wiring structure, the protective layer including an insulating material, wherein a first surface of the device isolation layer is coplanar with the first surface of the substrate, and a second surface of the device isolation layer is not coplanar with the second surface of the substrate,
wherein the active region includes:
a target doped region (source and drain region) between the device isolation layer and the gate electrode, the target doped region including a dopant having a first concentration; and
a path doped region (doped channel region of substrate 1 - the semiconductor substrate 1 may be a silicon substrate having a first conductivity (e.g., p-type conductivity), and may include well regions (not shown)) between the device isolation layer and the gate electrode and extending from the second surface of the substrate to the target doped region, the path doped region including a dopant having a second concentration less than the first concentration (channel doped region is less than source and drain region – for examiner n++ source and drain has higher doping of n type than n type in P-well region comprising the channel),
wherein the target doped region abuts the first surface of the substrate,
the path doped region abuts the second surface of the substrate.
SHIM does not disclose that the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, and does not disclose that the second surface of the device isolation layer is coplanar with the second surface of the substrate.
PNG
media_image2.png
508
481
media_image2.png
Greyscale
However, figs. 2k-L of Wang discloses a semiconductor device comprising:
a substrate including first 104 and second 106’ surfaces opposing each other;
a device isolation layer 112 extending into the substrate from the first surface toward the second surface of the substrate, the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, the device isolation layer defining an active region in the substrate;
a gate electrode on the first surface of the substrate;
wherein a first surface of the device isolation layer is coplanar with the first surface of the substrate, and a second surface of the device isolation layer is coplanar with the second surface of the substrate.
In view of such teaching, it would have been obvious to form a device of SHIM comprising wherein the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate and wherein the second surface of the device isolation layer is coplanar with the second surface of the substrate such as taught by Wang in order to provide complete isolation between the semiconductor devices within the different regions.
Shim and Wang disclose wherein a dopant concentration in the active region decreases from the first surface toward the second surface of the substrate.
PNG
media_image3.png
466
421
media_image3.png
Greyscale
However, fig. 21 of Liu discloses dopant profile of a dopant concentration in an active region decreases from a first surface toward a second surface of the substrate as anneal allows the dopant to drive in after surface implant or diffusion process.
As such it would have been obvious to form a device of Shim and Wang wherein a dopant concentration in the active region decreases from the first surface toward the second surface of the substrate such as taught by Liu in order to drive in the dopant into the substrate to dopant profile which allows for current to flow properly in a normal function device.
PNG
media_image4.png
453
984
media_image4.png
Greyscale
Regarding claim 15, fig. 28 of SHIM discloses a semiconductor device comprising:
a peripheral structure (structure below 100);
a cell structure on the peripheral structure (100 and CS); and
a protective layer covering the cell structure, the protective layer including an insulating material,
wherein the peripheral structure includes:
a substrate including first and second surfaces opposing each other;
a device isolation layer extending into the substrate from the first surface toward the second surface of the substrate, the device isolation layer defining an active region in the substrate;
a gate electrode on the first surface of the substrate; and
a wiring structure (wiring with 50) on the first surface of the substrate, the wiring structure is electrically connected to the gate electrode,
wherein the cell structure includes:
a stack structure disposed on the wiring structure and including a plurality of conductive layers and a plurality of interlayer insulating layers that are alternately stacked; and
a channel structure extending through the stack structure,
wherein a first surface of the device isolation layer is coplanar with the first surface of the substrate, and
a second surface of the device isolation layer is not coplanar with the second surface of the substrate,
wherein the active region includes:
a target doped region between the device isolation layer and the gate electrode, the target doped region including a dopant having a first concentration; and
a path doped region between the device isolation layer and the gate electrode and extending from the second surface of the substrate to the target doped region, the path doped region including a dopant having a second concentration less than the first concentration,
wherein the target doped region abuts the first surface of the substrate,
the path doped region abuts the second surface of the substrate.
SHIM does not disclose that the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, and does not disclose that the second surface of the device isolation layer is coplanar with the second surface of the substrate.
PNG
media_image2.png
508
481
media_image2.png
Greyscale
However, figs. 2k-L of Wang discloses a semiconductor device comprising:
a substrate including first 104 and second 106’ surfaces opposing each other;
a device isolation layer 112 extending into the substrate from the first surface toward the second surface of the substrate, the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, the device isolation layer defining an active region in the substrate;
a gate electrode on the first surface of the substrate;
wherein a first surface of the device isolation layer is coplanar with the first surface of the substrate, and a second surface of the device isolation layer is coplanar with the second surface of the substrate.
In view of such teaching, it would have been obvious to form a device of SHIM comprising wherein the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate and wherein the second surface of the device isolation layer is coplanar with the second surface of the substrate such as taught by Wang in order to provide complete isolation between the semiconductor devices within the different regions.
Regarding claims 2 and 17, fig. 2 of SHIM discloses wherein: the wiring structure includes an interlayer insulating layer 50, a plurality of wiring pads disposed in the interlayer insulating layer and a plurality of wiring contacts disposed in the interlayer insulating layer, wherein the semiconductor device further comprises an active contact disposed on the first surface of the substrate, the active contact electrically connecting the wiring structure to the active region.
Regarding claims 3 and 16, fig. 2 of Wang discloses wherein a width of the first surface of the device isolation layer in a horizontal direction is greater than a width of the second surface of the device isolation layer in the horizontal direction. The resulting structure would have been one meeting the claimed limitations.
Regarding claim 4, SHIM discloses wherein the semiconductor device comprises a NAND FLASH memory device.
Regarding claims 5 and 19, fig. 28 of SHIM discloses wherein: the active region includes:
a first region including a well region (region of substrate 1 between 11 and 1 is a well region);
a second region (source region) abuts the first surface of the substrate and is disposed between the device isolation layer and the gate electrode;
a third region is between the second region and the gate electrode; and
a fourth region surrounds the third region and is disposed between the first region and the third region,
wherein the second region and the third region are doped with a dopant having a same conductivity type,
the first region and the fourth region are doped with a dopant having the same conductivity type,
the first region and the second region are doped with dopants having different conductivity types from each other, and
a third doping concentration (depleted region at the boundary between 1 and 3) of the third region is lower than a second doping concentration of the second region.
Regarding claim 7, Shim does not disclose wherein the first to fourth regions are doped by a doping process performed through the second surface of the substrate.
“[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.”
Regarding claim 18, fig. 28 of SHIM discloses wherein the protective layer includes a portion surrounding an upper surface and a lateral side surface of the wiring structure.
Claims 8 -14 are rejected under 35 U.S.C. 103 as being unpatentable over SHIM and Wang and Liu in view of Dennen US 6555872
PNG
media_image5.png
469
1010
media_image5.png
Greyscale
Regarding claim 8, fig. 28 of SHIM discloses a semiconductor device comprising:
a substrate 1 including first and second surfaces opposing each other;
a device isolation layer extending into the substrate from the first surface toward the second surface of the substrate, the device isolation layer defining an active region in the substrate;
a gate electrode structure disposed on but not within the substrate, the gate electrode structure extending in a first horizontal direction (D1 across the page);
a protective layer (as labeled by examiner above) covering the wiring structure, the protective layer including an insulating material, wherein the wiring structure includes a bit line BL;
the bit line BL extending in a second horizontal direction (into the page) orthogonal to the first horizontal direction,
a first surface of the device isolation layer is coplanar with the first surface of the substrate, and a second surface of the device isolation layer is not coplanar with the second surface of the substrate,
wherein the active region includes:
a target doped region (source and drain region) between the device isolation layer and the gate electrode, the target doped region including a dopant having a first concentration; and
a path doped region (doped channel region of substrate 1 - the semiconductor substrate 1 may be a silicon substrate having a first conductivity (e.g., p-type conductivity), and may include well regions (not shown)) between the device isolation layer and the gate electrode and extending from the second surface of the substrate to the target doped region, the path doped region including a dopant having a second concentration less than the first concentration (channel doped region is less than source and drain region – for examiner n++ source and drain has higher doping of n type than n type in P-well region comprising the channel),
wherein the target doped region abuts the first surface of the substrate,
the path doped region abuts the second surface of the substrate.
SHIM does not disclose that the target doped region and the path doped region are formed by implanting the dopant through the second surface of the substrate, and the substrate is thinned by grinding the second surface of the substrate to expose the second surface of the device isolation layer.
SHIM does not disclose that the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, and does not disclose that the second surface of the device isolation layer is coplanar with the second surface of the substrate.
PNG
media_image2.png
508
481
media_image2.png
Greyscale
However, figs. 2k-L of Wang discloses a semiconductor device comprising:
a substrate including first 104 and second 106’ surfaces opposing each other;
a device isolation layer 112 extending into the substrate from the first surface toward the second surface of the substrate, the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, the device isolation layer defining an active region in the substrate;
a gate electrode on the first surface of the substrate;
wherein a first surface of the device isolation layer is coplanar with the first surface of the substrate, and a second surface of the device isolation layer is coplanar with the second surface of the substrate.
In view of such teaching, it would have been obvious to form a device of SHIM comprising wherein the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate and wherein the second surface of the device isolation layer is coplanar with the second surface of the substrate such as taught by Wang in order to provide complete isolation between the semiconductor devices within the different regions.
Shim and Wang disclose wherein a dopant concentration in the active region decreases from the first surface toward the second surface of the substrate.
PNG
media_image3.png
466
421
media_image3.png
Greyscale
However, fig. 21 of Liu discloses dopant profile of a dopant concentration in an active region decreases from a first surface toward a second surface of the substrate as anneal allows the dopant to drive in after surface implant or diffusion process.
As such it would have been obvious to form a device of Shim and Wang wherein a dopant concentration in the active region decreases from the first surface toward the second surface of the substrate such as taught by Liu in order to drive in the dopant into the substrate to dopant profile which allows for current to flow properly in a normal function device.
SHIM and Wang and Liu do not disclose that the gate electrode structure disposed within the substrate.
PNG
media_image6.png
470
680
media_image6.png
Greyscale
However, fig. 9 of Dennen discloses a MOSFET comprising a trench gate wherein the gate electrode structure disposed within the substrate in order to have a larger effective channel length.
In view of such teaching, it would have been obvious to form a device of SHIM and Wang and Liu comprising wherein the gate electrode structure disposed within the substrate such as taught by Dennen in order to have a larger effective channel length.
Regarding claim 9, fig. 28 of SHIM discloses wherein the wiring structure includes an interlayer insulating layer 50 and a contact structure disposed in the interlayer insulating layer.
Regarding claim 10, fig. 28 of Shim discloses wherein a width of the first surface of the device isolation layer in a horizontal direction is greater than a width of the second surface of the device isolation layer in the horizontal direction. The resulting structure would have been one meeting the claimed limitations.
Regarding claim 11, fig. 28 of SHIM (as labeled by examiner above) discloses wherein the protective layer includes a portion surrounding an upper surface and a lateral side surface of the wiring structure.
PNG
media_image7.png
579
955
media_image7.png
Greyscale
Regarding claim 12, fig. 28 of Shim (as labeled by examiner above) discloses wherein: the substrate includes a cell region; the active region includes a cell active region; the device isolation layer includes a cell device isolation layer disposed in the cell region; the cell device isolation layer defining the cell active region; the gate electrode structure includes a cell gate electrode disposed in the cell region; the wiring structure includes a cell wiring structure disposed in the cell region and further includes a cell capacitor structure disposed on the cell wiring structure, the cell capacitor structure is electrically connected to the cell active region in the substrate; and the protective layer is disposed on the cell capacitor structure.
Regarding claim 13, fig. 28 of SHIM discloses wherein: the substrate includes a peripheral region (far left region of fig. 28); the active region includes a peripheral active region; the device isolation layer includes a peripheral device isolation layer disposed in the peripheral region, the peripheral device isolation layer defining the peripheral active region; the gate electrode structure includes a peripheral gate electrode disposed in the peripheral region; the wiring structure includes a peripheral wiring structure disposed in the peripheral region; and the protective layer is disposed on the peripheral wiring structure.
PNG
media_image8.png
413
1184
media_image8.png
Greyscale
Regarding claim 14, fig. 28 of (SHIM as labeled by examiner above) discloses wherein: the active region includes:
a first region including a well region (region of substrate 1 between 11 and 11 is a well region);
a second region (source region) abuts the first surface of the substrate and is disposed between the device isolation layer and the gate electrode;
a third region is between the second region and the gate electrode; and
a fourth region surrounds the third region and is disposed between the first region and the third region,
wherein the second region and the third region are doped with a dopant having a same conductivity type,
the first region and the fourth region are doped with a dopant having the same conductivity type,
the first region and the second region are doped with dopants having different conductivity types from each other, and
a third doping concentration (depleted region at the boundary between 1 and 3) of the third region is lower than a second doping concentration of the second region.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over SHIM and Wang in view of Chao et al. 20200303545.
Regarding claims 6 and 20, SHIM and Wang do not disclose of wherein: the third region includes a lightly doped drain (LDD) region; and the fourth region includes an LDD halo well structure including a halo region.
However, par [0003] of Chao discloses of a MOSFET structure includes a lightly doped drain (LDD) region or a halo implantation region to improve the hot-carrier effect (HCE).
In view of such teaching, it would have been obvious to form a device of SHIM and Wang further comprising wherein: the third region includes a lightly doped drain (LDD) region; and the fourth region includes an LDD halo well structure including a halo region such as taught by Chao in order to improve the hot-carrier effect (HCE).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis A. Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
Prosecution Insights