DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on Majhi et al. 20090085129 applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7 and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over SHIM et al. 20190057898 in view of Wang et al. 20170125473 in view of Majhi et al. 20090085129 in view of Liu et al. 20210226008.
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Regarding claim 1, fig. 28 of SHIM 1. (Currently Amended) A semiconductor device comprising:
a substrate 1 including first and second surfaces opposing each other;
a device isolation layer 11 extending into the substrate from the first surface toward the second surface of the substrate, the device isolation layer defining an active region in the substrate;
a gate electrode on the first surface of the substrate;
a wiring structure on the first surface of the substrate, the wiring structure is electrically connected to the gate electrode and the active region; and
a protective layer 50covering the wiring structure, the protective layer including an insulating material,
wherein a first surface of the device isolation layer is coplanar with the first surface of the substrate, and the second surface of the device isolation layer is not coplanar with the second surface of the substrate.
Shim does not disclose that the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, wherein the second surface of the device isolation layer is coplanar with the second surface of the substrate,
wherein the active region includes:
a target doped region between the device isolation layer and the gate electrode, the target doped region including a dopant having a first concentration; and
a path doped region between the device isolation layer and the gate electrode and extending from the second surface of the substrate to the target doped region, the path doped region including the dopant having a second concentration less than the first concentration,
wherein the target doped region and the path doped region include a same type of dopant,
wherein a concentration of the same type of dopant in a portion of the active region including the target doped region and the path doped region decreases from the target doped region toward the second surface of the substrate through the path doped region,
wherein the target doped region abuts the first surface of the substrate, the path doped region abuts the second surface of the substrate.
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However, figs. 2k-L of Wang discloses a semiconductor device comprising:
a substrate including first 104 and second 106’ surfaces opposing each other;
a device isolation layer 112 extending into the substrate from the first surface toward the second surface of the substrate, the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, the device isolation layer defining an active region in the substrate;
a gate electrode on the first surface of the substrate;
wherein a first surface of the device isolation layer is coplanar with the first surface of the substrate, and a second surface of the device isolation layer is coplanar with the second surface of the substrate.
In view of such teaching, it would have been obvious to form a device of SHIM comprising wherein the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, wherein the second surface of the device isolation layer is coplanar with the second surface of the substrate such as taught by Wang in order to provide complete isolation between the semiconductor devices within the different regions.
Shim and Wang disclose wherein the active region includes:
a target doped region between the device isolation layer and the gate electrode, the target doped region including a dopant having a first concentration; and
a path doped region between the device isolation layer and the gate electrode and extending from the second surface of the substrate to the target doped region, the path doped region including the dopant having a second concentration less than the first concentration,
wherein the target doped region and the path doped region include a same type of dopant,
wherein a concentration of the same type of dopant in a portion of the active region including the target doped region and the path doped region decreases from the target doped region toward the second surface of the substrate through the path doped region,
wherein the target doped region abuts the first surface of the substrate, the path doped region abuts the second surface of the substrate.
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However, figs. 1-2 of Majhi disclose wherein a semiconductor device comprising:
a substrate 100 including first and second surfaces opposing each other;
a gate electrode on the first surface of the substrate;
an active region;
wherein the active region includes:
a target doped region 108 adjacent the gate electrode, the target doped region including a dopant having a first concentration (sum of LDD implant in fig. 1 and Halo implant in fig. 2 concentration); and
a path doped region 110 below the target doped region and the gate electrode and extending from the second surface of the substrate to the target doped region 108, the path doped region including the dopant having a second concentration (that of Halo implant only) less than the first concentration (sum of LDD implant in fig. 1 and Halo implant in fig. 2 concentration),
wherein the target doped region 108 and the path doped region 110 include a same type of dopant (that type of Halo implant dopant since fig. 2 shows that Halo implanted through region 108 to get to region 110),
wherein the target doped region abuts the first surface of the substrate, the path doped region abuts the second surface of the substrate.
In view of such teaching, it would have been obvious to form a device of Shim and Wang further comprising wherein the active region includes: a target doped region 108 adjacent the gate electrode, the target doped region including a dopant having a first concentration; and a path doped region below the target doped region and the gate electrode and extending from the second surface of the substrate to the target doped region 108, the path doped region including the dopant having a second concentration less than the first concentration, wherein the target doped region 108 and the path doped region include a same type of dopant, wherein the target doped region abuts the first surface of the substrate, the path doped region abuts the second surface of the substrate such as taught by Majhi help in order to control short channel effects.
Shim and Wang and Majhi do not explicitly discloses wherein a concentration of the same type of dopant in a portion of the active region including the target doped region and the path doped region decreases from the target doped region toward the second surface of the substrate through the path doped region.
However, note that par[011] of Majhi discloses of downstream annealing processes, such as the annealing process that activates the source and drain regions.
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However, fig. 21 of Liu discloses dopant profile of a dopant concentration in an active region decreases from a first surface toward a second surface of the substrate as anneal allows the dopant to drive in after surface implant or diffusion process.
As such it would have been obvious to form a device of Shim and Wang and Majhi discloses wherein a concentration of the same type of dopant in a portion of the active region including the target doped region and the path doped region decreases from the target doped region toward the second surface of the substrate through the path doped region such as taught by Liu in order to drive in the dopant into the substrate to dopant profile which allows for current to flow properly in a normal function device.
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Regarding claim 15, fig. 28 of SHIM discloses a semiconductor device comprising:
a peripheral structure (ps - structure below 100);
a cell structure on the peripheral structure (100 and CS); and
a protective layer covering the cell structure, the protective layer including an insulating material,
wherein the peripheral structure includes:
a substrate including first and second surfaces opposing each other;
a device isolation layer 11 extending into the substrate from the first surface toward the second surface of the substrate, the device isolation layer defining an active region in the substrate;
a gate electrode on the first surface of the substrate; and
a wiring structure (wiring with 50) on the first surface of the substrate, the wiring structure is electrically connected to the gate electrode,
wherein the cell structure includes:
a stack structure disposed on the wiring structure and including a plurality of conductive layers and a plurality of interlayer insulating layers that are alternately stacked; and
a channel structure VS extending through the stack structure,
wherein a first surface of the device isolation layer is coplanar with the first surface of the substrate, and
a second surface of the device isolation layer is not coplanar with the second surface of the substrate,
wherein the active region includes:
a target doped region between the device isolation layer and the gate electrode, the target doped region including a dopant having a first concentration; and
a path doped region between the device isolation layer and the gate electrode and extending from the second surface of the substrate to the target doped region, the path doped region including a dopant having a second concentration less than the first concentration,
wherein the target doped region abuts the first surface of the substrate,
the path doped region abuts the second surface of the substrate.
Shim does not disclose that the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, wherein the second surface of the device isolation layer is coplanar with the second surface of the substrate,
wherein the active region includes:
a target doped region between the device isolation layer and the gate electrode, the target doped region including a dopant having a first concentration; and
a path doped region between the device isolation layer and the gate electrode and extending from the second surface of the substrate to the target doped region, the path doped region including the dopant having a second concentration less than the first concentration,
wherein the target doped region and the path doped region include a same type of dopant,
wherein a concentration of the same type of dopant in a portion of the active region including the target doped region and the path doped region decreases from the target doped region toward the second surface of the substrate through the path doped region,
wherein the target doped region abuts the first surface of the substrate, the path doped region abuts the second surface of the substrate.
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However, figs. 2k-L of Wang discloses a semiconductor device comprising:
a substrate including first 104 and second 106’ surfaces opposing each other;
a device isolation layer 112 extending into the substrate from the first surface toward the second surface of the substrate, the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, the device isolation layer defining an active region in the substrate;
a gate electrode on the first surface of the substrate;
wherein a first surface of the device isolation layer is coplanar with the first surface of the substrate, and a second surface of the device isolation layer is coplanar with the second surface of the substrate.
In view of such teaching, it would have been obvious to form a device of SHIM comprising wherein the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, wherein the second surface of the device isolation layer is coplanar with the second surface of the substrate such as taught by Wang in order to provide complete isolation between the semiconductor devices within the different regions.
Shim and Wang disclose wherein the active region includes:
a target doped region between the device isolation layer and the gate electrode, the target doped region including a dopant having a first concentration; and
a path doped region between the device isolation layer and the gate electrode and extending from the second surface of the substrate to the target doped region, the path doped region including the dopant having a second concentration less than the first concentration,
wherein the target doped region and the path doped region include a same type of dopant,
wherein a concentration of the same type of dopant in a portion of the active region including the target doped region and the path doped region decreases from the target doped region toward the second surface of the substrate through the path doped region,
wherein the target doped region abuts the first surface of the substrate, the path doped region abuts the second surface of the substrate.
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However, figs. 1-2 of Majhi disclose wherein a semiconductor device comprising:
a substrate 100 including first and second surfaces opposing each other;
a gate electrode on the first surface of the substrate;
an active region;
wherein the active region includes:
a target doped region 108 adjacent the gate electrode, the target doped region including a dopant having a first concentration (sum of LDD implant in fig. 1 and Halo implant in fig. 2 concentration); and
a path doped region 110 below the target doped region and the gate electrode and extending from the second surface of the substrate to the target doped region 108, the path doped region including the dopant having a second concentration (that of Halo implant only) less than the first concentration (sum of LDD implant in fig. 1 and Halo implant in fig. 2 concentration),
wherein the target doped region 108 and the path doped region 110 include a same type of dopant (that type of Halo implant dopant since fig. 2 shows that Halo implanted through region 108 to get to region 110),
wherein the target doped region abuts the first surface of the substrate, the path doped region abuts the second surface of the substrate.
In view of such teaching, it would have been obvious to form a device of Shim and Wang further comprising wherein the active region includes: a target doped region 108 adjacent the gate electrode, the target doped region including a dopant having a first concentration; and a path doped region below the target doped region and the gate electrode and extending from the second surface of the substrate to the target doped region 108, the path doped region including the dopant having a second concentration less than the first concentration, wherein the target doped region 108 and the path doped region include a same type of dopant, wherein the target doped region abuts the first surface of the substrate, the path doped region abuts the second surface of the substrate such as taught by Majhi help in order to control short channel effects.
Shim and Wang and Majhi do not explicitly discloses wherein a concentration of the same type of dopant in a portion of the active region including the target doped region and the path doped region decreases from the target doped region toward the second surface of the substrate through the path doped region.
However, note that par[011] of Majhi discloses of downstream annealing processes, such as the annealing process that activates the source and drain regions.
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However, fig. 21 of Liu discloses dopant profile of a dopant concentration in an active region decreases from a first surface toward a second surface of the substrate as anneal allows the dopant to drive in after surface implant or diffusion process.
As such it would have been obvious to form a device of Shim and Wang and Majhi discloses wherein a concentration of the same type of dopant in a portion of the active region including the target doped region and the path doped region decreases from the target doped region toward the second surface of the substrate through the path doped region such as taught by Liu in order to drive in the dopant into the substrate to dopant profile which allows for current to flow properly in a normal function device.
Regarding claims 2 and 17, fig. 2 of SHIM discloses wherein: the wiring structure includes an interlayer insulating layer 50, a plurality of wiring pads disposed in the interlayer insulating layer and a plurality of wiring contacts disposed in the interlayer insulating layer, wherein the semiconductor device further comprises an active contact disposed on the first surface of the substrate, the active contact electrically connecting the wiring structure to the active region.
Regarding claims 3 and 16, fig. 2 of Wang discloses wherein a width of the first surface of the device isolation layer in a horizontal direction is greater than a width of the second surface of the device isolation layer in the horizontal direction. The resulting structure would have been one meeting the claimed limitations.
Regarding claim 4, SHIM discloses wherein the semiconductor device comprises a NAND FLASH memory device.
Regarding claims 5 and 19, fig. 28 of SHIM discloses wherein: the active region includes:
a first region including a well region (region of substrate 1 between 11 and 1 is a well region);
a second region (source region) abuts the first surface of the substrate and is disposed between the device isolation layer and the gate electrode;
a third region is between the second region and the gate electrode; and
a fourth region surrounds the third region and is disposed between the first region and the third region,
wherein the second region and the third region are doped with a dopant having a same conductivity type,
the first region and the fourth region are doped with a dopant having the same conductivity type,
the first region and the second region are doped with dopants having different conductivity types from each other, and
a third doping concentration (depleted region at the boundary between 1 and 3) of the third region is lower than a second doping concentration of the second region.
Regarding claim 7, Shim does not disclose wherein the first to fourth include dopants introduced through the second surface of the substrate.
Note introduced through the second surface of the substrate is a product-by-process limitation.
“[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.”
Regarding claim 18, fig. 28 of SHIM discloses wherein the protective layer includes a portion surrounding an upper surface and a lateral side surface of the wiring structure.
Claims 8 -14 are rejected under 35 U.S.C. 103 as being unpatentable over SHIM and Wang and Majhi and Liu in view of Dennen US 6555872.
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Regarding claim 8, fig. 28 of SHIM discloses a semiconductor device comprising:
a substrate 1 including first and second surfaces opposing each other;
a device isolation layer extending into the substrate from the first surface toward the second surface of the substrate, the device isolation layer defining an active region in the substrate;
a gate electrode structure disposed on but not within the substrate, the gate electrode structure extending in a first horizontal direction (D1 across the page);
a protective layer (as labeled by examiner above) covering the wiring structure, the protective layer including an insulating material, wherein the wiring structure includes a bit line BL;
the bit line BL extending in a second horizontal direction (into the page) orthogonal to the first horizontal direction,
a first surface of the device isolation layer is coplanar with the first surface of the substrate, and a second surface of the device isolation layer is not coplanar with the second surface of the substrate,
Shim does not disclose that the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, wherein the second surface of the device isolation layer is coplanar with the second surface of the substrate,
wherein the active region includes:
a target doped region between the device isolation layer and the gate electrode, the target doped region including a dopant having a first concentration; and
a path doped region between the device isolation layer and the gate electrode and extending from the second surface of the substrate to the target doped region, the path doped region including the dopant having a second concentration less than the first concentration,
wherein the target doped region and the path doped region include a same type of dopant,
wherein a concentration of the same type of dopant in a portion of the active region including the target doped region and the path doped region decreases from the target doped region toward the second surface of the substrate through the path doped region,
wherein the target doped region abuts the first surface of the substrate, the path doped region abuts the second surface of the substrate.
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However, figs. 2k-L of Wang discloses a semiconductor device comprising:
a substrate including first 104 and second 106’ surfaces opposing each other;
a device isolation layer 112 extending into the substrate from the first surface toward the second surface of the substrate, the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, the device isolation layer defining an active region in the substrate;
a gate electrode on the first surface of the substrate;
wherein a first surface of the device isolation layer is coplanar with the first surface of the substrate, and a second surface of the device isolation layer is coplanar with the second surface of the substrate.
In view of such teaching, it would have been obvious to form a device of SHIM comprising wherein the substrate having a thickness whereby a second surface of the device isolation layer is exposed at the second surface of the substrate, wherein the second surface of the device isolation layer is coplanar with the second surface of the substrate such as taught by Wang in order to provide complete isolation between the semiconductor devices within the different regions.
Shim and Wang disclose wherein the active region includes:
a target doped region between the device isolation layer and the gate electrode, the target doped region including a dopant having a first concentration; and
a path doped region between the device isolation layer and the gate electrode and extending from the second surface of the substrate to the target doped region, the path doped region including the dopant having a second concentration less than the first concentration,
wherein the target doped region and the path doped region include a same type of dopant,
wherein a concentration of the same type of dopant in a portion of the active region including the target doped region and the path doped region decreases from the target doped region toward the second surface of the substrate through the path doped region,
wherein the target doped region abuts the first surface of the substrate, the path doped region abuts the second surface of the substrate.
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However, figs. 1-2 of Majhi disclose wherein a semiconductor device comprising:
a substrate 100 including first and second surfaces opposing each other;
a gate electrode on the first surface of the substrate;
an active region;
wherein the active region includes:
a target doped region 108 adjacent the gate electrode, the target doped region including a dopant having a first concentration (sum of LDD implant in fig. 1 and Halo implant in fig. 2 concentration); and
a path doped region 110 below the target doped region and the gate electrode and extending from the second surface of the substrate to the target doped region 108, the path doped region including the dopant having a second concentration (that of Halo implant only) less than the first concentration (sum of LDD implant in fig. 1 and Halo implant in fig. 2 concentration),
wherein the target doped region 108 and the path doped region 110 include a same type of dopant (that type of Halo implant dopant since fig. 2 shows that Halo implanted through region 108 to get to region 110),
wherein the target doped region abuts the first surface of the substrate, the path doped region abuts the second surface of the substrate.
In view of such teaching, it would have been obvious to form a device of Shim and Wang further comprising wherein the active region includes: a target doped region 108 adjacent the gate electrode, the target doped region including a dopant having a first concentration; and a path doped region below the target doped region and the gate electrode and extending from the second surface of the substrate to the target doped region 108, the path doped region including the dopant having a second concentration less than the first concentration, wherein the target doped region 108 and the path doped region include a same type of dopant, wherein the target doped region abuts the first surface of the substrate, the path doped region abuts the second surface of the substrate such as taught by Majhi help in order to control short channel effects.
Shim and Wang and Majhi do not explicitly discloses wherein a concentration of the same type of dopant in a portion of the active region including the target doped region and the path doped region decreases from the target doped region toward the second surface of the substrate through the path doped region.
However, note that par[011] of Majhi discloses of downstream annealing processes, such as the annealing process that activates the source and drain regions.
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However, fig. 21 of Liu discloses dopant profile of a dopant concentration in an active region decreases from a first surface toward a second surface of the substrate as anneal allows the dopant to drive in after surface implant or diffusion process.
As such it would have been obvious to form a device of Shim and Wang and Majhi discloses wherein a concentration of the same type of dopant in a portion of the active region including the target doped region and the path doped region decreases from the target doped region toward the second surface of the substrate through the path doped region such as taught by Liu in order to drive in the dopant into the substrate to dopant profile which allows for current to flow properly in a normal function device.
SHIM and Wang and Majhi and Liu do not disclose that the gate electrode structure disposed within the substrate.
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However, fig. 9 of Dennen discloses a MOSFET comprising a trench gate wherein the gate electrode structure disposed within the substrate in order to have a larger effective channel length.
In view of such teaching, it would have been obvious to form a device of SHIM and Wang and Majhi and Liu comprising wherein the gate electrode structure disposed within the substrate such as taught by Dennen in order to have a larger effective channel length.
Regarding claim 9, fig. 28 of SHIM discloses wherein the wiring structure includes an interlayer insulating layer 50 and a contact structure disposed in the interlayer insulating layer.
Regarding claim 10, fig. 28 of Shim discloses wherein a width of the first surface of the device isolation layer in a horizontal direction is greater than a width of the second surface of the device isolation layer in the horizontal direction. The resulting structure would have been one meeting the claimed limitations.
Regarding claim 11, fig. 28 of SHIM (as labeled by examiner above) discloses wherein the protective layer includes a portion surrounding an upper surface and a lateral side surface of the wiring structure.
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Regarding claim 12, fig. 28 of Shim (as labeled by examiner above) discloses wherein: the substrate includes a cell region; the active region includes a cell active region; the device isolation layer includes a cell device isolation layer disposed in the cell region; the cell device isolation layer defining the cell active region; the gate electrode structure includes a cell gate electrode disposed in the cell region; the wiring structure includes a cell wiring structure disposed in the cell region and further includes a cell capacitor structure disposed on the cell wiring structure, the cell capacitor structure is electrically connected to the cell active region in the substrate; and the protective layer is disposed on the cell capacitor structure.
Regarding claim 13, fig. 28 of SHIM discloses wherein: the substrate includes a peripheral region (far left region of fig. 28); the active region includes a peripheral active region; the device isolation layer includes a peripheral device isolation layer disposed in the peripheral region, the peripheral device isolation layer defining the peripheral active region; the gate electrode structure includes a peripheral gate electrode disposed in the peripheral region; the wiring structure includes a peripheral wiring structure disposed in the peripheral region; and the protective layer is disposed on the peripheral wiring structure.
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Regarding claim 14, fig. 28 of (SHIM as labeled by examiner above) discloses wherein: the active region includes:
a first region including a well region (region of substrate 1 between 11 and 11 is a well region);
a second region (source region) abuts the first surface of the substrate and is disposed between the device isolation layer and the gate electrode;
a third region is between the second region and the gate electrode; and
a fourth region surrounds the third region and is disposed between the first region and the third region,
wherein the second region and the third region are doped with a dopant having a same conductivity type,
the first region and the fourth region are doped with a dopant having the same conductivity type,
the first region and the second region are doped with dopants having different conductivity types from each other, and
a third doping concentration (depleted region at the boundary between 1 and 3) of the third region is lower than a second doping concentration of the second region.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shim and Wang and Majhi and Liu in view of Chao et al. 20200303545.
Regarding claims 6 and 20, Shim and Wang and Majhi and Liu do not disclose of wherein: the third region includes a lightly doped drain (LDD) region; and the fourth region includes an LDD halo well structure including a halo region.
However, par [0003] of Chao discloses of a MOSFET structure includes a lightly doped drain (LDD) region or a halo implantation region to improve the hot-carrier effect (HCE).
In view of such teaching, it would have been obvious to form a device of Shim and Wang and Majhi and Liu further comprising wherein: the third region includes a lightly doped drain (LDD) region; and the fourth region includes an LDD halo well structure including a halo region such as taught by Chao in order to improve the hot-carrier effect (HCE).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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