DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Responsive to communications on 09/20/2024
Claims 1-20 pending
Claims 1-20 rejected
Priority
Application data sheet received on 05/19/2023 claims earliest priority to foreign application CN202210077584.7 filing date 01/24/2022. Priority document electronically received on 06/30/2023. Application data sheet accepted by the examiner.
Information Disclosure Statement
Information disclosure statement received on 09/20/2024 accepted and reviewed by the examiner. All references considered.
Drawings
Drawings received on 05/19/2023 accepted by the examiner.
Specification
Abstract received on 05/19/2023 contains less than 150 words and contains no legal or implied phraseology. Abstract is accepted by the examiner.
Specification received on 05/19/2023 accepted by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, an abstract idea, which has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception.
Claim 1:
Step 1: Is the claimed invention one of the four statutory categories? :
YES. The claim recites A method of a quantum circuit simulation which is a process.
Step 2A Prong 1, inquiry "Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?":
YES. Claim 1 recites: determining at least a first input parameter of the primitive function, the quantum circuit simulation including a plurality of first tensors respectively for the first input parameter;
A first input parameter of a primitive function is an input to a mathematic function. For example, x is a first input parameter of f(x). A tensor is a mathematic representation. For example, a value, array/vector, matrix etc. A plurality of first tensors corresponding to the first input parameter is mathematic values corresponding to the input parameter. For example, x= 1, 2, 3, and 4 are tensors associated with the input parameter of x. As outlined above, the action of the claim is to determine an input parameter of the primitive function. This is an observation of the primitive function and an evaluation of the parameter that the user would like to be parameterized. The MPEP 2106.04(a)(2)(III) states “Accordingly, the "mental processes" abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. “ Therefore this claim recites a mental process.
converting the primitive function to a target function according to the primitive function and at least the first input parameter, the target function including a converted first input parameter corresponding to the first input parameter, the plurality of first tensors being spliced into a second tensor for the converted first input parameter in the quantum circuit simulation
Converting the primitive to a target function is the conversion of the mathematic function f(x) which takes in the first input parameter/tensors into a mathematic function f’(x’) which takes in a one higher level of dimensionality for batch processing. The plurality of first tensors being spliced into a second tensor is the combination of the input tensors of f(x). for example, for f(x) to take in 1, 2, 3, 4 . f’(x’) would take in [1,2,3,4] . As outlined above, this conversion is an evaluation performed by a user to convert the function of f(x) into f’(x). MPEP 2106.04(a)(2)(III) states “Accordingly, the "mental processes" abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. “ Therefore the claim recites an abstract idea.
obtaining an execution result of the target function according to at least the second tensor for the converted first input parameter;
An execution result of a function is the result of the mathematic function. For example, for a function f(x) = 2x, the execution of x=1 would be f(1) = 2. The execution of the target function would be represented as f([1, 2, 3, 4]) = [2, 4, 6, 8]. The word “obtain an execution result” is a textual replacement for “calculate the answer of the target function with the given inputs. “ MPEP 2106.04(a)(2)(I)(C) states “A claim that recites a mathematical calculation, when the claim is given its broadest reasonable interpretation in light of the specification, will be considered as falling within the "mathematical concepts" grouping. A mathematical calculation is a mathematical operation (such as multiplication) or an act of calculating using mathematical methods to determine a variable or number, e.g., performing an arithmetic operation such as exponentiation. There is no particular word or set of words that indicates a claim recites a mathematical calculation. That is, a claim does not have to recite the word "calculating" in order to be considered a mathematical calculation. For example, a step of "determining" a variable or number using mathematical methods or "performing" a mathematical operation may also be considered mathematical calculations when the broadest reasonable interpretation of the claim in light of the specification encompasses a mathematical calculation.” Therefore this claim encompasses a mathematical calculation.
and performing the quantum circuit simulation based on the execution result of the target function.
Performing the simulation based on the execution results is to use the values determined by the execution in performing a quantum circuit simulation. For example, where parameter weights are inputs to the target function, the execution result may provide an output which minimizes a loss function. Performing the simulation would be then performing the quantum circuit using the weights which lead to the smallest output. The quantum circuit simulation is made up of matrix calculations which act on qubits following a path. The MPEP 2106.04(a)(2)(III)(B) states “If a claim recites a limitation that can practically be performed in the human mind, with or without the use of a physical aid such as pen and paper, the limitation falls within the mental processes grouping, and the claim recites an abstract idea.” Therefore this claim recites a mental process as it encompasses an individual tracing through a quantum circuit and calculating vector and matrix calculations which can be performed by an individual with a pen and paper.
Step 2A Prong 2, Does the claim recite additional elements that integrate the judicial exception into a practical application?
NO. Claim 1 additionally recites , comprising: receiving a primitive function for the quantum circuit simulation;
This claim limitation pertains to receiving a primitive function (a piece of data). The MPEP 2106.05(f)(2) states “Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more.” Therefore this claim limitation does not integrate a judicial exception into a practical application or provide significantly more.
Step 2B, does the claim recites additional elements that amount to significantly more than the judicial exception.
NO. As stated in Step 2A Prong 2, the additional element does not integrate a judicial exception into a practical application or provide significantly more.
Based on the above facts, the office concludes that claim 1 is not eligible under 35 USC 101.
Claim 2:
The method according to claim 1, wherein the obtaining the execution result comprises:
processing the converted first input parameter through a vector parallelism, to obtain the execution result.
Vector parallelism is running multiple vector calculations in parallel to execute the batched second tensor. As stated above, this is a further recitation of the mathematic execution performed in claim 1, and therefore claim 2 further recites an abstract idea.
Claim 3:The method according to claim 2, wherein the processing the converted first input parameter comprises:
performing the vector parallelism on the second tensor for the converted first input parameter by using a vector instruction set, the vector instruction set comprising one or more executable instructions for a processor to perform the vector parallelism on the second tensor for the converted first input parameter.
The processing step and vector parallelism was determined to be a mental process as outlined in claim 1. The vector instruction set is a set of instructions which informs the hardware used, such as a CPU, to complete the multiple batched computations at once. This claim limitation requires that the parallelism batched computations be performed by a computer with instructions. The MPEP 2106.05(f)(2) states “Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more.” Therefore this claim limitation does not integrate a judicial exception into a practical application or provide significantly more.
Claim 4:
The method according to claim 3, wherein the primitive function is configured to process an input wave function of a target quantum circuit in the quantum circuit simulation,
An input wave function is the initial state received into the function. For example F(input wave) = .. .
As stated above, the input wave function is a piece of received data using a normal computing device. Furthermore, one ordinarily skilled in the art could perform the above mental processes with a pen and paper using different input wave functions (i.e.: a state of 0 and a state of 1). Therefore, this claim is a further recitation of the primitive function which is data received by an ordinary computing device and does not integrate the above judicial exceptions.
and the performing the vector parallelism on the second tensor comprises:
splicing a plurality of input wave functions of the target quantum circuit into the second tensor for the converted first input parameter;
The steps above perform the function of claims 1-3, with the difference being that the input is a wave function. As outlined above, splicing the input into the second tensor, where the input being a wave function (i.e.: a state of 0 and a state of 1) is able to be performed in the mind in an individual. For example [0 , 1, 1, 0]. Therefore this limitation is a further recitation of the abstract idea.
and performing the vector parallelism on the second tensor for the converted first input parameter by using the vector instruction set, to obtain processing results respectively corresponding to the plurality of input wave functions.
As stated above in claim 1, this is an individual tracing through a quantum circuit and calculating vector and matrix calculations which can be performed by an individual with a pen and paper. Where the vector instruction set as already stated is the usage of computer hardware for its ordinary task. Therefore this claim further recites an abstract idea.
Claim 5:
The method according to claim 3,
wherein the primitive function is configured to optimize a group of circuit variation parameters of a target quantum circuit in the quantum circuit simulation,
Circuit variation parameters are parameters which outline properties of the circuit. For example F(rotation) = .. .
As stated above, the input wave function is a piece of received data using a normal computing device. Furthermore, one ordinarily skilled in the art could perform the above mental processes with a pen and paper using different inputs (ie: matrix rotation of pi). Therefore, this claim is a further recitation of the primitive function which is data received by an ordinary computing device and does not integrate the above judicial exceptions.
and the performing the vector parallelism on the second tensor for the converted first input parameter comprises:
splicing a plurality of groups of circuit variation parameters of the target quantum circuit into the second tensor for the converted first input parameter;
The steps above perform the function of claims 1-3, with the difference being that the input is circuit variation parameters. As outlined above, splicing the input into the second tensor, where the input being a circuit variation parameter is able to be performed in the mind in an individual. For example [0, pi/2, pi]. Therefore this limitation is a further recitation of the abstract idea.
and performing the vector parallelism on the second tensor for the converted first input parameter by using the vector instruction set, to obtain optimization results respectively corresponding to the plurality of groups of circuit variation parameters.
As stated above in claim 1, this is an individual tracing through a quantum circuit and calculating vector and matrix calculations which can be performed by an individual with a pen and paper. Where the vector instruction set as already stated is the usage of computer hardware for its ordinary task. Therefore this claim further recites an abstract idea.
Claim 6:The method according to claim3, wherein the primitive function is configured to
generate circuit noise of a target quantum circuit in the quantum circuit simulation according to a group of random numbers,
Circuit noise is a degree of random error as it occurs in the circuit simulation. As stated above, the input wave function is a piece of received data using a normal computing device. For example f(noise=3) = … Furthermore, one ordinarily skilled in the art could perform the above mental processes with a pen and paper using different inputs (ie: delete a rotation gate). Therefore, this claim is a further recitation of the primitive function which is data received by an ordinary computing device and does not integrate the above judicial exceptions.
and the performing the vector parallelism on the second tensor for the converted first input parameter comprises:
splicing a plurality of groups of random numbers into the second tensor for the converted first input parameter; and
The steps above perform the function of claims 1-3, with the difference being that the input is circuit noise. As outlined above, splicing the input into the second tensor, where the input being circuit noise is able to be performed in the mind in an individual. For example [delete first gate, add a gate, replace first gate]. Therefore this limitation is a further recitation of the abstract idea.
performing the vector parallelism on the second tensor for the converted first input parameter by using the vector instruction set, to obtain noise simulation results respectively corresponding to the plurality of groups of random numbers.
As stated above in claim 1, this is an individual tracing through a quantum circuit and calculating vector and matrix calculations which can be performed by an individual with a pen and paper. Where the vector instruction set as already stated is the usage of computer hardware for its ordinary task. Therefore this claim further recites an abstract idea.
Claim 7:The method according to claim 3, wherein the primitive function is configured to
generate a circuit structure of a target quantum circuit according to a group of control parameters in the quantum circuit simulation,
Circuit structure is the presence/absence of gates/operations in the circuit simulation. Where it is understood that operations in the context of the quantum circuit simulator are mathematic matrix operations. As stated above, the primitive function is a piece of received data using a normal computing device. For example f(3) = … Furthermore, one ordinarily skilled in the art could perform the above mental processes with a pen and paper using different inputs (ie: a circuit with 3 gates). Therefore, this claim is a further recitation of the primitive function which is data received by an ordinary computing device and does not integrate the above judicial exceptions.
and the performing the vector parallelism on the second tensor for the converted first input parameter comprises:
splicing a plurality of groups of control parameters into the second tensor for the converted first input parameter;
The steps above perform the function of claims 1-3, with the difference being that the input is circuit structure. As outlined above, splicing the input into the second tensor, where the input being circuit structure is able to be performed in the mind in an individual. For example [circuit structure 1, circuit structure 2, circuit structure 3]. Therefore this limitation is a further recitation of the abstract idea.
and performing the vector parallelism on the second tensor for the converted first input parameter by using the vector instruction set, to obtain circuit structure generation results respectively corresponding to the plurality of groups of control parameters.
As stated above in claim 1, this is an individual tracing through a quantum circuit and calculating vector and matrix calculations which can be performed by an individual with a pen and paper. Where the vector instruction set as already stated is the usage of computer hardware for its ordinary task. Therefore this claim further recites an abstract idea.
Claim 8:
The method according to claim 3, wherein the primitive function is configured to
perform a circuit measurement of a target quantum circuit according to a group of measurement parameters in the quantum circuit simulation,
Circuit measurement parameters are how the qubits/outputs are measured in the circuit simulation. Where it is understood that operations in the context of the quantum circuit simulator are mathematic matrix operations. As stated above, the primitive function is a piece of received data using a normal computing device. For example f(X, Y, Z) = … Furthermore, one ordinarily skilled in the art could perform the above mental processes with a pen and paper using different inputs (ie: measure Z value). Therefore, this claim is a further recitation of the primitive function which is data received by an ordinary computing device and does not integrate the above judicial exceptions.
and the performing the vector parallelism on the second tensor for the converted first input parameter comprises:
splicing a plurality of groups of measurement parameters into the second tensor for the converted first input parameter;
The steps above perform the function of claims 1-3, with the difference being that the measurement parameters. As outlined above, splicing the input into the second tensor, where the input being circuit structure is able to be performed in the mind in an individual. For example [X, Y, Z]. Therefore this limitation is a further recitation of the abstract idea.
and performing the vector parallelism on the second tensor for the converted first input parameter by using the vector instruction set, to obtain measurement results respectively corresponding to the plurality of groups of measurement parameters.
As stated above in claim 1, this is an individual tracing through a quantum circuit and calculating vector and matrix calculations which can be performed by an individual with a pen and paper. Where the vector instruction set as already stated is the usage of computer hardware for its ordinary task. Therefore this claim further recites an abstract idea.
Claim 9:The method according to claim 1, wherein the converting the primitive function to the target function comprises: modifying the first input parameter in the primitive function to the converted first input parameter; and in response to a second input parameter in the primitive function of no parallelizing need, retaining the second input parameter in the target function.
This claim is a further recitation of the “modifying” step of claim 1 and is a further recitation of the abstract idea. Furthermore, one ordinarily skilled in the art may reasonably evaluate that a second input parameter does not need to be parallelized based on what the user would like to be tested. Therefore this limitation is a further recitation of the abstract idea.
Claim 10:
The method according to claim 1, wherein the converting the primitive function to the target function comprises:
calling a function conversion interface with the primitive function and first information being provided to the function conversion interface, the first information indicating the first input parameter in the primitive function for parallelizing, and the function conversion interface causing the primitive function to be converted to the target function according to the first information.
This claim limitation provides information to an interface which then causes the abstract ideas of claim 1 to occur. The MPEP 2106.05(f)(2) states “Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more.” This claim transmits data through an interface rather than apply the exception in practical application, and Therefore this claim limitation does not integrate a judicial exception into a practical application or provide significantly more.
Claim 11:
The method according to claim 10, further comprising:
providing second information to the function conversion interface, the second information indicating a second input parameter in the primitive function for calculating a derivative, the function conversion interface converting the primitive function to the target function according to the first information and the second information, and the target function comprising derivative information of the primitive function according to the second input parameter.
This claim limitation provides information to an interface which is then used for the judicial exception of calculating derivatives. The MPEP 2106.05(f)(2) states “Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more.” This claim transmits data through an interface rather than apply the exception in practical application, and Therefore this claim limitation does not integrate a judicial exception into a practical application or provide significantly more.
Claim 12:
The method according to claim 11, wherein the function conversion interface comprises a first interface and a second interface,
the first interface is configured to convert the primitive function to a first target function according to the first information;
and the second interface is configured to convert the primitive function to a second target function according to the first information and the second information.
As stated previously, This claim limitation provides information to an interface which then causes the abstract ideas of claim 1 to occur. The MPEP 2106.05(f)(2) states “Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more.” This claim transmits data through an interface rather than apply the exception in practical application, and Therefore this claim limitation does not integrate a judicial exception into a practical application or provide significantly more.
Claim 13:
The method according to claim 10, wherein the function conversion interface is an application programming interface (API) that encapsulates a machine learning library, the machine learning library is configured to provide a vector instruction set for executing the target function to obtain the execution result.
This claim states that the function conversion interface API encapsulates a digital machine learning library which provides the vector instruction set which performs the judicial exceptions of claims 1-3. As understood by the examiner, a digital machine learning library uses a regular computer to call different mathematic functions. The MPEP 2106.05(f)(2) states “Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more.” Therefore, the fact that a machine learning library is called, using a conversion interface, does not integrate the judicial exception into a practical application or provide significantly more.
Claims 14-19:
Claims 14-19 are effective duplicates of claims 1-6 and are therefore rejected under a similar rational. Claims 14-19 are directed to an apparatus which is a machine. Claims 14-19 additionally recite An apparatus for a quantum circuit simulation, comprising processing circuitry configured to.
The MPEP 2106.05(f)(2) states “Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more.” Therefore this claim limitation does not integrate a judicial exception into a practical application or provide significantly more.
Claim 20:
Claim 20 is an effective duplicates of claims 1 and is therefore rejected under a similar rational. Claim 20 is directed to a non-transitory computer-readable storage medium which is a manufactured product. Claim 20 additionally recite A non-transitory computer-readable storage medium storing instructions which when executed by at least one processor cause the at least one processor to perform:
The MPEP 2106.05(f)(2) states “Use of a computer or other machinery in its ordinary capacity for economic or other tasks (e.g., to receive, store, or transmit data) or simply adding a general purpose computer or computer components after the fact to an abstract idea (e.g., a fundamental economic practice or mathematical equation) does not integrate a judicial exception into a practical application or provide significantly more.” Therefore this claim limitation does not integrate a judicial exception into a practical application or provide significantly more.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 9, 14-17, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Luo_2020 (“Yao.jl: Extensible, Efficient Framework for Quantum Algorithm Design” as evidenced by Johnny_2021 (“When vectorization hits the memory wall: investigating the AVX2 memory gather instruction”)
Claim 1:
Luo_2020 teaches A method of a quantum circuit simulation, comprising: ( abstract: “It achieves state-of-the-art performance in simulating small to intermediate sized quantum circuits that are relevant to near-term applications.”)
receiving a primitive function for the quantum circuit simulation; (See figure 1: QBIR. “quantum block intermediate representation”. Where this is a mathematic/code intermediate representation which is what is understood to be the primitive function for the circuit simulation. With example given in page 5 section 2.1 “ In Yao, it takes three lines of code to construct the QBIR of the QFT circuit”)
determining at least a first input parameter of the primitive function, the quantum circuit simulation including a plurality of first tensors respectively for the first input parameter; (page 5 col 2 par 2: “In Yao, to execute a quantum circuit, one can simply feed a quantum state (examiner note: a first input parameter) into the QBIR (examiner note: of the primitive function).
_ Listing 2: apply! and pipe _
julia> rand_state(3) |> qft(3);
# same as apply!(rand_state(3), qft(3))
_ _
Here, we define a random state on 3 qubits (examiner note: a plurality of first tensors for the first input parameter) and pass it through the QFT circuit.
converting the primitive function to a target function according to the primitive function and at least the first input parameter, the target function including a converted first input parameter corresponding to the first input parameter, the plurality of first tensors being spliced into a second tensor for the converted first input parameter in the quantum circuit simulation; (page 13 section 4.3 Batched Quantum Registers: “The batched register is a collection of quantum wave functions. It can be samples of classical data for quantum machine learning tasks [66] or an ensemble of pure quantum states for thermal state simulation [55]. For both applications, having the batch dimension not only provides convenience but may also significantly speed up the simulations. We adopt the Single Program Multiple Data (SPMD) [67] design in Yao similar to modern machine learning frameworks so that it can make use of modern multi-processors such as multi-threading or GPU support (and potentially multi-processor QPUs). Applying a quantum circuit to a batched register means to apply the same quantum circuit to a batch of wave functions in parallel, (Examiner note: Where the quantum circuit which can be applied to a batch register is the target function which includes a batch of wave functions in parallel as the input parameter) which is extremely friendly to modern multi-processors. The memory layout of the quantum register is a matrix of the size 2a × 2rB, where a is the number of system qubits, r is the number of remaining qubits (or environment qubits), B is the batch size. (Examiner note: This is the first tensors spliced together into a batched matrix/input which is the second tensor) For gates acting on the active qubits, the remaining qubits and batch dimension can be treated on an equal footing. We put the batch dimension as the last dimension because Julia array is column majored. As the last dimension, it favors broadcasting on the batch dimensions. One can construct a batched register in Yao and perform operations on it. These operations are automatically broadcasted over the batch dimension.
obtaining an execution result of the target function according to at least the second tensor for the converted first input parameter; (page 13 col 2: “Listing 16: a batch of quantum registers _
julia> reg = rand_state(4; nbatch=5);
julia> reg |> qft(4) |> measure!
5-element Array{BitBasis.BitStr{4,Int64},1}:
1011 (2)
1011 (2)
0000 (2)
1101 (2)
0111 (2) _ _
Note that we have used the measure! Function to collapse all batches.
The measurement results are represented in BitStr type which is a subtype of Integer and has a static length. Here, it pretty-prints the measurement results and provides a convenient readout of measuring results.
and performing the quantum circuit simulation based on the execution result of the target function. (page 15 section 5.3 Parametrized Quantum Circuit Performance “Next, we benchmark the parameterized circuit of depth d = 10 shown in Fig. 9(a). This type of hardware efficient circuits was employed in the VQE experiment [57]. These benchmarks further test the performance of circuit abstraction in practical applications. The results in Fig. 9(b) shows that Yao reaches the best performance for more than 10 qubits on CPU. qulacs’s well tuned C++ simulator is faster than Yao for fewer qubits. On a CUDA device, Yao and qulacs show similar performance. qiskit cuda backend shows better performance for more that 20 qubits. These benchmarks also, show that CUDA parallelization starts to be beneficial for a qubit number larger than 16. Overall, Yao is one of the fastest quantum circuit simulators for this type of application.” .. see figure 9a description “Figure 9: (a) A parameterized quantum circuit with single qubit rotation and CNOT gates; (b) Benchmarks of the parameterized circuit; (c) Benchmarks of the parametrized circuit, the batched version. Line “yao" represents the batched registers, “yao (cuda)" represents the batched register on GPU, “yao × 1000" is running on a non-batched register repeatedly for 1000 times.” Examiner note: Where these inherently show a simulation being performed on the batched registers which all contain execution results.
Claim 2:The method according to claim 1, wherein the obtaining the execution result comprises:
Luo_2020 teaches processing the converted first input parameter through a vector parallelism, to obtain the execution result.
(page 13 section 4.3 Batched Quantum Registers: We adopt the Single Program Multiple Data (SPMD) [67] design in Yao similar to modern machine learning frameworks so that it can make use of modern multi-processors such as multi-threading or GPU support (and potentially multi-processor QPUs). Applying a quantum circuit to a batched register means to apply the same quantum circuit to a batch of wave functions in parallel, which is extremely friendly to modern multi-processors. The memory layout of the quantum register is a matrix of the size 2a × 2rB, where a is the number of system qubits, r is the number of remaining qubits (or environment qubits), B is the batch size. (Examiner note: This is the first tensors spliced together into a batched matrix/input which is the second tensor) page 14 col 2 par 2: “Our test machine contains an Intel(R) Xeon(R) Gold 6230 CPU with a Tesla V100 GPU accelerator. SIMD is enabled with AVX2 instruction set”
Examiner note: Where this is understood to be vector parallelism. Please see specifications par 34 of this instant application “For example, for a function f(x)=2xx, when 1 is inputted, 2 is returned, that is, f(l)=2. In a vector parallelism version fv(x), fv([1, 2])=[2, 4] may be implemented. This process does not require successive computing. Instead, a vector instruction set (or referred to as a vectorized instruction set) on the hardware may be used to complete the computations at one time.” Where vector parallelism is understood to be the process of running the different state vectors In parallel, which is functionally equivalent to what is described above. See also AVX2 instruction set, which shows that this is vector parallelism. Where Johnny_2021 provides evidence that the [AVX2 instruction set is a vector instruction set]. under section “what are vector gather instructions: “Vector instruction set has a load instruction that can load N identical consecutive values from the memory. For example, AVX2 instruction set”). Where this process constructed through a vector instruction set to perform the functionally equivalent method as outlined above is vector parallelism.
Claim 3:
The method according to claim 2, wherein the processing the converted first input parameter comprises:
Luo_2020 as evidenced by Johnny_2021 teaches performing the vector parallelism on the second tensor for the converted first input parameter by using a vector instruction set, the vector instruction set comprising one or more executable instructions for a processor to perform the vector parallelism on the second tensor for the converted first input parameter.
(page 13 section 4.3 Batched Quantum Registers: We adopt the Single Program Multiple Data (SPMD) [67] design in Yao similar to modern machine learning frameworks so that it can make use of modern multi-processors such as multi-threading or GPU support (and potentially multi-processor QPUs). Applying a quantum circuit to a batched register means to apply the same quantum circuit to a batch of wave functions in parallel, which is extremely friendly to modern multi-processors … page 14 col 2 par 2: “Our test machine contains an Intel(R) Xeon(R) Gold 6230 CPU with a Tesla V100 GPU accelerator. SIMD is enabled with AVX2 instruction set”
Where Johnny_2021 provides evidence that the [AVX2 instruction set is a vector instruction set]. under section “what are vector gather instructions: “Vector instruction set has a load instruction that can load N identical consecutive values from the memory. For example, AVX2 instruction set”)
Claim 4:Luo_2020 as evidenced by Johnny_2021 teaches The method according to claim 3, wherein the primitive function is configured to process an input wave function of a target quantum circuit in the quantum circuit simulation, (page 13 section 4.3 Batched Quantum Registers: “The batched register is a collection of quantum wave functions. (examiner note: configured to process an input wave function)
and the performing the vector parallelism on the second tensor comprises:
splicing a plurality of input wave functions of the target quantum circuit into the second tensor for the converted first input parameter; and performing the vector parallelism on the second tensor for the converted first input parameter by using the vector instruction set, to obtain processing results respectively corresponding to the plurality of input wave functions.
(page 13 section 4.3 Batched Quantum Registers: “The batched register is a collection of quantum wave functions. (examiner note: configured to process an input wave function) It can be samples of classical data for quantum machine learning tasks [66] or an ensemble of pure quantum states for thermal state simulation [55]. For both applications, having the batch dimension not only provides convenience but may also significantly speed up the simulations. We adopt the Single Program Multiple Data (SPMD) [67] design in Yao similar to modern machine learning frameworks so that it can make use of modern multi-processors such as multi-threading or GPU support (and potentially multi-processor QPUs). Applying a quantum circuit to a batched register means to apply the same quantum circuit to a batch of wave functions in parallel, (Examiner note: performing vector parallelism on the second tensor) which is extremely friendly to modern multi-processors. The memory layout of the quantum register is a matrix of the size 2a × 2rB, where a is the number of system qubits, r is the number of remaining qubits (or environment qubits), B is the batch size. (Examiner note: This is the first tensors of input wave functions spliced together into a batched matrix/input which is the second tensor) For gates acting on the active qubits, the remaining qubits and batch dimension can be treated on an equal footing. We put the batch dimension as the last dimension because Julia array is column majored. As the last dimension, it favors broadcasting on the batch dimensions. One can construct a batched register in Yao and perform operations on it. These operations are automatically broadcasted over the batch dimension.
page 13 col 2: “Listing 16: a batch of quantum registers _
julia> reg = rand_state(4; nbatch=5);
julia> reg |> qft(4) |> measure!
5-element Array{BitBasis.BitStr{4,Int64},1}:
1011 (2)
1011 (2)
0000 (2)
1101 (2)
0111 (2) _ _
Note that we have used the measure! Function to collapse all batches.
The measurement results (Examiner note: obtain processing results respectively corresponding to the plurality of input wave functions.) are represented in BitStr type which is a subtype of Integer and has a static length. Here, it pretty-prints the measurement results and provides a convenient readout of measuring results. … Page 14 col 2 par 2: “Our test machine contains an Intel(R) Xeon(R) Gold 6230 CPU with a Tesla V100 GPU accelerator. SIMD is enabled with AVX2 instruction set” (Examiner note: Vector parallelism done through vector instruction set)
Claim 9:
The method according to claim 1, wherein the converting the primitive function to the target function comprises:
Luo_2020 further recites modifying the first input parameter in the primitive function to the converted first input parameter; (page 9 col 2: “Here, variational_circuit is predefined in YaoExtensions to have a hardware efficient architecture [57] shown in Fig. 9. The dispatch! function with the second parameter specified to :random gives random initial parameters. The expect function evaluates expectation values of the observables; the second argument can be a wave function or a pair of the input wave function (Examiner note: a first input parameter which is converted, see claim 1) and circuit ansatz like above. expect' evaluates the gradient of this observable for the input wave function and circuit parameters. Here, we only make use of its second return value. For batched registers, the gradients of circuit parameters are accumulated rather than returning a batch of gradients.”
and in response to a second input parameter in the primitive function of no parallelizing need, retaining the second input parameter in the target function.
Page 10:" In case one would like to share parameters in the variational circuit (Examiner note: When there is no parallelizing need) , one can simply use the same block instance in the QBIR.” (Examiner note: An express recitation that the other parameters (ie second input parameter) are retained by choice, while the first parameter (wave functions) is batched and varied as outlined in claim 1.
Claims 14-17:Claims 14 – 17 are effective duplicated of claims 1-4 respectively and are therefore rejected under the same rationales as claims 1-4 above. Additionally claims 14-17 recite and pertain to an apparatus, which is taught by Luo_2020
Luo_2020 teaches the additional limitations of An apparatus for a quantum circuit simulation, (abstract: “Yao features generic and differentiable programming of quantum circuits. It achieves state of-the-art performance in simulating small to intermediate sized quantum circuits that are relevant to near-term applications.”) comprising processing circuitry configured to: (Page 14 col 2 par 2 “Our test machine contains an Intel(R) Xeon(R) Gold 6230 CPU with a Tesla V100 GPU accelerator. SIMD is enabled with AVX2 instruction set”)
Claim 20:
Claim 20 is an effective duplicate of claim 1 and is therefore rejected under the same rational as claim 1. Additionally claim 20 recites A non-transitory computer-readable storage medium, which is taught by Luo_2020.
Luo_2020 teaches the additional limitations of A non-transitory computer-readable storage medium storing instructions (page 11 section 4.1 “Quantum registers store quantum states in contiguous memory, which can either be the CPU memory or other hardware memory, such as a CUDA device.”) which when executed by at least one processor cause the at least one processor to perform: (Page 14 col 2 par 2 “Our test machine contains an Intel(R) Xeon(R) Gold 6230 CPU with a Tesla V100 GPU accelerator. SIMD is enabled with AVX2 instruction set”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5-6, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Luo_2020 as evidenced by Johnny_2021 And further in view of guerreschi_2020 (“Intel Quantum Simulator: A cloud-ready high-performance simulator of quantum circuits”).
Claim 5:
Luo_2020 as evidenced by Johnny_2021 makes obvious The method according to claim 3, wherein the primitive function is configured to page 13 section 4.3 Batched Quantum Registers: “The batched register is a collection of quantum wave functions. (examiner note: configured to process an input wave function)
and the performing the vector parallelism on the second tensor for the converted first input parameter comprises:
splicing a plurality of groups of
(page 13 section 4.3 Batched Quantum Registers: “The batched register is a collection of quantum wave functions. (examiner note: configured to process an input wave function) It can be samples of classical data for quantum machine learning tasks [66] or an ensemble of pure quantum states for thermal state simulation [55]. For both applications, having the batch dimension not only provides convenience but may also significantly speed up the simulations. We adopt the Single Program Multiple Data (SPMD) [67] design in Yao similar to modern machine learning frameworks so that it can make use of modern multi-processors such as multi-threading or GPU support (and potentially multi-processor QPUs). Applying a quantum circuit to a batched register means to apply the same quantum circuit to a batch of wave functions in parallel, (Examiner note: perfoming vector parallelism on the second tensor) which is extremely friendly to modern multi-processors. The memory layout of the quantum register is a matrix of the size 2a × 2rB, where a is the number of system qubits, r is the number of remaining qubits (or environment qubits), B is the batch size. (Examiner note: This is the first tensors of input wave functions spliced together into a batched matrix/input which is the second tensor) For gates acting on the active qubits, the remaining qubits and batch dimension can be treated on an equal footing. We put the batch dimension as the last dimension because Julia array is column majored. As the last dimension, it favors broadcasting on the batch dimensions. One can construct a batched register in Yao and perform operations on it. These operations are automatically broadcasted over the batch dimension.
page 13 col 2: “Listing 16: a batch of quantum registers _
julia> reg = rand_state(4; nbatch=5);
julia> reg |> qft(4) |> measure!
5-element Array{BitBasis.BitStr{4,Int64},1}:
1011 (2)
1011 (2)
0000 (2)
1101 (2)
0111 (2) _ _
Note that we have used the measure! Function to collapse all batches.
The measurement results (Examiner note: obtain processing results respectively corresponding to the plurality of input wave functions.) are represented in BitStr type which is a subtype of Integer and has a static length. Here, it pretty-prints the measurement results and provides a convenient readout of measuring results. … Page 14 col 2 par 2: “Our test machine contains an Intel(R) Xeon(R) Gold 6230 CPU with a Tesla V100 GPU accelerator. SIMD is enabled with AVX2 instruction set” (Examiner note: Vector parallelism done through vector instruction set)
Luo_2020 does not expressly recite optimize a group of circuit variation parameters … groups of circuit variation parameters.
Where Luo_2020 teaches the methods of claims 1-3 applied to variations of input wave functions, but expressly to optimize circuits through groups of circuit variation parameters
Guerreschi_2020 however makes obvious optimize a group of circuit variation parameters … groups of circuit variation parameters. (page 5-6: “The most consequential change in the IQS implementation compared to its original release is the ability of dividing the processes into groups using the MPI function MPI Comm create group . Each group can be used to store a quantum state, possibly in a distributed way if the group itself is composed by more than one process. Now, when a QubitRegister object is created, it actually initializes a state in each group of processes: we call \pool" the collection of such states. In addition, when a method of the form ApplyGate is called, the gate is actually applied to each and every state of the pool.” … “There are two important observations: the first one is that defining a non-trivial pool of states may take advantage of the available processes in a more effective way. The second is that each state of the pool is naturally subjected to the same quantum circuit. The latter characteristic, if strictly enforced, would make the simulations redundant: we would simulate over and over the same identical evolution. However it is possible to differentiate the applied circuit for each of the state in the pool and the relevant commands are discussed in Appendix D. Moreover, there are cases in which simulating closely related circuits is required and what seemed a limitation actually becomes a beneficial feature. Here we discuss two of these situations and present the corresponding results in Section IV. Code snippets are discussed in Appendix D.
In Variational Quantum Algorithms (VQA) a quantum circuit composed of parametric gates is optimized to prepare states with desired properties, often related to having large overlap with the ground state of certain observables. During the optimization, the same circuit is simulated over and over with the only difference being the value of its parameters (examiner note: optimizing a group of circuit variation parameters) (think of them as the angle of one-qubit rotations). Within the pool functionality, it is easy to assign different parameter values to the circuit simulated by the distinct states in the pool. (Examiner note: groups of different circuit parameters) This approach greatly speedup the overall simulations of VQA protocols based on several classes of optimizers, like genetic algorithm, swarm particle optimization, or gradient-based methods.”
Luo_2020 and Guerreschi_2020 are analogous art to the claimed invention because they are from the same field of endeavor called quantum circuit simulation. Before the effective filing date, it would have been obvious to a person ordinarily skilled in the art to combine Luo_2020 and Guerreschi_2020.
The rational for doing so would have been to follow a teaching and motivation proposed in the prior art. Luo states section 8.2: “Circuit compilation and optimization is a key topic for quantum computing towards practical experiments. A new language interface along with a compiler for Yao [93] is under development. It should be more compilation friendly with a design based on Julia’s native abstract syntax tree. By integrating with Julia compiler, it will allow Yao to model quantum channels in a seamlessly way. On the other hand, quantum circuit simplification and optimization are crucial for reducing the cost of both simulations and experiments. The ongoing circuit simplification project [94] will also support better pattern matching and term rewriting system with support of ZX calculus [95]. This will allows smarter and more systematic circuit simplifications such as the ones in Refs. [96–98].” Guerreschi_2020 provides a method in the art of performing this goal, which is running these circuits in parallel, which is similar to how Luo_2020 runs circuits in batches, see page 2 par 3: “We expect
that at least two use cases will profit massively from this extension. First, when multiple circuits or variants of the same circuit have to be run in parallel (think for example of variational algorithms in conjunction with classical optimizers like the genetic algorithm or particle swarm optimizers). And second, when stochastic methods are used to include noise and decoherence in the simulation.”
Therefore it would have been obvious to combine the batched simulation workflow of Luo_2020 with the variational quantum circuit simulations of Guerreschi_2020 for the benefit of reducing the cost of simulations and experiments to obtain the invention as specified in the claims.
Claim 6:
Luo_2020 as evidenced by Johnny_2021 makes obvious The method according to claim3, wherein the primitive function is configured to page 13 section 4.3 Batched Quantum Registers: “The batched register is a collection of quantum wave functions. (examiner note: configured to process an input wave function)
and the performing the vector parallelism on the second tensor for the converted first input parameter comprises:
splicing a plurality of groups of random numbers [input wave functions] into the second tensor for the converted first input parameter; and
performing the vector parallelism on the second tensor for the converted first input parameter by using the vector instruction set,
(page 13 section 4.3 Batched Quantum Registers: “The batched register is a collection of quantum wave functions. (examiner note: configured to process an input wave function) It can be samples of classical data for quantum machine learning tasks [66] or an ensemble of pure quantum states for thermal state simulation [55]. For both applications, having the batch dimension not only provides convenience but may also significantly speed up the simulations. We adopt the Single Program Multiple Data (SPMD) [67] design in Yao similar to modern machine learning frameworks so that it can make use of modern multi-processors such as multi-threading or GPU support (and potentially multi-processor QPUs). Applying a quantum circuit to a batched register means to apply the same quantum circuit to a batch of wave functions in parallel, (Examiner note: perfoming vector parallelism on the second tensor) which is extremely friendly to modern multi-processors. The memory layout of the quantum register is a matrix of the size 2a × 2rB, where a is the number of system qubits, r is the number of remaining qubits (or environment qubits), B is the batch size. (Examiner note: This is the first tensors of input wave functions spliced together into a batched matrix/input which is the second tensor) For gates acting on the active qubits, the remaining qubits and batch dimension can be treated on an equal footing. We put the batch dimension as the last dimension because Julia array is column majored. As the last dimension, it favors broadcasting on the batch dimensions. One can construct a batched register in Yao and perform operations on it. These operations are automatically broadcasted over the batch dimension.
page 13 col 2: “Listing 16: a batch of quantum registers _
julia> reg = rand_state(4; nbatch=5);
julia> reg |> qft(4) |> measure!
5-element Array{BitBasis.BitStr{4,Int64},1}:
1011 (2)
1011 (2)
0000 (2)
1101 (2)
0111 (2) _ _
Note that we have used the measure! Function to collapse all batches.
The measurement results (Examiner note: obtain processing results respectively corresponding to the plurality of input wave functions.) are represented in BitStr type which is a subtype of Integer and has a static length. Here, it pretty-prints the measurement results and provides a convenient readout of measuring results. … Page 14 col 2 par 2: “Our test machine contains an Intel(R) Xeon(R) Gold 6230 CPU with a Tesla V100 GPU accelerator. SIMD is enabled with AVX2 instruction set” (Examiner note: Vector parallelism done through vector instruction set)
Luo_2020 does not expressly recite generate circuit noise of according to a group of random numbers, .. obtain noise simulation results … groups of random numbers
Where Luo_2020 teaches the methods of claims 1-3 applied to variations of input wave functions, but not expressly to generate circuit noise according to a group of random numbers.
Guerreschi_2020 however makes obvious generate circuit noise of according to a group of random numbers, .. obtain noise simulation results … groups of random numbers (page 5-6: “The most consequential change in the IQS implementation compared to its original release is the ability of dividing the processes into groups using the MPI function MPI Comm create group . Each group can be used to store a quantum state, possibly in a distributed way if the group itself is composed by more than one process. Now, when a QubitRegister object is created, it actually initializes a state in each group of processes: we call \pool" the collection of such states. In addition, when a method of the form ApplyGate is called, the gate is actually applied to each and every state of the pool.” … “There are two important observations: the first one is that defining a non-trivial pool of states may take advantage of the available processes in a more effective way. The second is that each state of the pool is naturally subjected to the same quantum circuit. The latter characteristic, if strictly enforced, would make the simulations redundant: we would simulate over and over the same identical evolution. However it is possible to differentiate the applied circuit for each of the state in the pool and the relevant commands are discussed in Appendix D. Moreover, there are cases in which simulating closely related circuits is required and what seemed a limitation actually becomes a beneficial feature. Here we discuss two of these situations and present the corresponding results in Section IV. Code snippets are discussed in Appendix D.
…
“IQS is a simulator of unitary dynamics in which each state is pure. Nonetheless it is possible to use IQS to simulate the effect of noise and decoherence during the circuit (Examiner note: obtain noise influenced results) by means of introducing stochastic perturbations (Examiner note: random numbers. See also code in page 13-14 which has “RandomNumberGenerator”) to the ideal circuit and averaging over the ensemble of \perturbed" circuits [18]. Formally, this approach is based on the unraveling of master equations into stochastic Schrodinger equations in the circuit-model formalism [40] and corresponds to the introduction of additional \noise gates" in the form of one-qubit rotations with stochastic rotation angles. IQS provides specialized methods to apply these noise gates that automatically varies their rotation angles over the pool's states. (Examiners note: ie: varies the random numbers)
Luo_2020 and Guerreschi_2020 are analogous art to the claimed invention because they are from the same field of endeavor called quantum circuit simulation. Before the effective filing date, it would have been obvious to a person ordinarily skilled in the art to combine Luo_2020 and Guerreschi_2020.
The rational for doing so would have been to follow a teaching and motivation proposed in the prior art. Luo_2020 section 8.3 states “Noise important for simulation of near-term quantum devices. Currently, Yao does not support noisy simulations directly. However, a batched register in Yao be conveniently converted to a reduced density matrix. By porting Yao with QuantumInformation.jl [99], one can carry out noisy simulation with density matrices. One can find a blog in Appendix I.” Guerreschi_2020 provides a method in the art of performing this goal, which is running these circuits in parallel, which is similar to how Luo_2020 runs circuits in batches, see page 2 par 3: “We expect that at least two use cases will profit massively from this extension. First, when multiple circuits or variants of the same circuit have to be run in parallel (think for example of variational algorithms in conjunction with classical optimizers like the genetic algorithm or particle swarm optimizers). And second, when stochastic methods are used to include noise and decoherence in the simulation.”
As outlined, Luo_2020 understood the importance of noisy simulation and provides a method to perform it with a batched register. Guerreschi_2020 also provides a method to generate noisy circuits. Therefore it would have been obvious to combine the batched simulation workflow of Luo_2020 with the variational noise simulations of Guerreschi_2020 for the benefit of simulating an important metric in near-term quantum devices to obtain the invention as specified in the claims.
Claims 18-19:
Claims 18-19 are effective duplicates of claims 5-6 respectively except that they depend on claim 14, and are therefore rejected under the same rationales as claims 5-6 and claims 14.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Luo_2020 as evidenced by Johnny_2021 And further in view of Broughton_2021 (“TensorFlow Quantum: A Software Framework for Quantum Machine Learning”)
Claim 7:Luo_2020 as evidenced by Johnny_2021 makes obvious The method according to claim 3, wherein the primitive function is configured page 13 section 4.3 Batched Quantum Registers: “The batched register is a collection of quantum wave functions. (examiner note: configured to process an input wave function)
and the performing the vector parallelism on the second tensor for the converted first input parameter comprises:
splicing a plurality of page 13 section 4.3 Batched Quantum Registers: “The batched register is a collection of quantum wave functions. (examiner note: configured to process an input wave function) It can be samples of classical data for quantum machine learning tasks [66] or an ensemble of pure quantum states for thermal state simulation [55]. For both applications, having the batch dimension not only provides convenience but may also significantly speed up the simulations. We adopt the Single Program Multiple Data (SPMD) [67] design in Yao similar to modern machine learning frameworks so that it can make use of modern multi-processors such as multi-threading or GPU support (and potentially multi-processor QPUs). Applying a quantum circuit to a batched register means to apply the same quantum circuit to a batch of wave functions in parallel, (Examiner note: perfoming vector parallelism on the second tensor) which is extremely friendly to modern multi-processors. The memory layout of the quantum register is a matrix of the size 2a × 2rB, where a is the number of system qubits, r is the number of remaining qubits (or environment qubits), B is the batch size. (Examiner note: This is the first tensors of input wave functions spliced together into a batched matrix/input which is the second tensor) For gates acting on the active qubits, the remaining qubits and batch dimension can be treated on an equal footing. We put the batch dimension as the last dimension because Julia array is column majored. As the last dimension, it favors broadcasting on the batch dimensions. One can construct a batched register in Yao and perform operations on it. These operations are automatically broadcasted over the batch dimension.
page 13 col 2: “Listing 16: a batch of quantum registers _
julia> reg = rand_state(4; nbatch=5);
julia> reg |> qft(4) |> measure!
5-element Array{BitBasis.BitStr{4,Int64},1}:
1011 (2)
1011 (2)
0000 (2)
1101 (2)
0111 (2) _ _
Note that we have used the measure! Function to collapse all batches.
The measurement results (Examiner note: obtain processing results respectively corresponding to the plurality of input wave functions.) are represented in BitStr type which is a subtype of Integer and has a static length. Here, it pretty-prints the measurement results and provides a convenient readout of measuring results. … Page 14 col 2 par 2: “Our test machine contains an Intel(R) Xeon(R) Gold 6230 CPU with a Tesla V100 GPU accelerator. SIMD is enabled with AVX2 instruction set” (Examiner note: Vector parallelism done through vector instruction set)
Luo_2020 does not expressly recite to generate a circuit structure of a target quantum circuit according to a group of control parameters … groups of control parameters .. obtain circuit structure generation results respectively corresponding to the plurality of groups of control parameters
Luo_2020 teaches the process of claims 1-3 as applied to input wave functions, but not expressly to circuit structures.
Broughton_2021 however makes obvious to generate a circuit structure of a target quantum circuit according to a group of control parameters … groups of control parameters .. obtain circuit structure generation results respectively corresponding to the plurality of groups of control parameters (par 34: “2. Layerwise quantum circuit learning (Examiner note: generate a circuit structure of a target quantum circuit) ” .. par 2: “In phase one, the algorithm constructs the circuit by subsequently adding and training layers of a predefined structure. We start by picking a number of initial layers s, that contains parameters which are always active during training to avoid entering a regime where the number of active parameters is too small to decrease the loss [133]. These layers are then trained for a fixed number of iterations el, after which another set of layers is added to the circuit. How many layers this set contains is controlled by a hyperparameter p. Another hyperparameter q determines after how many layers the parameters in previous layers are frozen. I.e., for p = 2 and q = 4, we add two layers at intervals of el iterations, and only train the parameters in the last four layers, while all other parameters in the circuit are kept fixed. (Examiner note: Generated according to group control parameters) This procedure is repeated until a fixed, predefined circuit depth is reached” … see page 34 code … see page 35 code pertaining to layerwise quantum learning:
# Update model parameters and add
# new 0 parameters for new layers .
model . set_weights
[np. pad ( weights , ( n_qubits , 0))])
model . fit ( x_train ,
y_train ,
batch_size =128 ,
epochs =10 ,
verbose =1,
validation_data =( x_test , y_test )) “
Luo_2020 and Broughton_2021 are analogous art to the claimed invention because they are from the same field of endeavor called quantum simulation. Before the effective filing date, it would have been obvious to a person ordinarily skilled in the art to combine Luo_2020 and Broughton_2021.
The rational for doing so would have been to follow a teaching and motivation proposed in the prior art. Luo states section 8.2: “Circuit compilation and optimization is a key topic for quantum computing towards practical experiments. A new language interface along with a compiler for Yao [93] is under development. It should be more compilation friendly with a design based on Julia’s native abstract syntax tree. By integrating with Julia compiler, it will allow Yao to model quantum channels in a seamlessly way. On the other hand, quantum circuit simplification and optimization are crucial for reducing the cost of both simulations and experiments. The ongoing circuit simplification project [94] will also support better pattern matching and term rewriting system with support of ZX calculus [95]. This will allows smarter and more systematic circuit simplifications such as the ones in Refs. [96–98].” Broughton_2021 similarly has a method for accomplishing this task, see page 34 col 2 : “1. Dynamically building circuits for arbitrary learning tasks 2. Manipulating circuit structure and parameters during training 3. Reducing the number of trained parameters.” Broughton_2021 acknowledges the usage of batching during training, see code 35 above, as well as batching over circuits of varying size, see page 11 col 2 : “Given these, the Sample layer produces a tf.RaggedTensor of shape [batch_size, num_samples, n_qubits] , where the n_qubits dimension is ragged to account for the possibly varying circuit size over the input batch of quantum data. One ordinarily skilled in the art would recognize that the training parameters of Broughton_2021 which manipulates circuit structure during training could be combined with the batch training, which would allow the user of Luo_2020 to generate optimized circuit structures for learning tasks.
Therefore it would have been obvious to combine the quantum circuit batching workflow of Yoa_2020 with the generation of circuit structure using control parameters by Broughton_2021 for the benefit of performing circuit compilation to solve the key topic of circuit compilation to accomplish learning tasks and reduce numbers of trained parameters to reduce the cost of simulations and experiments to obtain the invention as specified in the claims.
Claim 8:
Luo_2020 as evidenced by Johnny_2021 makes obvious The method according to claim 3, wherein the primitive function is configured to perform a circuit measurement of a target quantum circuit [process an input wave function] according to a group of measurement parameters in the quantum circuit simulation, , (page 13 section 4.3 Batched Quantum Registers: “The batched register is a collection of quantum wave functions. (examiner note: configured to process an input wave function)
and the performing the vector parallelism on the second tensor for the converted first input parameter comprises:
splicing a plurality of groups of measurement parameters into the second tensor for the converted first input parameter; and performing the vector parallelism on the second tensor for the converted first input parameter by using the vector instruction set, to obtain measurement results respectively corresponding to the plurality of groups of measurement parameters. [process wave function results] (page 13 section 4.3 Batched Quantum Registers: “The batched register is a collection of quantum wave functions. (examiner note: configured to process an input wave function) It can be samples of classical data for quantum machine learning tasks [66] or an ensemble of pure quantum states for thermal state simulation [55]. For both applications, having the batch dimension not only provides convenience but may also significantly speed up the simulations. We adopt the Single Program Multiple Data (SPMD) [67] design in Yao similar to modern machine learning frameworks so that it can make use of modern multi-processors such as multi-threading or GPU support (and potentially multi-processor QPUs). Applying a quantum circuit to a batched register means to apply the same quantum circuit to a batch of wave functions in parallel, (Examiner note: perfoming vector parallelism on the second tensor) which is extremely friendly to modern multi-processors. The memory layout of the quantum register is a matrix of the size 2a × 2rB, where a is the number of system qubits, r is the number of remaining qubits (or environment qubits), B is the batch size. (Examiner note: This is the first tensors of input wave functions spliced together into a batched matrix/input which is the second tensor) For gates acting on the active qubits, the remaining qubits and batch dimension can be treated on an equal footing. We put the batch dimension as the last dimension because Julia array is column majored. As the last dimension, it favors broadcasting on the batch dimensions. One can construct a batched register in Yao and perform operations on it. These operations are automatically broadcasted over the batch dimension.
page 13 col 2: “Listing 16: a batch of quantum registers _
julia> reg = rand_state(4; nbatch=5);
julia> reg |> qft(4) |> measure!
5-element Array{BitBasis.BitStr{4,Int64},1}:
1011 (2)
1011 (2)
0000 (2)
1101 (2)
0111 (2) _ _
Note that we have used the measure! Function to collapse all batches.
The measurement results (Examiner note: obtain processing results respectively corresponding to the plurality of input wave functions.) are represented in BitStr type which is a subtype of Integer and has a static length. Here, it pretty-prints the measurement results and provides a convenient readout of measuring results. … Page 14 col 2 par 2: “Our test machine contains an Intel(R) Xeon(R) Gold 6230 CPU with a Tesla V100 GPU accelerator. SIMD is enabled with AVX2 instruction set” (Examiner note: Vector parallelism done through vector instruction set)
Luo_2020 does not expressly recite a circuit measurement of a target quantum circuit … according to a group of measurement parameters in the quantum circuit simulation … obtain measurement results respectively corresponding to the plurality of groups of measurement parameters.
Luo_2020 teaches the methods of claim 1-3 applied to input wave functions, not measurements parameters
Broughton_2021 however makes obvious a circuit measurement of a target quantum circuit … according to a group of measurement parameters in the quantum circuit simulation … obtain measurement results respectively corresponding to the plurality of groups of measurement parameters. (page 11 col 2 par 5: “TFQ implements tfq.layers.Expectation , a Keras layer which enables the extraction of measurement expectation values (Examiner note: circuit measurement of a target quantum circuit) from quantum models. The user supplies a tensor of parameterized circuits, a list of symbols contained in the circuits, a tensor of values to substitute for the symbols in the circuit, and a tensor of operators to measure with respect to them (Examiner note: a group of measurement parameters to which measurement results are obtains corresponding got the measurements parameters). Given these inputs, the layer outputs a tensor of expectation values. “)
Luo_2020 and Broughton_2021 are analogous art to the claimed invention because they are from the same field of endeavor called quantum simulation. Before the effective filing date, it would have been obvious to a person ordinarily skilled in the art to combine Luo_2020 and Broughton_2021.The rational for doing so would have been to follow a teaching and motivation in the prior art.
Luo_2020 states page 1 col 1 par 1: “A block refers to a tensor representation of quantum operations, which can be quantum circuits and quantum operators of various granularities (quantum gates, Hamiltonian, or the whole program)”With “Measure” being given as a block in page 27. See also page 9 col 2 “For batched registers, the gradients of circuit parameters are accumulated rather than returning a batch of gradients. …. Page 10:" In case one would like to share parameters in the variational circuit, one can simply use the same block instance in the QBIR.” Which implies that anything in blocks can be varied across circuits when using different block instances in the QBIR. Furthermore
Broughton_2021 provides motivation to vary and store multiple measurement parameters. Broughton_2021 states page 20 col 2 section Hybrid Quantum Classical Neural Networks: “Note that, in some cases, instead of the expectation values of the set of operators f^hkgMk =1, one may instead want to relay the histogram of measurement results obtained from multiple measurements of the eigenvalues of each of these observables.” … page 21 col 1 par 1: “Thus, considering vectors of expectation values is a relatively general way of representing the output of a quantum neural network. In the limit where the set of observables considered forms an informationally complete set of observables [104], then the array of measurement outcomes would fully characterize the wavefunction,” Luo_2020 page 17 acknowledges the ability of their Yao program to neural network training “Yao’s efficient AD engine and batched quantum register support allow joint training of quantum circuit and classical neural network effortlessly.”
Therefore it would have been obvious to combine the batched workflow of Lou_2020 with the input of varying measurement parameters of Broughton_2021 by for the benefit of fully characterizing a wavefunction through a plurality of measurement results run in parallel to improve neural network training to obtain the invention as specified in the claims.
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Luo_2020 as evidenced by Johnny_2021 And further in view of Bergholm_2020 (“PennyLane: Automatic differentiation of hybrid quantum classical computations”)
Claim 10:
The method according to claim 1, wherein the converting the primitive function to the target function comprises:
Luo_2020 makes obvious calling a function conversion interface with the primitive function and first information being provided to the function conversion interface,( Page 4 col 1 : “Yao builds its customized type system and dispatches to the quantum registers and circuits with a general interface.” … Page 11 col 2 par 2: “The quantum register stores hardware-specific information about the quantum states (Examiner note: Where the quantum state is the information provided that needs parallelizing, see claim 1, where the quantum states are handled in the batched registers). In classical simulation on a CPU, the quantum register is an array containing the quantum wave function. For GPU simulations, the quantum register stores the pointer to a GPU array. In an actual experiment, the register should be the quantum device that hosts the quantum state. Yao handles all of these cases with a unified apply! interface, which dispatches the instructions depending on different types of QBIR nodes and registers.”) page 13 section 4.3 “We adopt the Single Program Multiple Data (SPMD) [67] design in Yao similar to modern machine learning frameworks so that it can make use of modern multi-processors such as multi-threading or GPU support (and potentially multi-processor QPUs). Applying a quantum circuit to a batched register means to apply the same quantum circuit to a batch of wave functions in parallel, (Examiner note: Where the quantum circuit which can be applied to a batch register is the target function which includes a batch of wave functions in parallel as the input parameter) which is extremely friendly to modern multi-processors. The memory layout of the quantum register is a matrix of the size 2a × 2rB, where a is the number of system qubits, r is the number of remaining qubits (or environment qubits), B is the batch size. (Examiner note: This is the first tensors spliced together into a batched matrix/input which is the second tensor)” (Examiner note: see also claim 1 mapping)
Bergholm_2020 however makes , the first information indicating the first input parameter in the primitive function for parallelizing, and the function conversion interface
Page 8 col 2 par 1: PennyLane also provides a higher-level interface for easily and automatically creating and processing QNodes. This includes a library of circuit ansätze or ‘templates’ from across the quantum machine learning literature, tools to map a single ansatz across multiple observables or devices, and the ability to easily create cost functions for common quantum variational algorithms.
Page 9 col 1 : “A number of variational algorithms, such as the variational quantum eigensolver, require numerous quantum circuit evaluations per optimization time-step. In Penny- Lane, this corresponds to constructing and evaluating multiple QNodes. PennyLane provides a high-level framework for processing and manipulating groups of (possibly independent) QNodes, known as a QNodeCollection. QNode collections are sequences of QNodes, each bound to potentially different devices, that can be evaluated independently —i.e., the input of any QNode in the collection does not depend on the output of another.”
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Examiner note: where the qNodes are passed into the qNodeColelction to be run in parallel through the higher level interface. This is the input parameter that gets parallelized.
Luo_2020 and Bergholm_2020 are analogous art to the claimed invention because they are from the same field of endeavor called quantum circuit simulation. Before the effective filing date, it would have been obvious to a person ordinarily skilled in the art to combine Luo_2020 and Bergholm_2020. The rational for doing so would have been to follow teaching and motivation proposed in the prior art.
Luo_2020 states page 9 col 2: “To demonstrate the efficiency of Yao’s AD engine, we use the codes in Listing 9 to simulate the variational quantum eigensolver (VQE)” and Page 17 col 2 par 2: “Circuit compilation and optimization is a key topic for quantum computing towards practical experiments. A new language interface along with a compiler for Yao [93] is under development. It should be more compilation friendly with a design based on Julia’s native abstract syntax tree. By integrating with Julia compiler, it will allow Yao to model quantum channels in a seamlessly way.”
Bergholm_2020 states page 9 col 2: “The key advantage of QNode collections is that, since the QNodes are independent, they can be evaluated simultaneously and are embarrassingly parallelizable” The creator of Luo_2020 would recognize that an interface could be applied to simulate parallelizable functions and simulations, which would allow Luo_2020 optimize variational circuits in parallel.
Therefore it would have been obvious to combine the workflow of Luo_2020 with the use of an interface which calls in inputs for parallelization for the benefit of allowing variational circuits to run in parallel for optimization tasks to obtain the invention as specified in the claims.
Claim 11:
Luo_2020 makes obvious providing page 9 col 2 par 2 – page 10: “Here, variational_circuit is predefined in YaoExtensions to have a hardware efficient architecture [57] shown in Fig. 9. The dispatch! function with the second parameter specified to :random gives random initial parameters. The expect function evaluates expectation values of the observables; the second argument can be a wave function (Examiner note: the first input parameter) or a pair of the input wave function and circuit ansatz like above. expect' evaluates the gradient of this observable for the input wave function and circuit parameters. Here, we only make use of its second return value. For batched registers, the gradients of circuit parameters are accumulated rather than returning a batch of gradients. dispatch!(-, circuit, ...) implements the gradient descent algorithm with energy as the loss function. The first argument is a binary operator that computes a new parameter based on the old parameter in c and the third argument, the gradients. (Examiner note: Where these are arguments /second information used for calculating the derivatives) Parameters in a circuit can be extracted by calling parameters(circuit), which collects parameters into a vector by visiting the QBIR in depthfirst order. The same parameter visiting order is used in dispatch!. In case one would like to share parameters in the variational circuit, one can simply use the same block instance in the QBIR. In the training process, gradients can be updated in the same field. After the training, the circuit is fully optimized and returns the ground state of the model Hamiltonian with zero state as input. (Examiner note: where the target function uses both the derivative information with gradients and the arguments)
Luo_2020 does not expressly recite providing
Where Luo_2020 does not expressly recite a methodology which allows a user to select a second information which is used to calculate the derivative.
Bergholm_2020 however makes obvious providing second information to the function conversion interface, the second information (page 8 col 1 par 4-5: “PennyLane currently has seven built-in optimizers, which work with the default Autograd interface: standard gradient descent, gradient descent with momentum, gradient descent with Nesterov momentum, Adagrad, Adam, RMSprop, and quantum natural gradient descent [45]. For the PyTorch and TensorFlow, the optimizers provided by those libraries can be used. While automatic differentiation with gradients and Jacobians is a handy feature, sometimes we want certain parts of our computational pipeline (e.g., the inputs x in the supervised learning example) not to be part of a gradient. In PennyLane all positional arguments to quantum nodes can be differentiated, while keyword arguments are never differentiated. (Examiner note: Where the positional arguments are the second information) Thus, when using the gradient-descent-based optimizers included in PennyLane, all numerical parameters appearing in non-keyword arguments will be updated, while numerical values included as keyword arguments will not be updated. Once defined, keyword arguments must always be passed as keyword arguments, and not as positional arguments.”
Luo_2020 and Bergholm_2020 are analogous art to the claimed invention because they are from the same field of endeavor called quantum circuit simulation. Before the effective filing date, it would have been obvious to a person ordinarily skilled in the art to combine Luo_2020 and Bergholm_2020. The rational for doing so would have been to follow teaching and motivation proposed in the prior art.
Luo_2020 states page 9 col 2: “To demonstrate the efficiency of Yao’s AD engine, we use the codes in Listing 9 to simulate the variational quantum eigensolver (VQE)” and Page 17 col 2 par 2: “Circuit compilation and optimization is a key topic for quantum computing towards practical experiments. A new language interface along with a compiler for Yao [93] is under development. It should be more compilation friendly with a design based on Julia’s native abstract syntax tree. By integrating with Julia compiler, it will allow Yao to model quantum channels in a seamlessly way.” Bergholm_2020 provides a similar method of optimization using derivatives, Bergholm_2020 provides a benefit of “page 8 col 1 par 5: While automatic differentiation with gradients and Jacobians is a handy feature, sometimes we want certain parts of our computational pipeline (e.g., the inputs x in the supervised learning example) not to be part of a gradient” In order to conduct supervised learning for quantum optimization tasks, one ordinarily skilled in the art would incorporate a standard machine learning interface to specify which inputs need to be a part of the gradient and which inputs should remain static (ie: such as circuit structure)
Therefore it would have been obvious to combine the gradients and simulation methodology of Luo_2020 with the usage of second information with gradients for the benefit of optimizing certain parameters of circuits while allowing the rest to remain static to obtain the invention as specified in the claims.
Claim 12:
The method according to claim 11,
Luo_2020 makes obvious wherein the function conversion interface comprises a first interface and a second interface, (page 9 col 2 “expect” and “expect’”)
the first interface is configured to convert the primitive function to a first target function according to the first information; (page 9 col 2: “Here, variational_circuit is predefined in YaoExtensions to have a hardware efficient architecture [57] shown in Fig. 9. The dispatch! function with the second parameter specified to :random gives random initial parameters. The expect function evaluates expectation values of the observables; (examiner note: a first interface, where the function is understood to be the interface, where this acts on the circuit/primitive function ) the second argument can be a wave function or a pair of the input wave function and circuit ansatz (Examiner note: The first information) like above”
and the second interface is configured to convert the primitive function to a second target function according to the first information and the second information. (page 9 col 2: “expect' (examiner note: the second interface) evaluates the gradient (examiner note: a second target function which computes a gradient of circuit/prim. Function) of this observable for the input wave function and circuit parameters (Examiner note: first information) . Here, we only make use of its second return value. For batched registers, the gradients of circuit parameters are accumulated (Examiner note: second information) rather than returning a batch of gradients.”)
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Luo_2020 as evidenced by Johnny_2021 And further in view of Bergholm_2020 and Broughton_2021
Claim 13:
Luo_2020 does not expressly recite, but Broughton_2021 makes further obvious The method according to claim 10, wherein the function conversion interface is an application programming interface (API) that encapsulates a machine learning library, the machine learning library is configured to provide a vector instruction set for executing the target function to obtain the execution result. (page 8 figure 4 description: “Figure 4. The software stack of TFQ, showing its interactions with TensorFlow, Cirq, and computational hardware. At the top of the stack is the data to be processed. Classical data is natively\ processed by TensorFlow; TFQ adds the ability to process quantum data, consisting of both quantum circuits and quantum operators. The next level down the stack is the Keras API in TensorFlow. (Examiner note: Where keras is the function conversion interface. see page 34: “Keras weight manipulation interface” ) page 6: “TensorFlow is a language for describing computations as stateful dataflow graphs [67]. Describing machine learning models as dataflow graphs is advantageous for performance during training.”( Examiner note: Where TensorFlow is understood to be a machine learning library) … page 14 col 1: “TFQ will adapt to the user’s available hardware. For CPU based simulations, SSE2 instruction set [82] and AVX2 + AVX512 instruction sets” (Examiner note: Where as evidenced by Johnny_2021, this is a vector instruction set, see page 3: “Vector instruction set has a load instruction that can load N identical consecutive values from the memory. For example, AVX2 instruction set.” Where it is understood that this instruction set does the simulations which is executing the target function which is the batched execution of the quantum circuit).
Luo_2020 and Broughton_2021 are analogous art to the claimed invention because they are from the same field of endeavor called quantum circuit simulation. Before the effective filing date, it would have been obvious to a person ordinarily skilled in the art to combine Luo_2020 and Broughton_2021. The rational for doing so would have been to follow a teaching and motivation proposed in the prior art.
Broughton_2021 page 5 col 1 states “Today, exploring new hybrid quantum-classical models is a difficult and error-prone task. The engineering effort required to manually construct such models, develop quantum datasets, and set up training and validation stages decreases a researcher’s ability to iterate and discover. TensorFlow has accelerated the research and understanding of deep learning in part by automating common model building tasks. Development of software tooling for hybrid quantum classical models should similarly accelerate research and understanding for quantum machine learning. To develop such tooling, the requirement of accommodating a heterogeneous computational environment involving both classical and quantum processors is key. This computational heterogeneity suggested the need to expand TensorFlow, which is designed to distribute computations across CPUs, GPUs, and TPUs [67], to also encompass quantum processing units (QPUs). This project has evolved into TensorFlow Quantum. TFQ is an integration of Cirq with TensorFlow that allows researchers and students to simulate QPUs while designing, training, and testing hybrid quantum-classical models, and eventually run the quantum portions of these models on actual quantum processors as they come online. A core contribution of TFQ is seamless backpropagation through combinations of classical and quantum layers in hybrid quantum-classical models. This allows QML researchers to directly harness the rich set of tools already available in TF and Keras.” Luo_2021 page 26 states “It is straightforward to make use of external libraries written in other languages”
Therefore, it would have been obvious to combine quantum simulation workflow of Luo_2020 with the usage of machine learning libraries called with an API for the benefit of harnessing premade tools already available to advance quantum computing simulation through machine learning algorithms to obtain the invention as specified in the claims.
Conclusion
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/A.H.S./Examiner, Art Unit 2187
/EMERSON C PUENTE/Supervisory Patent Examiner, Art Unit 2187
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