DETAILED ACTION
This Office action is in response to the Preliminary amendment filed on September 20, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 22, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were filed on May 26, 2023. These drawings are accepted by the Examiner.
Claim Objections
Claim 14 is objected to because of the following informalities: “The processing device of claim 11, wherein the controller is directly coupled to the vertical power module” should be “The processing device of claim 11, wherein a controller is directly coupled to the vertical power module” because claim 11 does not recite a controller, therefore this correction is necessary in order to prevent any 112th issues related to lack of antecedent basis. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-11 and 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nan et al. (U.S. Pub. 2022/0415558 A1, Reference Provided as Part of the Information Disclosure Statement “IDS”).
In re claim 1, Nan discloses a processing device (Fig. 3), the processing device comprising:
a processing unit (xPU 380);
a printed circuit board (PCB 370) in communication with the processing unit;
a Trans-Inductor Voltage Regulator (TLVR) based vertical power Voltage Regulator (VR) module (TLVR module 350) in communication with and directly coupled to the printed circuit board (PCB 370); and
a controller in communication with, and configured to control, the TLVR based vertical power VR module (Para. 0026).
In re claim 2, Nan discloses wherein the TLVR based vertical power VR module does not include a capacitance board (See Fig. 3, the TLVR module 350 does not include a capacitance board).
In re claim 6, Nan discloses wherein the TLVR based vertical power VR module includes one or more output capacitors (Fig. 3, Para. 0026).
In re claim 7, Nan discloses wherein the PCB includes one or more output capacitors on a surface closest to the TLVR based vertical power VR module (Fig. 3, Para. 0026).
In re claim 8, Nan discloses wherein the PCB includes one or more output capacitors on a surface closest to the processing unit (Fig. 3, Para. 0026).
In re claim 9, Nan discloses wherein the processing unit is directly coupled to a first surface of the PCB (See Fig. 3).
In re claim 10, Nan discloses wherein the TLVR based vertical power VR module is directly coupled to a second side of the PCB opposite of the first side of the PCB, wherein the TLVR based vertical power VR module is positioned directly under the processing unit (See Fig. 3).
In re claim 11, Nan discloses a processing device (Fig. 3), the processing device comprising:
a processing unit (xPU 380);
a printed circuit board (PCB 370) in communication with the processing unit;
a vertical power module (TLVR module 350) in communication with and directly coupled to the printed circuit board, wherein the vertical power module does not include a capacitance board (See Fig. 3, the VR module 350 does not include a capacitance board); and
one or more output capacitors (the TLVR module 350 may not include a capacitance board, such as cap-board 255 described in connection with FIG. 2; but it may include capacitors serving as the output capacitance of the TLVR circuit on the module, Para. 0026).
In re claim 15, Nan discloses wherein the one or more output capacitors are on a surface of the PCB closest to the vertical power module (Fig. 3, Para. 0026).
In re claim 16, Nan discloses wherein the one or more output capacitors are on a surface of the PCB closest to the processing unit (Fig. 3, Para. 0026).
In re claim 17, Nan discloses wherein the one or more output capacitors are on the vertical power module (Fig. 3, Para. 0026).
In re claim 18, Nan discloses wherein the processing unit is directly coupled to a first surface of the PCB (See Fig. 3).
In re claim 19, Nan discloses wherein the vertical power module is directly coupled to a second side of the PCB opposite of the first side of the PCB, wherein the vertical power VR module is positioned directly under the processing unit (See Fig. 3).
In re claim 20, Nan discloses further comprising a second vertical power module (Para. 0026-0027).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3, 5, 12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Nan et al. (U.S. Pub. 2022/0415558 A1, Reference Provided as Part of the Information Disclosure Statement “IDS”) in view of Capetillo (U.S. Pub. No. 2023/0049859 A1).
In re claim 3, Nan discloses fails to disclose wherein the controller operates a constant on- time control scheme.
Capetillo teaches (Fig. 7) a Trans-Inductor Voltage Regulator (300), wherein the controller (500) operates a constant on- time control scheme (Para. 0044).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Nan wherein the controller operates a constant on- time control scheme as disclosed in Capetillo to respond to a change in load current, allowing for a faster transient response (Para. 0002).
In re claim 5, Nan fails to disclose wherein the controller is directly coupled to the TLVR based vertical power VR module.
Capetillo teaches (Fig. 7) a Trans-Inductor Voltage Regulator (300), wherein the controller (500) is directly coupled to the TLVR based vertical power VR module (See Fig. 7).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Nan wherein the controller is directly coupled to the TLVR based vertical power VR module as disclosed in Capetillo to respond to a change in load current, allowing for a faster transient response (Para. 0002).
In re claim 12, Nan discloses a controller (Para. 0026).
Nan discloses fails to disclose wherein the controller operates a constant on- time control scheme.
Capetillo teaches (Fig. 7) a Trans-Inductor Voltage Regulator (300) wherein the controller (500) operates a constant on- time control scheme (Para. 0044).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Nan wherein the controller operates a constant on- time control scheme as disclosed in Capetillo to respond to a change in load current, allowing for a faster transient response (Para. 0002).
In re claim 14, Nan fails to disclose wherein the controller is directly coupled to the vertical power module.
Capetillo teaches (Fig. 7) a Trans-Inductor Voltage Regulator (300), wherein the controller (500) is directly coupled to the vertical power module (See Fig. 7).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Nan wherein the controller is directly coupled to the vertical power module as disclosed in Capetillo to respond to a change in load current, allowing for a faster transient response (Para. 0002).
Allowable Subject Matter
Claims 4 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 4, the prior art of record fails to disclose or suggest “wherein the TLVR based vertical power VR module has a 1Ons latency requirement” in combination with other limitations of the claim.
Regarding to claim 13, the prior art of record fails to disclose or suggest “wherein the vertical power module has a 1Ons latency requirement” in combination with other limitations of the claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAFAEL O. DE LEÓN DOMENECH whose telephone number is (571)270-0517. The examiner can normally be reached 8:00 a.m. -5:00 p.m..
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/RAFAEL O DE LEON DOMENECH/Primary Examiner, Art Unit 2838