DETAILED ACTION
Response to Amendment
This Office Action is in response to applicant’s communication filed March 9, 2026 in response to PTO Office Action dated March 3, 2026. The applicant’s remarks and amendment to the specification and/or claims were considered with the results that follow.
Claims 2-26 and 28-41 have been presented for examination in this application. In response to the last Office Action, claims 21-26, 28-30, 33, 35, 36, 38, 40, and 41 have been amended.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21-26 and 28-41 is/are rejected under 35 U.S.C. 102(a)(2)as being anticipated by Karthikeyan et al. (US# 2021/0124409).
Regarding claim 21, Karthikeyan et al. teaches a storage device comprising: a connector comprising a power management pin, wherein the power management pin comprises a first electrical connection, the connector further comprising a second electrical connection [0037, lines 1-4; Figure 1B with pin connections at ends of power, C/E, and PWDIS_CONN lines];
a detector circuit configured to detect an asserted power management signal received on the power management pin [0038, lines 1-7; high/low assertion]; and
a power management circuit capable of configuring power to at least a portion of the storage device based, at least in part, on the detector circuit detecting the asserted power management signal [voltage levels of current PWDIS protocol voltages; 0038, lines 1-7];
wherein the storage device is configured to operate at a reduced power based, at least in part, on a state of a dual port operation signal (voltage level)( port from sender to port of receiver)received using the second electrical connection [reduced power interpreted as no power, 0037, lines 13-16; see also 0038, lines 4-10; 0037, lines 16-19].
Regarding claim 22, Karthikeyan et al. teaches wherein the asserted power management signal comprises operating in a first state, and, based at least in part on the operating in the first state, operating in a second state [0038, lines 4-10].
Regarding claim 23, Karthikeyan et al. teaches wherein the storage device further comprises a nonvolatile memory configured to indicate the type of the storage device [0032, lines 1-5; storage device follows from memory device type to which the commands are specifically translated/converted], and the storage device is configured to operate in at the reduced power mode based, at least in part, on the type of the storage device [0037, lines 13-19; memory operates according to power circuitry for SSD].
Regarding claim 24, Karthikeyan et al. teaches, wherein the storage device is configured to operate as a U.3 storage device at the reduced power [any other type of non-volatile memory; 0028, lines 1-4].
Regarding claim 25, Karthikeyan et al. teaches wherein the reduced power is a first reduced power, and the storage device is configured to operate, based at least in part on the asserted power management signal, in at a second reduced power mode. [0037, 13-16 and 0038, lines 4-10].
Regarding claim 26, Karthikeyan et al. teaches wherein the storage device is configured to operate, in at the second reduced power mode, as a U.2 storage device [any other type of non-volatile memory; 0028, lines 1-4].
Regarding claim 28, Karthikeyan et al. teaches wherein the storage device is configured to latch the asserted power management signal [0044].
Claims 29 and 36 recite similar subject matter to that of claim 21, and are rejected for the same reasons as claim 21.
Claims 30 and 38 recite similar subject matter to that of claim 22, and are rejected for the same reasons as claim 22.
Claims 31 and 39 recite similar subject matter to that of claim 23, and are rejected for the same reasons as claim 23.
Claims 32 and 41 recite similar subject matter to that of claim 24, and are rejected for the same reasons as claim 24.
Regarding claim 33, Karthikeyan et al. teaches wherein the at least a portion of the storage device is a first portion of the storage device (each storage cell), and the storage device is configured to reduce, based at least in part on the valid asserted power management signal, power to a second portion (another storage cell/s) of the storage device [claim does not recite that power is reduced to only second portion; 0037, lines 13-16; 0038, lines 4-10]
Claim 34 recites similar subject matter to that of claim 26, and is rejected for the same reasons as claim 26.
Claims 35 and 40 recite similar subject matter to that of claim 28, and are rejected for the same reasons as claim 28.
Regarding claim 37, Karthikeyan et al. teaches wherein the configuring the power to the at least a portion of the storage device comprises modifying the power to the at least a portion of the storage device [claim does not recite that power is reduced to only a portion; 0037, lines 13-16; 0038, lines 4-10].
Response to Arguments
Applicant’s arguments with respect to claim(s) 21-26 and 28-41 have been considered but are moot in view of the new prior art rejections.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Brian R. Peugh whose telephone number is (571) 272-4199. The examiner can normally be reached on Monday-Friday from 7:30am to 3:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Rocio Del Mar Perez-Velez, phone number 571-270-5935, can be reached. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is 571-272-2100.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/BRIAN R PEUGH/Primary Examiner, Art Unit 2133