DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Specification
The abstract of the disclosure is objected to because it is less than 50 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 5, 9, and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzawa et al. U.S. Patent Application 2018/0211949 (hereinafter “Uzawa”) and further in view of Huang et al. U.S. Patent Application 2011/0310514 (hereinafter “Huang”).
Regarding claim 1, Uzawa teaches a device comprising: a first interconnect (refer to GND)(fig.21) to provide a voltage (implicit); a second interconnect (refer to Tout)(fig.21); a parasitic bipolar junction transistor (BJT) circuit structure (refer to NMOS transistor N2 and diode D4)(fig.21)(refer also to fig.3 and fig. 5) comprising a metal-oxide semiconductor field effect transistor (MOSFET) first diode (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Dsn)(fig.3) and a MOSFET second diode (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Ddn)(fig.3) coupled in series with the first diode in an anti- parallel configuration relative to each other (implicit)(refer to fig.3), and a first node (i.e. node NBG)(fig.3)(refer also to back gate of NMOS transistor N2)(fig.21)(refer also to fig.5), wherein the first diode and the second diode are coupled to each other via the first node (implicit)(refer to fig.3), and wherein the first node provides a base terminal of the BJT circuit structure (refer to base of parasitic bipolar transistor of transistor NM)(fig.5); and a first resistor (i.e. resistor R4)(fig.21) coupled between the first node and the first interconnect (implicit)(refer to fig.21); however, Uzawa does not teach a third diode coupled between the second interconnect and the parasitic BJT circuit structure. However, Huang teaches a third diode (i.e. diode DQP1)(fig.4) coupled between the second interconnect and the parasitic BJT circuit structure (implicit)(refer to ENDin)(fig.4). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uzawa to include the diode of Huang to provide the advantage of increasing the operation voltage range of the input signal (refer to Huang abstract).
Regarding claim 2, Uzawa and Huang teach the device of claim 1; wherein the parasitic BJT circuit structure comprises: a first well structure of a first dopant type (i.e. Huang P-well)(fig.3), wherein the first diode comprises first source or drain regions of a second dopant type (refer to Huang N+ and D of QDN)(fig.3) and each extending at least partially into the first well structure (implicit), and wherein the second diode comprises second source or drain regions (refer to Huang N+ and S of QDN)(fig.3) extending at least partially into the first well structure (implicit), and wherein the second source or drain regions are each of the second dopant type (implicit); and a first tap structure extending at least partially into the first well structure (refer to Huang P+ and W of QDN)(fig.3), around the first source or drain regions (implicit), and around the second source or drain regions (implicit), wherein the first tap structure is of the first dopant type (implicit).
Regarding claim 5, Uzawa and Huang teach the device of claim 1, wherein the second interconnect is to communicate a signal (implicit), wherein the parasitic BJT circuit structure comprises a collector terminal (refer to Huang BTQDN)(fig.4) and an emitter terminal (refer to Huang BTQDN)(fig.4), wherein the third diode comprises a p-type diode coupled to the collector terminal (refer to Huang DQP1)(fig.4), and wherein the first interconnect is coupled to the emitter terminal (refer to Huang VSS)(fig.4).
Regarding claim 9, Uzawa and Huang teach the device of claim 1, wherein the second interconnect is to provide a second voltage (refer to Uzawa fig.3), wherein the parasitic BJT circuit structure comprises a collector terminal (refer to Huang BTQDN)(fig.4) and an emitter terminal (refer to Huang BTQDN)(fig.4), wherein the third diode comprises a p-type diode coupled to the collector terminal (refer to Huang DQP1)(fig.4), and wherein the first interconnect is coupled to the emitter terminal (refer to Huang VSS)(fig.4).
Regarding claim 11, Uzawa teaches an apparatus comprising: a first interconnect (refer to GND)(fig.21) to provide a voltage (implicit); a second interconnect (refer to Tout)(fig.21); an electrostatic discharge (ESD) clamp structure (refer to transistor N2, diode D4, and resistor R4)(fig.21) having a first terminal coupled to the first interconnect (implicit) and a second terminal coupled to the second interconnect (implicit), wherein the ESD clamp structure comprises a parasitic NPN bipolar junction transistor (BJT) circuit structure (refer to NMOS transistor N2 and diode D4)(fig.21)(refer also to fig.3 and fig. 5) comprising a base (refer to fig.5), an emitter terminal (refer to fig.5), a collector terminal (refer to fig.5), and anti-parallel MOSFET first (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Dsn)(fig.3) and second diodes (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Ddn)(fig.3) each having an anode (implicit)(refer to fig.3), wherein the base comprises the anodes (implicit)(refer to figs. 3 and 5); however, Uzawa does not teach a third diode having aa anode coupled to the second interconnect and a cathode coupled to the collector terminal of the BJT circuit structure. However, Huang teaches a third diode (i.e. diode DQP1)(fig.4) having an anode coupled to the second interconnect (implicit) and a cathode coupled to the emitter terminal of the BJT circuit structure (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Uzawa to include the diode of Huang to provide the advantage of increasing the operation voltage range of the input signal (refer to Huang abstract).
Regarding claim 12, Uzawa and Huang teach the apparatus of claim 11; however, they do not teach wherein the ESD clamp comprises a shunting capacity of at least 1.3V, and wherein the apparatus comprises at least one semiconductor device coupled to the first and second interconnects and having an operation voltage of 1.2V. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the ESD clamp comprising a shunting capacity of at least 1.3V, and wherein the apparatus comprises at least one semiconductor device coupled to the first and second interconnects and having an operation voltage of 1.2V, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Uzawa and Boyd to include wherein the ESD clamp having a shunting capacity of at least 1.3V, and wherein the apparatus comprises at least one semiconductor device coupled to the first and second interconnects and having an operation voltage of 1.2V to provide the advantage of properly sizing the ESD clamp to the circuit’s needs.
Regarding claim 13, Uzawa and Huang teach the apparatus of claim 11, comprising a first resistor (i.e. Uzawa resistor R4)(fig.21) coupled between the base and the first interconnect (implicit)(refer to Uzawa fig. 21).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzawa and Huang as applied to claim 2 above, and further in view of Sithanandam et al. U.S. Patent Application 2019/0319453 (hereinafter “Sithanandam”).
Regarding claim 4, Uzawa and Huang teach the device of claim 2; however, they do not teach the device comprising at least one fin structure of at least one fin field effect transistor (finFET) structure comprising at least one fin having either (1) the first source or drain regions or (2) the second source or drain regions. However, Sithanandam teaches the device comprising at least one fin structure of at least one fin field effect transistor (finFET) structure (refer to [0044])(at least one fin is inherent in a FinFet) comprising at least one fin (refer to [0044])(at least one fin is inherent in a FinFet) having either (1) the first source or drain regions or (2) the second source or drain regions (refer to [0044]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uzawa and Huang to include the FinFet structure of Sithanandam to provide the advantage of using a smaller area of the chip for the ESD protection structure.
Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzawa et al. U.S. Patent Application 2018/0211949 (hereinafter “Uzawa”) and further in view of Boyd et al. U.S. Patent No. 7,719,806 (hereinafter “Boyd”).
Regarding claim 1, Uzawa teaches a device comprising: a first interconnect (refer to GND)(fig.21) to provide a voltage (implicit); a second interconnect (refer to Tout)(fig.21); a parasitic bipolar junction transistor (BJT) circuit structure (refer to NMOS transistor N2 and diode D4)(fig.21)(refer also to fig.3 and fig. 5) comprising a metal-oxide semiconductor field effect transistor (MOSFET) first diode (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Dsn)(fig.3) and a MOSFET second diode (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Ddn)(fig.3) coupled in series with the first diode in an anti- parallel configuration relative to each other (implicit)(refer to fig.3), and a first node (i.e. node NBG)(fig.3)(refer also to back gate of NMOS transistor N2)(fig.21)(refer also to fig.5), wherein the first diode and the second diode are coupled to each other via the first node (implicit)(refer to fig.3), and wherein the first node provides a base terminal of the BJT circuit structure (refer to base of parasitic bipolar transistor of transistor NM)(fig.5); and a first resistor (i.e. resistor R4)(fig.21) coupled between the first node and the first interconnect (implicit)(refer to fig.21); however, Uzawa does not teach a third diode coupled between the second interconnect and the parasitic BJT circuit structure. However, Boyd teaches a third diode (i.e. diode D1)(fig.6B) coupled between the second interconnect and the parasitic BJT circuit structure (implicit)(refer to PAD)(fig.6B). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uzawa to include the diode of Boyd to provide the advantage of minimizing leakage current in the device (refer to Boyd col. 7 line 59 to 67).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzawa and Boyd as applied to claim 1 above, and further in view of Disney et al. U.S. Patent Application 2008/0029820 (hereinafter “Disney”).
Regarding claim 7, Uzawa and Boyd teach the device of claim 1, wherein the second interconnect is to communicate a signal (implicit), wherein the parasitic BJT circuit structure comprises a collector terminal (refer to Uzawa fig.5) and an emitter terminal (refer to Uzawa fig.5), and wherein the first interconnect is coupled to the collector terminal (refer to Uzawa fig.5); however, they do not teach wherein the third diode is an n-type MOSFET diode coupled to the emitter terminal. However, Disney teaches wherein the third diode is an n-type MOSFET diode coupled to the emitter terminal (refer to top ESD clamp 401)(figs.4A and 4C). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uzawa and Boyd to include the MOSFET diode of Disney to provide the advantage of using equivalent structures for a diode circuit.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang and further in view of Uzawa and Abou-Khalil et al. U.S. Patent No. 8,503,140 (hereinafter “Abou-Khalil”).
Regarding claim 15, Huang teaches a system comprising: a first interconnect (refer to VDD)(fig.10) to provide a voltage (implicit) a second interconnect (refer to ENDIN)(fig.10); a pad-to VDD (PD) mode electrostatic discharge (ESD) clamp structure (i.e. ESD protection circuit 900)(fig.10) arranged to receive positive current from the second interconnect (implicit) and having a first terminal coupled to the first interconnect (implicit) and a second terminal coupled to the second interconnect (implicit), wherein the PD mode ESD clamp structure comprises a parasitic NPN bipolar junction transistor (BJT) circuit structure (refer to QDN)(figs.4 and 10)(refer also to BTQDN)(fig.4)(refer also to [0021]) comprising a base (refer to fig.4), an emitter terminal of an emitter (refer to fig.4), a collector terminal of a collector (refer to fig.4); and a third diode (refer to QP1)(figs.4 and 10)(refer also to DQP1)(fig.4)(refer also to [0021]) having an anode coupled to the second interconnect (implicit)(refer to fig.4) and a cathode coupled to the collector of the BJT circuit structure (implicit)(refer to fig.4); however, Huang does not teach the system being a computer implemented system, comprising a memory; and processor circuitry communicatively coupled to the memory, the processor circuitry comprising the first interconnect, second interconnect, PD mode ESD clamp structure, and the third diode; and the parasitic NPN BJT circuit structure comprising anti-parallel first and second diodes each having an anode, wherein the base comprises the anodes. However, Uzawa teaches the parasitic NPN BJT circuit structure comprising anti-parallel first (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Dsn)(fig.3) and second diodes (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Ddn)(fig.3) each having an anode (implicit)(refer to fig.3), wherein the base comprises the anodes (implicit)(refer to figs. 3 and 5). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Huang to include the anti-parallel diodes of Uzawa to provide the advantage of providing an equivalent circuit structure to the BJT of Huang. However, Huang and Uzawa do not teach the system being a computer implemented system, comprising a memory; and processor circuitry communicatively coupled to the memory, the processor circuitry comprising the first interconnect, second interconnect, PD mode ESD clamp structure, and the third diode. However, Abou-Khalil teaches the system being a computer implemented system (refer to col. 9 lines 42-58), comprising a memory (inherent)(refer to col. 9 lines 42-58); and processor circuitry communicatively coupled to the memory (inherent)(refer to col. 9 lines 42-58), the processor circuitry comprising the first interconnect, second interconnect, PD mode ESD clamp structure, and the third diode (refer to col. 9 lines 42-58). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Huang and Uzawa to include the computer implemented system of Abou-Khalil to provide the advantage of protecting systems which are vulnerable to ESD.
Regarding claim 16, Huang, Uzawa, and Abou-Khalil teach the system of claim 15; wherein the emitter and the collector each comprise a pair of n-doped regions spaced within an isolated p-type well (refer to Huang N+ region associated with D in QDN and N+ region associated with S in QDN)(fig.3), and wherein the base comprises a region of the isolated p-type well external to the n-doped regions (implicit)(refer to Huang P+ regions associated with W in QDN)(fig.3).
Regarding claim 17, Huang, Uzawa, and Abou-Khalil teach the system of claim 15, wherein the PD mode ESD clamp structure comprises a triple well having a p-type substrate (implicit)(refer to Huang fig.3), a deep n-type well on the p-type substrate (i.e. Huang Deep N-well)(fig.3), and an isolated p-type well within the deep n-type well (i.e. Huang P-well)(fig.3).
Double Patenting
Claims 1-4, 7, and 8 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 of copending Application No. 18/201,597 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-4 of the reference application contain all of the limitations of claims 1-4 of the instant application and claims 5 and 6 of the reference application contain all of the limitations of claims 7 and 8 of the instant application, respectively.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Allowable Subject Matter
Claims 3, 6, and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and rewritten or amended to overcome the Double Patenting rejection(s) set forth in this Office action.
Claims 10, 14, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claim 3 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 3, especially wherein the parasitic BJT circuit structure comprises: a second well structure extending under and around the first well structure, and having the second dopant type; and a second tap structure extending at least partially into the second well structure and having the second dopant type, wherein the second tap structure extends around the first well structure.
Claim 6 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 6, especially an input-output clamp circuit coupled between the first interconnect and the second interconnect; a fourth diode coupled in series with the first resistor between the first node and the first interconnect; and a second resistor coupled between the first node and the emitter terminal.
Claim 8 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 8, especially a fourth diode coupled in series with the first resistor between the first node and the first interconnect; and a second resistor coupled between the base terminal and the emitter terminal; and an input-output clamp circuit coupled between the first interconnect and the second interconnect.
Claim 10 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 10, especially a clamp circuit coupled between the first interconnect and the second interconnect, the clamp circuit comprising: two resistor-capacitor (RC) pairs coupled to each other in series and each having a resistor coupled to a capacitor at a common node, and two MOSFETs each having a gate, wherein a different one of the common nodes is coupled to one of the gates; and a first terminal on the second interconnect and coupled to the parasitic BJT circuit structure; a second terminal on the second interconnect and coupled to the clamp circuit; and a second resistor on the second interconnect between the first and second terminals.
Claim 14 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 14, especially a second resistor and a base diode coupled in series with the second resistor and between the base and the first interconnect, wherein the first resistor is in parallel to the second resistor and the base diode between the base and the first interconnect. Claims 18 and 19 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 18, especially wherein the PD mode ESD clamp structure comprises a first resistor coupled between the base and the first interconnect, and wherein the deep n-type well is coupled to the first resistor. Claim 19 is indicated as containing allowable subject matter based on its dependency on claim 18. Claim 20 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 20, especially wherein the emitter and the collector each comprise a pair of parallel n-doped strips spaced within the isolated p-type well, and wherein the base comprises a region of the isolated p-type well external to the strips, wherein one of the anti-parallel first or second diodes represents a first PN junction between the deep n-type well and the isolated p-type well, and the other of the anti-parallel first or second diodes represents a second PN junction between the deep n- type well and the p-type substrate, wherein the PD mode ESD clamp structure comprises: a p-tap within the isolated p-type well and extending around the strips; an n-tap within the deep n-type well and extending around the isolated p- type well; a first resistor coupled to the p-tap at the isolated p-type well to represent the first resistor being coupled between the base and the first interconnect; and a second resistor coupled to the n-tap at the deep n-type well to represent the second resistor being coupled between the base and the first interconnect in parallel to the first resistor, wherein a fourth diode is in series with the second resistor.
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838
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