DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Specification
The abstract of the disclosure is objected to because it is less than 50 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 and 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzawa et al. U.S. Patent Application 2018/0211949 (hereinafter “Uzawa”) and further in view of Boyd et al. U.S. Patent No. 7,719,806 (hereinafter “Boyd”).
Regarding claim 1, Uzawa teaches a device comprising: a first interconnect (refer to GND)(fig.21); a second interconnect (refer to Tout)(fig.21) to provide a signal (implicit); a parasitic bipolar junction transistor (BJT) circuit structure (refer to NMOS transistor N2 and diode D4)(fig.21)(refer also to fig.3 and fig. 5) comprising: a metal-oxide semiconductor field effect transistor (MOSFET) first diode (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Ddn)(fig.3), a MOSFET second diode (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Ddn)(fig.3) coupled in series with the first diode in an anti- parallel configuration relative to each other (implicit)(refer to fig.3), and a first node (i.e. node NBG)(fig.3)(refer also to back gate of NMOS transistor N2)(fig.21)(refer also to fig.5) comprising a base of the BJT circuit structure (refer to base of parasitic bipolar transistor of transistor NM)(fig.5), wherein the first diode and the second diode are coupled to each other via the first node (implicit)(refer to fig.3); and a first resistor (i.e. resistor R4)(fig.21) coupled between the first node and the first interconnect (implicit)(refer to fig.21); however, Uzawa does not teach a third diode coupled in series to the first and second diodes, coupled to the second interconnect, and having a forward bias to direct forward current away from the BJT circuit structure and to the second interconnect. However, Boyd teaches a third diode (i.e. diode D1)(fig.6B) coupled in series to the first and second diodes (implicit), coupled to the second interconnect (i.e. PAD)(fig.6B), and having a forward bias to direct forward current away from the BJT circuit structure and to the second interconnect (implicit)(refer to fig.6B). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uzawa to include the diode of Boyd to provide the advantage of minimizing leakage current in the device (refer to Boyd col. 7 line 59 to 67).
Regarding claim 9, Uzawa and Boyd teach the device of claim 1, wherein the parasitic BJT circuit structure comprises a collector (refer to Uzawa figures 5 and 21), and wherein the first interconnect is coupled to the collector (refer to Uzawa figures 5 and 21).
Regarding claim 10, Uzawa teaches an apparatus comprising: a first interconnect (refer to GND)(fig.21) to provide a voltage (implicit); a second interconnect (refer to Tout)(fig.21) to provide a signal (implicit); an electrostatic discharge (ESD) clamp structure (refer to transistor N2, diode D4, and resistor R4)(fig.21) having a first terminal coupled to the first interconnect (implicit) and a second terminal coupled to the second interconnect (implicit), wherein the ESD clamp structure comprises a parasitic NPN bipolar junction transistor (BJT) circuit structure (refer to NMOS transistor N2 and diode D4)(fig.21)(refer also to fig.3 and fig. 5) comprising a base (refer to fig.5), an emitter terminal (refer to fig.5), a collector terminal (refer to fig.5), and anti-parallel MOSFET first (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Ddn)(fig.3) and second diodes (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Ddn)(fig.3) each having an anode (implicit)(refer to fig.3), wherein the base comprises the anodes (implicit)(refer to figs. 3 and 5); however, Uzawa does not teach a third diode having a cathode coupled to the second terminal and an anode coupled to the emitter terminal of the BJT. However, Boyd teaches a third diode (i.e. diode D1)(fig.6B) having a cathode coupled to the second terminal (implicit) and an anode coupled to the emitter terminal of the BJT (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uzawa to include the diode of Boyd to provide the advantage of minimizing leakage current in the device (refer to Boyd col. 7 line 59 to 67).
Regarding claim 11, Uzawa and Boyd teach the apparatus of claim 10; however, they do not teach wherein the ESD clamp having a shunting capacity of at least 1.3V, and wherein the apparatus comprises at least one semiconductor device coupled to the first and second interconnects and having an operation voltage of 1.2V. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the ESD clamp having a shunting capacity of at least 1.3V, and wherein the apparatus comprises at least one semiconductor device coupled to the first and second interconnects and having an operation voltage of 1.2V, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Uzawa and Boyd to include wherein the ESD clamp having a shunting capacity of at least 1.3V, and wherein the apparatus comprises at least one semiconductor device coupled to the first and second interconnects and having an operation voltage of 1.2V to provide the advantage of properly sizing the ESD clamp to the circuit’s needs.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzawa and Boyd as applied to claim 1 above, and further in view of Huang et al. U.S. Patent Application 2011/0310514 (hereinafter “Huang”).
Regarding claim 2, Uzawa and Boyd teach the device of claim 1; however, they do not teach wherein the parasitic BJT circuit structure comprises: a first well structure of a first dopant type, wherein the first diode comprises first source or drain regions of a second dopant type and each extending at least partially into the first well structure, and wherein the second diode comprises second source or drain regions extending at least partially into the first well structure, and wherein the second source or drain regions are each of the second dopant type; and a first tap structure extending at least partially into the first well structure, around the first source or drain regions, and around the second source or drain regions, wherein the first tap structure is of the first dopant type. However, Huang teaches wherein the parasitic BJT circuit structure comprises: a first well structure of a first dopant type (i.e. P-well)(fig.3), wherein the first diode comprises first source or drain regions of a second dopant type (refer to N+ and D of QDN)(fig.3) and each extending at least partially into the first well structure (implicit), and wherein the second diode comprises second source or drain regions (refer to N+ and S of QDN)(fig.3) extending at least partially into the first well structure (implicit), and wherein the second source or drain regions are each of the second dopant type (implicit); and a first tap structure extending at least partially into the first well structure (refer to P+ and W of QDN)(fig.3), around the first source or drain regions (implicit), and around the second source or drain regions (implicit), wherein the first tap structure is of the first dopant type (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uzawa and Boyd to include the doping and well structure of Huang to provide the advantage of providing a common structure for an NMOS transistor with easy connections to the back gate.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzawa, Boyd, and Huang as applied to claim 2 above, and further in view of Sithanandam et al. U.S. Patent Application 2019/0319453 (hereinafter “Sithanandam”).
Regarding claim 4, Uzawa, Boyd, and Huang teach the device of claim 2; however, they do not teach the device comprising at least one fin of at least one fin field effect transistor (finFET) structure and comprising either (1) the first source or drain regions or (2) the second source or drain regions. However, Sithanandam teaches the device comprising at least one fin of at least one fin field effect transistor (finFET) structure (refer to [0044])(at least one fin is inherent in a FinFet) and comprising either (1) the first source or drain regions or (2) the second source or drain regions (refer to [0044]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uzawa, Boyd, and Huang to include the FinFet structure of Sithanandam to provide the advantage of using a smaller area of the chip for the ESD protection structure.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzawa and Boyd as applied to claim 1 above, and further in view of Disney et al. U.S. Patent Application 2008/0029820 (hereinafter “Disney”).
Regarding claim 5, Uzawa and Boyd teach the device of claim 1, wherein the first interconnect is to provide a voltage (implicit), wherein the parasitic BJT circuit structure comprises a collector terminal (refer to Uzawa fig.5) and an emitter terminal (refer to Uzawa fig.5), and wherein the first interconnect is coupled to the collector terminal (refer to Uzawa fig.5); however, they do not teach wherein the third diode comprises an n-type MOSFET diode coupled to the emitter terminal. However, Disney teaches wherein the third diode comprises an n-type MOSFET diode coupled to the emitter terminal (refer to top ESD clamp 401)(figs.4A and 4C). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uzawa and Boyd to include the MOSFET diode of Disney to provide the advantage of using equivalent structures for a diode circuit.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzawa and Boyd as applied to claim 1 above, and further in view of Worley et al. U.S. Patent No. 8,427,796 (hereinafter “Worley”).
Regarding claim 7, Uzawa and Boyd teach the device of claim 1, wherein the parasitic BJT circuit structure is a first BJT circuit structure (implicit); however, they do not teach wherein the device comprises an input-output clamp circuit coupled between the first interconnect and the second interconnect and having a parasitic second BJT circuit structure in parallel to the first BJT circuit structure, wherein the second BJT circuit structure comprises a base at a second node, and two anti-parallel diodes coupled to each other via the second node, wherein the input-output clamp circuit comprises a fourth diode having an anode coupled to the second interconnect and a cathode coupled to the second BJT circuit structure. However, Worley teaches wherein the device comprises an input-output clamp circuit (refer to positive ESD clamp 200)(fig.6) coupled between the first interconnect (i.e. IC pad 604)(fig.6) and the second interconnect (i.e. Gnd Bus)(fig.6) and having a parasitic second BJT circuit structure in parallel to the first BJT circuit structure (inherent)(refer to Np1)(fig.2), wherein the second BJT circuit structure comprises a base at a second node (inherent), and two anti-parallel diodes coupled to each other via the second node (inherent), wherein the input-output clamp circuit comprises a fourth diode (i.e. diode 218)(fig.2) having an anode coupled to the second interconnect (implicit) and a cathode coupled to the second BJT circuit structure (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uzawa and Boyd to include the input-output clamp circuit of Worley to provide the advantage of protecting from both negative and positive ESD.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzawa and further in view of Boyd and Abou-Khalil et al. U.S. Patent No. 8,503,140 (hereinafter “Abou-Khalil”).
Regarding claim 15, Uzawa teaches a system comprising: a first interconnect (refer to GND)(fig.21) and a second interconnect (refer to Tout)(fig.21); a pad-to VSS (PS) mode electrostatic discharge (ESD) clamp structure (refer to transistor N2, diode D4, and resistor R4)(fig.21) arranged to receive negative current from the first interconnect (implicit) and having a first terminal coupled to the first interconnect (implicit) and a second terminal coupled to the second interconnect (implicit), wherein the PS mode ESD clamp structure comprises a parasitic NPN bipolar junction transistor (BJT) circuit structure (refer to NMOS transistor N2 and diode D4)(fig.21)(refer also to fig.3 and fig. 5) comprising a base (refer to fig.5), an emitter terminal of an emitter (refer to fig.5), a collector terminal of a collector (refer to fig.5), and anti-parallel first (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Ddn)(fig.3) and second diodes (inherent in NMOS transistor N2)(fig.21)(refer also to parasitic diode Ddn)(fig.3) each having an anode (implicit)(refer to fig.3), wherein the base comprises the anodes (implicit)(refer to figs. 3 and 5); however, Uzawa does not teach the system being a computer implemented system, comprising a memory; and processor circuitry communicatively coupled to the memory, the processor circuitry comprising the first interconnect, second interconnect, PS mode ESD clamp structure, and a third diode having a cathode coupled to the second terminal and an anode coupled to the emitter terminal of the BJT. However, Boyd teaches a third diode (i.e. diode D1)(fig.6B) having a cathode coupled to the second terminal (implicit) and an anode coupled to the emitter terminal of the BJT (implicit). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uzawa to include the diode of Boyd to provide the advantage of minimizing leakage current in the device (refer to Boyd col. 7 line 59 to 67). However, Uzawa and Boyd do not teach the system being a computer implemented system, comprising a memory; and processor circuitry communicatively coupled to the memory, the processor circuitry comprising the first interconnect, second interconnect, PS mode ESD clamp structure, and the third diode. However, Abou-Khalil teaches the system being a computer implemented system (refer to col. 9 lines 42-58), comprising a memory (inherent)(refer to col. 9 lines 42-58); and processor circuitry communicatively coupled to the memory (inherent)(refer to col. 9 lines 42-58), the processor circuitry comprising the first interconnect, second interconnect, PS mode ESD clamp structure, and the third diode (refer to col. 9 lines 42-58). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Uzawa and Boyd to include the computer implemented system of Abou-Khalil to provide the advantage of protecting systems which are vulnerable to ESD.
Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uzawa, Boyd, and Abou-Khalil as applied to claim 15 above, and further in view of Huang.
Regarding claim 16, Uzawa, Boyd, and Abou-Khalil teach the system of claim 15; however, they do not teach wherein the PS mode ESD clamp structure comprises an isolated p-type well, wherein the emitter and collector each comprise a pair of n-doped regions spaced within an isolated p-type well, and wherein the base comprises a region of the isolated p-type well external to the n-doped regions. However, Huang teaches wherein the PS mode ESD clamp structure comprises an isolated p-type well (i.e. P-well)(fig.3), wherein the emitter and collector each comprise a pair of n-doped regions spaced within an isolated p-type well (refer to N+ region associated with D in QDN and N+ region associated with S in QDN)(fig.3), and wherein the base comprises a region of the isolated p-type well external to the n-doped regions (implicit)(refer to P+ regions associated with W in QDN)(fig.3). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Uzawa, Boyd, and Abou-Khalil to include the doping and well structure of Huang to provide the advantage of providing a common structure for an NMOS transistor with easy connections to the back gate.
Regarding claim 17, Uzawa, Boyd, Abou-Khalil, and Huang teach the system of claim 15, wherein the PS mode ESD clamp structure comprises a triple well having a p-type substrate (implicit)(refer to Huang fig.3)(refer also to Boyd fig.3D), a deep n-type well on the p-type substrate (i.e. Huang Deep N-well)(fig.3), and an isolated p-type well within the deep n-type well (i.e. Huang P-well)(fig.3).
Allowable Subject Matter
Claims 3, 6, 8, 12-14, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claim 3 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 3, especially wherein the parasitic BJT circuit structure comprises: a second well structure extending under and around the first well structure, and having the second dopant type; and a second tap structure extending at least partially into the second well structure and having the second dopant type, wherein the second tap structure extends around the first well structure.
Claim 6 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 6, especially an input-output clamp circuit coupled between the first interconnect and the second interconnect; a fourth diode coupled in series with the first resistor between the first node and the first interconnect; and a second resistor coupled between the first node and the emitter terminal.
Claim 8 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 8, especially a second resistor coupled between the second node and the first interconnect. a fifth diode coupled in series with the second resistor between the second node and the first interconnect; and a third resistor coupled between the second node and the first interconnect in parallel to the second resistor.
Claim 12 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 12, especially a first resistor coupled between the base and the emitter terminal.
Claims 13 and 14 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 13, especially a first resistor node coupled between the BJT and the third diode, and a first resistor coupled between the first resistor node and the base. Claim 14 is indicated as containing allowable subject matter based on its dependency on claim 13.
Claims 18 and 19 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 18, especially wherein the PS mode ESD clamp structure comprises a resistor coupled between the base and the first interconnect, and wherein the deep n-type well is coupled to a first resistor. Claim 19 is indicated as containing allowable subject matter based on its dependency on claim 18.
Claim 20 is indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 20, especially wherein the PS mode ESD clamp structure comprises an adjacent p-type well adjacent the deep n-type well and a p-type doped region within the adjacent p-type well, and wherein the second diode is coupled to the first interconnect via the p-type doped region.
Conclusion
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838
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