DETAILED ACTION
This Office action responds to the Amendment file on November 13, 2025, responding to the Office action mailed on August 13, 2025, has been entered. The present Office action is made with all the suggested amendments being fully considered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Amendment
Applicant’s amendments to the Drawings have overcome the objections to drawings, as previously set forth in the Non-Final Office action mailed on August 13, 2025. Accordingly, all previous drawings objections are hereby withdrawn.
Response to Arguments
Applicant’s arguments with respect to the claims filed on November 13, 2025 have been considered, but are moot in view of the new grounds of rejections.
Applicant argues the prior art of Siemieniec et al. (US 9,356,017) lacks “the source pad is shorted to the substrate”, “gate pad being insulated from the substrate”, the source pad and the gate pad not in the passive region”. However, the specification of Siemieniec et al. (US 9,356,017) embeds all these details which was not discovered earlier.
Siemieniec et al. (US 9,356,017) teach “the source 95 of the depletion mode transistor 83 includes a conductive via 96 which extends through … to the … substrate 82” (col.9/l.66-col.10/l.3 and FIG. 7) and “the source 122 of the depletion mode transistor 117' by a conductive via 131 which extends from the source 122 through … to then ... substrate 111 (col.11/ll.13-17 and FIG. 8) which indicate the source pad being shorted to the substrate either on top surface of the substrate or within/into the substrate.
Siemieniec et al. (US 9,356,017) teach “The conductive via 73 extends between the gate pad 72 … through the barrier layer … to the p-doped substrate 46 … The conductive via 73 may be electrically insulated from the Group III nitride-based layers by lining the via with an electrically insulating material, such as silicon oxide” (col.8/ll.53-62).
Siemieniec et al. (US 9,356,017) teach a depletion mode transistor 17 and a high-voltage transistor 14 having their own distinct regions as shown in FIG. 3A; “the gate pad 72 is coupled to the gate 53' of the depletion mode Group III nitride-based transistor 48 and is arranged on the passivation layer 62 on the upper surface of the non-active region 70 of the semiconductor device 40” (col.8/ll.43-46); and “the gate of the depletion mode Group III nitride based transistor is coupled to the source by a conductive via … the conductive via may be arranged in a non-active region of the semiconductor device” (col.4/l.64-col.5/l.3, col.8/ll.8-14 and FIG. 5). Hence, a person of ordinarily skilled in the semiconductor art would anticipate the source pad of the depletion mode Group III nitride based transistor is also arranged in the non-active region.
Drawings
The amended drawings replacement sheet were received on November 13, 2025. These drawings are for FIGs 7 and 8. However, the amended FIG. 8 has introduced a new reference number 121 which is considered as a new matter.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: The amended FIG. 8 contains reference number 121 which is not being used in the originally filed Specification on May 25, 202. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 7, 9-15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. (Siemieniec hereinafter) (US 9,356,017) in view of Imada (US 2013/0082336).
Regarding Claims 1-3, 6, 7, 9-15, and 17-20:
Siemieniec (see FIGS. 4A-8) teaches
{1} a lateral field-effect transistor 40/40'/80/110, comprising: a substrate 46; a device functional layer 57/58/56/60/59, arranged on the substrate, and comprising a first surface away from the substrate; wherein the lateral field-effect transistor is configured with an active region 71 and a passive region 70; a gate pad 72/53'/73 is arranged in the passive region, and the gate pad extends from the first surface to a surface 55 of the substrate; the gate pad is insulated from the substrate and the device functional layer; a source pad 51'/66 is arranged in the passive region, the source pad 95/51'/66 extends from the first surface to the surface of the substrate; the source pad is shorted to the substrate;
{2} a first slot, extending from the first surface to the surface of the substrate, wherein the gate pad comprises a first gate-pad portion 72/53' and a second gate-pad portion 53'/73; the first gate-pad portion is arranged on the first surface around a circumference of the first slot; and the second gate-pad portion fills the first slot; a dielectric layer, comprising a first dielectric-layer portion and a second dielectric-layer portion, wherein the first dielectric-layer portion is arranged on a side wall and a bottom wall of the first slot; the second dielectric-layer portion 62/91 is arranged on the first surface; a second slot, extending from the first surface to the surface of the substrate, wherein the source pad comprises a first source pad portion 95/51' and a second source pad portion 51'/66; the first source pad portion is arranged on the first surface around a circumference of the second slot; the second source pad portion fills the second portion of the second slot;
{6, 15} the transistor is a HEMT device; the device functional layer 57/58/56/60/59 comprises a plurality of active semiconductor layers formed on the substrate; two-dimensional electron gas (2DEG) 58/105/116 is defined at hetero-interface(s) between at least two (57/56)/(87/86)/(115/114) of the active semiconductor layers;
{7} the active semiconductor layers are made of III-V compound;
{9, 17} the dielectric layer is a layer made of a material selected from a group of SiO2,Si3N4 and Al2O3; {11, 19} a depth of the first slot is greater than or equal to a thickness of the device functional layer;
{12, 20} a depth of the second slot is greater than or equal to a thickness of the device functional layer; and
{14} a method for preparing a lateral field-effect transistor 40/40'/80/110, comprising: providing a device structure, comprising a substrate 46 and a device functional layer 57/58/56/60/59, wherein the device functional layer is arranged on the substrate; the device functional layer comprises a first surface away from the substrate; the device structure is configured with a first region for forming an active region 71 and a second region for forming a passive region 70; forming a first slot and a second slot extending from the first surface to the substrate in the second region; forming a dielectric layer, comprising a first dielectric-layer portion and a second dielectric- layer portion, wherein the first dielectric-layer portion is arranged on a circumference and a bottom wall of the first slot; the second dielectric-layer portion is arranged on the first surface; forming a gate pad 53'/73, comprising a first gate-pad portion 53' and a second gate-pad portion 73, wherein the first gate-pad portion is arranged on the first surface around the circumference of the first slot; the second gate-pad portion fills the first slot; forming a source pad, comprising a first source pad portion and a second source pad portion, wherein the first source pad portion of the source pad is arranged on the first surface around a circumference of the second slot; the second source pad portion of the source pad fills the second slot; wherein the source pad is shorted to the substrate.
Siemieniec (see col.4/l.64 – col.5/l.18, col.7/ll.31-34, col.8/ll.10-62, col.9/ll.13-18, col.10/ll.7-8, and col.11/ll.13-17) teaches
“the gate of the depletion mode Group III nitride based transistor is coupled to the source by a conductive via … may be arranged in a non-active region of the semiconductor device and may extend between the gate pad and the substrate, whereby the substrate is coupled with the source of the high-voltage Group III nitride transistor … the high voltage transistor 14, the depletion mode transistor 17 … are monolithically integrated in a single semiconductor body 31 … are formed from a compound semiconductor … Group III nitride-based transistor, such as gallium nitride-based HEMT”;
“the source 51' of the depletion mode Group III nitride-based transistor 48 by a conductive via 66 which extends between the source 51' and the n-doped region 53”;
“a conductive via 73 which extends between a gate pad 72 and the p-doped silicon substrate 46 in the non-active region 70 of the semiconductor device 40 … the non-active region 70 may be positioned peripheral to one or more active regions 71 … the conductive via 73 extends between the gate pad 72 … through the barrier layer 57, the channel layer 56, the transition layers 60 and the buffer layer 59 and electrically couples the gate pad 72 … to the p-doped substrate 46 … the conductive via 73 may be electrically insulated from the Group III nitride-based layers by lining the via with electrically insulating material, such as silicon oxide”;
“Each of the conductive vias 66, 67 is lined with an electrically insulating material 74 in regions of the via which extend between the two-dimensional electron gas 58 and the p-doped substrate 46”;
“the cathode 99 of the diode 84 is formed at the interface between the conductive via 96 and the n-doped substrate 82” as shown FIG. 7; and
“the cathode 130 … is coupled to the source 122 of the depletion mode transistor 117' by a conductive via 131 which extends from the source 122 through the aluminum gallium nitride layer 115 and the gallium nitride layer 144 to the n-doped substrate 111” as shown in FIG. 8.
However, Siemieniec does not explicitly teach {3} the passive region comprises a first side portion at a side of the active region; and the first slot and the second slot are both arranged on the first side portion; {10, 18} the dielectric layer is a stacked layer of Si3N4 layer(s) and Al2O3 layer(s); and {13} the source pad is made of a material selected from a group of titanium, aluminum, gold, and nickel, or an alloy of multi materials selected from a group of titanium, aluminum, gold, and nickel; and/or the gate pad is made of a material selected from a group of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or an alloy of multi materials selected from a group of nickel, gold, platinum, titanium, chromium, titanium, and tungsten, or a material of platinum silicide.
Imada (see FIG. 6 and ¶ [0045], [0055], [0056]) teaches a method of forming Group III-V HEMT device and the transistor region 101 of the AlGaN/GaN HEMT device being sandwiched between the drain pad region 102 and (the source pad region 104 and the gate pad region 103) and “a conductive material is deposited on the surface of the compound semiconductor multilayer structure 2 … may be any metal that forms an ohmic contact … at least one metal selected from the group consisting of Ti, Ni, and Pd”, “an insulating material, for example Al2O3 is deposited on the compound multilayer structure 2 … the thickness of Al2O3 … in the range of approximately 2 nm to approximately 200 nm … the gate insulating film 7 is formed”, “Alternatively, an oxide, nitride, or oxynitride of Si, Hf, Zr, Ti, Ta, or W, or any of these compounds may be selected as appropriate to deposit in multiple layers to form the gate insulating film”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Siemieniec to include the teaching of Imada to place both the gate pad and source pad on the same side of the peripheral/non-active region to meet the design requirements and to utilize other known insulating and conductive materials used with Group III-V semiconductor materials, such as silicon nitride, aluminum oxide, nickel, titanium for the multilayered insulating gate liner and the source/drain/gate pads and fillers and to manufacture the HEMT device in certain logical steps.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. (Siemieniec hereinafter) (US 9,356,017) in view of Imada (US 2013/0082336) as applied to claim 2 or 14 above, and further in view of Shimomugi et al. (Shimomugi hereinafter) (US 2019/0097563).
Regarding Claim 4:
Siemieniec in the device and method of Imada does not explicitly teach the relationship among the parasitic capacitance, parasitic resistance, and parasitic inductance of a field effect transistor and its connection with gate driving circuit.
Shimomugi (see, ¶ [0025], [0032], [0033], [0037], [0038] and FIG. 3) teaches “an elements may be used as the switching elements 5a to 5f … a wide band gap semiconductor formed of gallium nitride … can be used”, “the drive control unit 30 is input to a gate terminal of the switching element 5a via a gate driver 50 and the gate resistor Rg1”, “the gate driver 50 of the drive control circuit 39a can carry out the charging and discharging of the switching element 5a”, the gate resistor Rg1 is configured to provide the equivalent effect to that of the gate resistor Rg1 disposed inside the drive control circuit 39a”, “Lg” denotes an inductance by a signal line between the drive control circuit 39a and the switching element 5a”, “’Cgs’ denotes a gate-source capacitance component”, “the inductance Lg largely affects switching timings of the switching elements”, “the difference in the switching timing among the switching elements are suppressed by adjusting a resistance value of the gate resistor Rg1 … having a large inductance Lg … the value of the gate resistor Rg1 is made small … a time for the gate-source voltage Vgs to reach the threshold voltage differs depending on the magnitude of the inductance … a magnitude of the inductance value … is inversely related to a magnitude of the value of the gate resistor Rg1” and source is grounded.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Siemieniec in the device and method of Imada to further include the teaching of Shimomugi to place a gate driver circuit to manage the threshold voltage and switching behavior of the HEMT through a relationship among the resistor and the inductance between the gate and the gate driver circuit and the gate-source capacitance which depends on the distance between the gate pad and gate electrode, the capacitances between the gate pad and the substrate and between the gate pad and the source pad, the dimensions of the gate and source pads, etc.
The differences in the method of determining the required gate resistance and gate inductance from the gate driver to the gate pad will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such method of determining the required gate resistance and gate inductance from the gate driver to the gate pad are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the method of determining the required gate resistance and gate inductance from the gate driver to the gate pad, it would have been obvious to one of ordinary skill in the art to use the instant invention of the method of determining the required gate resistance and gate inductance from the gate driver to the gate pad to manage the desirable threshold voltage and switching behavior of the HEMT.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934, 1936s (Fed. Cir. 1990).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. (Siemieniec hereinafter) (US 9,356,017) in view of Imada (US 2013/0082336) as applied to claim 4 above, and further in view of Imada (Imada2 hereinafter) (US 2013/0334540).
Regarding Claim 5:
Siemieniec in the device and method of Imada does not explicitly teach the drain electrode is configured to be connected to a power supply and the source electrode is grounded.
Imada2 (see, ¶ [0032] and FIG. 4) teaches “a drain of the HEMT 11 which is connected between a terminal to which a power supply voltage is supplied and a ground terminal, and the electrode 4 is connected to a source of the HEMT 11”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Siemieniec in the device and method of Imada to further include the teaching of Imada2 to connect the drain of the high-voltage Group III nitride-based transistor to a power supply voltage and to connect the source of the high-voltage Group III nitride based transistor to ground when it is used as a switching element of a switching circuit.
Claims 8 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. (Siemieniec hereinafter) (US 9,356,017) in view of Imada (US 2013/0082336) as applied to claim 2 or 14 above, and further in view of Kim et al. (Kim hereinafter) (US 2021/0143097).
Regarding Claims 8 and 16:
Siemieniec in the device and method of Imana does not explicitly teach thickness of the gate insulating liner inside the trenches.
Kim (see ¶ [0003], [0044], [0045]) teaches “replacing the conventional silicon dioxide with a low-k dielectric material of the same thickness reduces parasitic capacitance noticeably, thus enabling faster switching speed”; “the liner 206 comprises one or more layer/sub-layers of dielectric material(s) … nitrogen based dielectrics, such as SiN, SiCN, SiON, or a combination thereof … has a thickness … of more than 3 nm”; “a trench bottom portion of the liner 206 … the horizontal coverage 206H … may have a thickness of about 2 nm – 5 nm … the vertical coverage 206V … may have a thickness of about 4 nm – 10 nm”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Siemieniec in the device and method of Imada to further include the teaching of Kim to select an appropriate thickness of the insulating liner/layer between the gate pads and Group III nitride material inside a trench/via in the non-active region to reduce the parasitic capacitance, to increase the switching speed, and to improve heat dissipation.
The differences in specific thickness range of the gate dielectric layer in the non-active region will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such specific thickness range of the gate dielectric layer in the non-active region are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see paragraph on page 11) of the specific thickness range of the gate dielectric layer in the non-active region, it would have been obvious to one of ordinary skill in the art to use the instant invention of the specific thickness range of the gate dielectric layer inside a trench/via in the non-active region to reduce the parasitic capacitance, to increase the switching speed, and to improve heat dissipation.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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