Prosecution Insights
Last updated: April 19, 2026
Application No. 18/202,425

ELECTRONIC DEVICE AND AN OPERATING METHOD OF THE ELECTRONIC DEVICE

Non-Final OA §103§112
Filed
May 26, 2023
Examiner
BARNIE, REXFORD N
Art Unit
2836
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
11%
Grant Probability
At Risk
1-2
OA Rounds
3y 5m
To Grant
52%
With Interview

Examiner Intelligence

Grants only 11% of cases
11%
Career Allow Rate
5 granted / 46 resolved
-57.1% vs TC avg
Strong +41% interview lift
Without
With
+40.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
62 currently pending
Career history
108
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.5%
+9.5% vs TC avg
§102
23.0%
-17.0% vs TC avg
§112
25.2%
-14.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 46 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Objections Claim 11 is objected to because of the following informalities: “tine” should be changed to “times” . Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 20 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The terms “pull-up technique” or “pull down technique” are not known terms and do not convey the applicant’s claimed invention. The applicant is advised to change the terms to be in scope with the claimed invention as shown in (see figs. 7 and 10) to “using a pair of pull up transistors” and ‘u sing a pair of pull down transistors” Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2019/0109480) in view of Jung et al. (US 10,705,593) and further in view of Lim et al. (US 10,840,7 3 0) Regarding claim 1, Hsu teaches in (see fig. 3) a connector (see fig s . 1- 2 @ 110, 128) including a voltage terminal, a detection terminal, and a data terminal (see para 0024-0025) ; a battery (125) ; a corruption detection circuit (210, 222, fig. 4)) configured to detect whether the connector is corrupted; a voltage cutoff circuit (210, 222, 122 fig. 4) connected with the voltage terminal of the connector, and configured to electrically connect the voltage terminal with an internal node (inherent) to supply voltage to internal component of a load when the corruption of the connector is not detected by the corruption detection circuit and to electrically disconnect the voltage terminal (VBus) from the internal (node (inherent) when corruption is detected by the corruption detection circuit in (see para 0024-002 9 ) a power management (224) configured to charge the battery is shown in (see fig. 3) by using voltage generated by the connector. However, Hsu et al. fails to a PMIC coupled between an internal node and a battery and configured to charge the battery by using a voltage of an internal node explicitly. Jung et al. teaches a charging system in (see fig. 4) comprising an internal node (N2) coupled to a power control module and a battery (180) wherein a PMIC (1912) is positioned between the internal node (N2) and battery (180). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teaching of Jung into that of Hsu thus making it possible to detect the state of power such as abnormality to a load and then make corrective measures if needed to protect a battery of a load or an electronic device in (see abstract of Jung et al.). The combination fails to teach a charging pin connected with the internal node, and configured to transfer a voltage of the internal node to an external device when the charging pin is connected with the external device, irrespective of whether the corruption is detected ; It’s notoriously well known in the art to couple loads to a computing device for charging as long as the computing device has a charged battery capable of powering or charging a secondary load, irrespective of whether the power from a main adapter is working or not, even though the battery of the computing would drain faster. Lim et al. teaches an electronic device in (see fig. 6A) wherein a charging pin (626) can be connected to an internal node (inherent) to an external device when the charging pin is connected with the external device wherein both devices have batteries to be charged. Note that the devices can be charged via one another without having to be coupled to the outlet irrespective of whether of a fault in a wall adapter. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lim et al. into that of the combination thus making it possible to use electronic devices (loads) to charge other loads without the need for utility power where there may not be access to AC power for convenience. Regarding claim 2, The combination including Hsu teaches detection of an overvoltage(voltage detector) for detecting voltage levels . Claim(s) 3-6 , 8 and 10 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2019/0109480) in view of Jung et al. (US 10,705,593) and further in view of Lim et al. (US 10,840,7 3 0) and further in view of OKA (US 2016/0064919). Regarding claim 3, The combination fails to wherein the corruption detection circuit is configured to: detect whether the connector is corrupted using different techniques, according to 6whether an external voltage is supplied through the voltage terminal. Oka teaches a protection circuit in conjunction with an adapter wherein different techniques or detection methods can be used to detect an abnormality or faults in (see fig. 1) to detect overvoltage, overcurrent, low voltage or rated voltage abnormalities. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of Oka into the combination thus making it possible to detect abnormalities associated with a power lines or supplies by using various techniques to ascertain corruption of an adapter. Regarding claim s 4 -6 , The combination teaches a power cutoff circuit (210) in collaboration with (110) which detects voltages and send voltage signals to a corruption detection circuit (222) (0024-0034 of Hsu et al.) Regarding claim 8 , The combination teaches periodically tested for corruption to determine status of a connector in (see para 0039) so it’s the examiner’s position that as long as the detected voltage is low than threshold or gre a t er which can be done at predetermined intervals one can determined whether there is a fault or not or the fau l t still persist . Regarding claim 10, The combination including Hsu et al. teaches in (see figs.), a resistor RT. Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2019/0109480) in view of Lim et al. (US 10,840,7 3 0). Regarding claim 19, Hsu et al. teaches a n operating method of an electronic device which is configured to be connected with a first external device through a connector (see figs. 1-3, 110, 128) , the method comprising: detecting whether the connector is corrupted; blocking an electrical connection with a voltage terminal of the connector when the connector is corrupted; establishing the electrical connection with the voltage terminal of the connector when the connector is not corrupted (see para 0024-0029) ; Hsu fails to teach a first device configured to connected to a second device through a charging means (pin) and providing a voltage to the second external device when the second external device is connected with the charging means, irrespective of whether the connector is corrupted. It’s notoriously well known in the art to couple loads to a computing device for charging as long as the computing device has a charged battery capable of powering or charging a secondary load, irrespective of whether the power from a main adapter is working or not, even though the battery of the computing would drain faster. Lim et al. teaches an electronic device in (see fig. 6A) wherein a charging pin (626) can be connected to an internal node (inherent) to an external device when the charging pin is connected with the external device wherein both devices have batteries to be charged. Note that the devices can be charged via one another without having to be coupled to the outlet irrespective of whether of a fault in a wall adapter. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Lim et al. into that of the combination thus making it possible to use electronic devices (loads) to charge other loads without the need for utility power where there may not be access to AC power for convenience. Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 2019/0109480) in view of Lim et al. (US 10,840,7 3 0) and further in view of Kim (US 2007/0177317). Regarding claim 20, The combination fails to teach using a pull up transistor(s) and a pull-down transistors to control overvoltage or faults. Kim et al. teaches in (see figs. 3-4), a control circuits capable of wherein the detecting whether the connector is corrupted includes: detecting whether the connector is corrupted (fault, overvoltage) , using a pull-down technique, when an external voltage is supplied to the voltage terminal of the connector (ground) ; and detecting whether the connector is corrupted, using a pull-up technique, when the excess external voltage is not supplied to the voltage terminal of the connector. The examiner reads the limitation as being able to control excess voltage from the utility via ground and controlling power when need be and also, in view of Hsu, if the outlet power is disconnected using an internal power (battery) to power loads by boosting power to the loads if need be. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kim into that of the combination thus making it possible to incorporate the teaching of using pull-up and pull down means to control overvoltage or excess current/voltage to protect a load. Allowable Subject Matter Claims 7, 9, 11-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 16-18 are allowed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rexford Barnie whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-7492 . The examiner can normally be reached 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /REXFORD N BARNIE/ Supervisory Patent Examiner, Art Unit 2836
Read full office action

Prosecution Timeline

May 26, 2023
Application Filed
Mar 24, 2026
Non-Final Rejection — §103, §112 (current)

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Granted
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
11%
Grant Probability
52%
With Interview (+40.9%)
3y 5m
Median Time to Grant
Low
PTA Risk
Based on 46 resolved cases by this examiner. Grant probability derived from career allow rate.

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